SECOND EDITION

Microelectronics Behzad Razavi

International Student Version

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Microelectronics Second Edition

Behzad Razavi University of California, Los Angeles

International Student Version

c 2015 John Wiley & Sons (Asia) Pte Ltd Copyright c Lepas/Shutterstock Cover image Contributing Subject Matter Experts : Dr. Anil V Nandi, BVB CET Hubli; Dr. Ramesha C. K., BITS Pilani - K. K. Birla Goa Campus; and Dr. Laxminidhi T., NIT Karnataka Surathkal Founded in 1807, John Wiley & Sons, Inc. has been a valued source of knowledge and understanding for more than 200 years, helping people around the world meet their needs and fulfill their aspirations. Our company is built on a foundation of principles that include responsibility to the communities we serve and where we live and work. In 2008, we launched a Corporate Citizenship Initiative, a global effort to address the environmental, social, economic, and ethical challenges we face in our business. Among the issues we are addressing are carbon impact, paper specifications and procurement, ethical conduct within our business and among our vendors, and community and charitable support. For more information, please visit our website: www.wiley.com/go/citizenship. All rights reserved. This book is authorized for sale in Europe, Asia, Africa and the Middle East only and may not be exported. The content is materially different than products for other markets including the authorized U.S. counterpart of this title. Exportation of this book to another region without the Publisher’s authorization may be illegal and a violation of the Publisher’s rights. The Publisher may take legal action to enforce its rights. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, website www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, website http://www.wiley.com/go/permissions. ISBN: 978-1-118-16506-5 Printed in Asia 10 9 8 7 6 5 4 3 2 1

To Angelina and Jahan, for their love and patience

About the Author Behzad Razavi received the BSEE degree from Sharif University of Technology in 1985 and the MSEE and PhDEE degrees from Stanford University in 1988 and 1992, respectively. He was with AT&T Bell Laboratories and Hewlett-Packard Laboratories until 1996. Since 1996, he has been Associate Professor and subsequently Professor of electrical engineering at University of California, Los Angeles. His current research includes wireless transceivers, frequency synthesizers, phase-locking and clock recovery for high-speed data communications, and data converters. Professor Razavi was an Adjunct Professor at Princeton University from 1992 to 1994, and at Stanford University in 1995. He served on the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC) from 1993 to 2002 and VLSI Circuits Symposium from 1998 to 2002. He has also served as Guest Editor and Associate Editor of the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems, and International Journal of High Speed Electronics. Professor Razavi received the Beatrice Winner Award for Editorial Excellence at the 1994 ISSCC, the best paper award at the 1994 European Solid-State Circuits Conference, the best panel award at the 1995 and 1997 ISSCC, the TRW Innovative Teaching Award in 1997, the best paper award at the IEEE Custom Integrated Circuits Conference in 1998, and the McGraw-Hill First Edition of the Year Award in 2001. He was the co-recipient of both the Jack Kilby Outstanding Student Paper Award and the Beatrice Winner Award for Editorial Excellence at the 2001 ISSCC. He received the Lockheed Martin Excellence in Teaching Award in 2006, the UCLA Faculty Senate Teaching Award in 2007, and the CICC Best Invited Paper Award in 2009 and 2012. He was the co-recipient of the 2012 VLSI Circuits Symposium Best Student Paper Award. He was also recognized as one of the top 10 authors in the 50-year history of ISSCC. Professor Razavi received the IEEE Donald Pederson Award in Solid-State Circuits in 2011. Professor Razavi is a Fellow of IEEE, has served as an IEEE Distinguished Lecturer, and is the author of Principles of Data Conversion System Design, RF Microelectronics (translated to Chinese, Japanese, and Korean), Design of Analog CMOS Integrated Circuits (translated to Chinese, Japanese, and Korean), Design of Integrated Circuits for Optical Communications, and Fundamentals of Microelectronics (translated to Korean and Portuguese). He is also the editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits and Phase-Locking in High-Performance Systems.

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Preface The first edition of this book was published in 2008 and has been adopted by numerous universities around the globe for undergraduate microelectronics education. Following is a detailed description of each chapter with my teaching and learning recommendations. Coverage of Chapters The material in each chapter can be decomposed into three categories: (1) essential concepts that the instructor should cover in the lecture, (2) essential skills that the students must develop but cannot be covered in the lecture due to the limited time, and (3) topics that prove useful but may be skipped according to the instructor’s preference.1 Summarized below are overviews of the chapters showing which topics should be covered in the classroom. Chapter 1: Introduction to Microelectronics The objective of this chapter is to provide the “big picture” and make the students comfortable with analog and digital signals. I spend about 30 to 45 minutes on Sections 1.1 and 1.2, leaving the remainder of the chapter (Basic Concepts) for the teaching assistants to cover in a special evening session in the first week. Chapter 2: Basic Semiconductor Physics Providing the basics of semiconductor device physics, this chapter deliberately proceeds at a slow pace, examining concepts from different angles and allowing the students to digest the material as they read on. A terse language would shorten the chapter but require that the students reread the material multiple times in their attempt to decipher the prose. It is important to note, however, that the instructor’s pace in the classroom need not be as slow as that of the chapter. The students are expected to read the details and the examples on their own so as to strengthen their grasp of the material. The principal point in this chapter is that we must study the physics of devices so as to construct circuit models for them. In a quarter system, I cover the following concepts in the lecture: electrons and holes; doping; drift and diffusion; pn junction in equilibrium and under forward and reverse bias. Chapter 3: Diode Models and Circuits This chapter serves four purposes: (1) make the students comfortable with the pn junction as a nonlinear device; (2) introduce the concept of linearizing a nonlinear model to simplify the analysis; (3) cover basic circuits with which any electrical engineer must be familiar, e.g., rectifiers and limiters; and (4) develop the skills necessary to analyze heavily-nonlinear circuits, e.g., where it is difficult to predict which diode turns on at what input voltage. Of these, the first three are essential and should be covered in the lecture, whereas the last depends on the instructor’s preference. (I cover it in my lectures.) In the interest of time, I skip a number of sections in a quarter system, e.g., voltage doublers and level shifters. Chapter 4: Physics of Bipolar Transistors Beginning with the use of a voltagecontrolled current source in an amplifier, this chapter introduces the bipolar transistor 1

Such topics are identified in the book by a footnote.

v

vi

Preface as an extension of pn junctions and derives its small-signal model. As with Chapter 2, the pace is relatively slow, but the lectures need not be. I cover structure and operation of the bipolar transistor, a very simplified derivation of the exponential characteristic, and transistor models, mentioning only briefly that saturation is undesirable. Since the T-model of limited use in analysis and carries little intuition (especially for MOS devices), I have excluded it in this book. Chapter 5: Bipolar Amplifiers This is the longest chapter in the book, building the foundation necessary for all subsequent work in electronics. Following a bottom-up approach, this chapter establishes critical concepts such as input and output impedances, biasing, and small-signal analysis. While writing the book, I contemplated decomposing Chapter 5 into two chapters, one on the above concepts and another on bipolar amplifier topologies, so that the latter could be skipped by instructors who prefer to continue with MOS circuits instead. However, teaching the general concepts does require the use of transistors, making such a decomposition difficult. Chapter 5 proceeds slowly, reinforcing, step-by-step, the concept of synthesis and exploring circuit topologies with the aid of “What if?” examples. As with Chapters 2 and 4, the instructor can move at a faster pace and leave much of the text for the students to read on their own. In a quarter system, I cover all of the chapter, frequently emphasizing the concepts illustrated in Figure 5.7 (the impedance seen looking into the base, emitter, or collector). With about two (perhaps two and half) weeks allotted to this chapter, the lectures must be precisely designed to ensure the main concepts are imparted in the classroom. Chapter 6: Physics of MOS Devices This chapter parallels Chapter 4, introducing the MOSFET as a voltage-controlled current source and deriving its characteristics. Given the limited time that we generally face in covering topics, I have included only a brief discussion of the body effect and velocity saturation and neglected these phenomena for the remainder of the book. I cover all of this chapter in our first course. Chapter 7: CMOS Amplifiers Drawing extensively upon the foundation established in Chapter 5, this chapter deals with MOS amplifiers but at a faster pace. I cover all of this chapter in our first course. Chapter 8: Operational Amplifier as a Black Box Dealing with op-amp-based circuits, this chapter is written such that it can be taught in almost any order with respect to other chapters. My own preference is to cover this chapter after amplifier topologies have been studied, so that the students have some bare understanding of the internal circuitry of op amps and its gain limitations. Teaching this chapter near the end of the first course also places op amps closer to differential amplifiers (Chapter 10), thus allowing the students to appreciate the relevance of each. I cover all of this chapter in our first course. Chapter 9: Cascodes and Current Mirrors This chapter serves as an important step toward integrated circuit design. The study of cascodes and current mirrors here also provides the necessary background for constructing differential pairs with active loads or cascodes in Chapter 10. From this chapter on, bipolar and MOS circuits are covered together and various similarities and contrasts between them are pointed out. In our second microelectronics course, I cover all of the topics in this chapter in approximately two weeks.

Preface

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Chapter 10: Differential Amplifiers This chapter deals with large-signal and smallsignal behavior of differential amplifiers. The students may wonder why we did not study the large-signal behavior of various amplifiers in Chapters 5 and 7; so I explain that the differential pair is a versatile circuit and is utilized in both regimes. I cover all of this chapter in our second course. Chapter 11: Frequency Response Beginning with a review of basic concepts such as Bode’s rules, this chapter introduces the high-frequency model of transistors and analyzes the frequency response of basic amplifiers. I cover all of this chapter in our second course. Chapter 12: Feedback and Stability Most instructors agree the students find feedback to be the most difficult topic in undergraduate microelectronics. For this reason, I have made great effort to create a step-by-step procedure for analyzing feedback circuits, especially where input and output loading effects must be taken into account. As with Chapters 2 and 5, this chapter proceeds at a deliberately slow pace, allowing the students to become comfortable with each concept and appreciate the points taught by each example. I cover all of this chapter in our second course. Chapter 13: Oscillators This new chapter deals with both discrete and integrated oscillators. These circuits are both important in real-life applications and helpful in enhancing the feedback concepts taught previously. This chapter can be comfortably covered in a semester system. Chapter 14: Output Stages and Power Amplifiers This chapter studies circuits that deliver higher power levels than those considered in previous chapters. Topologies such as push-pull stages and their limitations are analyzed. This chapter can be covered in a semester system. Chapter 15: Analog Filters This chapter provides a basic understanding of passive and active filters, preparing the student for more advanced texts on the subject. This chapter can also be comfortably covered in a semester system. Chapter 16: Digital CMOS Circuits This chapter is written for microelectronics courses that include an introduction to digital circuits as a preparation for subsequent courses on the subject. Given the time constraints in quarter and semester systems, I have excluded TTL and ECL circuits here. Chapter 17: CMOS Amplifiers This chapter is written for courses that cover CMOS circuits before bipolar circuits. As explained earlier, this chapter follows MOS device physics and, in essence, is similar to Chapter 5 but deals with MOS counterparts. Problem Sets In addition to numerous examples, each chapter offers a relatively large problem set at the end. For each concept covered in the chapter, I begin with simple, confidence-building problems and gradually raise the level of difficulty. Except for the device physics chapters, all chapters also provide a set of design problems that encourage students to work “in reverse” and select the bias and/or component values to satisfy certain requirements.

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Preface SPICE Some basic circuit theory courses may provide exposure to SPICE, but it is in the first microelectronics course that the students can appreciate the importance of simulation tools. Appendix A of this book introduces SPICE and teaches circuit simulation with the aid of numerous examples. The objective is to master only a subset of SPICE commands that allow simulation of most circuits at this level. Due to the limited lecture time, I ask the teaching assistants to cover SPICE in a special evening session around the middle of the quarter—just before I begin to assign SPICE problems. Most chapters contain SPICE problems, but I prefer to introduce SPICE only in the second half of the first course (toward the end of Chapter 5). This is for two reasons: (1) the students must first develop their basic understanding and analytical skills, i.e., the homeworks must exercise the fundamental concepts; and (2) the students appreciate the utility of SPICE much better if the circuit contains a relatively large number of devices (e.g., 5-10). Homeworks and Exams In a quarter system, I assign four homeworks before the midterm and four after. Mostly based on the problem sets in the book, the homeworks contain moderate to difficult problems, thereby requiring that the students first go over the easier problems in the book on their own. The exam questions are typically “twisted” versions of the problems in the book. To encourage the students to solve all of the problems at the end of each chapter, I tell them that one of the problems in the book is given in the exam verbatim. The exams are openbook, but I suggest to the students to summarize the important equations on one sheet of paper.

Behzad Razavi

Acknowledgments This book has taken four years to write and benefited from contributions of many individuals. I wish to thank the following for their input at various stages of this book’s development: David Allstot (University of Washington), Joel Berlinghieri, Sr. (The Citadel), Bernhard Boser (University of California, Berkeley), Charles Bray (University of Memphis), Marc Cahay (University of Cincinnati), Norman Cox (University of Missouri, Rolla), James Daley (University of Rhode Island), Tranjan Farid (University of North Carolina at Charlotte), Paul Furth (New Mexico State University), Roman Genov (University of Toronto), Maysam Ghovanloo (North Carolina State University), Gennady Gildenblat (Pennsylvania State University), Ashok Goel (Michigan Technological University), Michael Gouzman (SUNY, Stony Brook), Michael Green (University of California, Irvine), Sotoudeh Hamedi-Hagh (San Jose State University), Reid Harrison (University of Utah), Payam Heydari (University of California, Irvine), Feng Hua (Clarkson University), Marian Kazmierchuk (Wright State University), Roger King (University of Toledo), Edward Kolesar (Texas Christian University), Ying-Cheng Lai (Arizona State University), Daniel Lau (University of Kentucky, Lexington), Stanislaw Legowski (University of Wyoming), Philip Lopresti (University of Pennsylvania), Mani Mina (Iowa State University), James Morris (Portland State University), Khalil Najafi (University of Michigan), Homer Nazeran (University of Texas, El Paso), Tamara Papalias (San Jose State University), Matthew Radmanesh (California State University, Northridge), Angela Rasmussen (University of Utah), Sal R. Riggio, Jr. (Pennsylvania State University), Ali Sheikholeslami (University of Toronto), Kalpathy B. Sundaram (University of Central Florida), Yannis Tsividis (Columbia University), Thomas Wu (University of Central Florida), Darrin Young (Case Western Reserve University). I am grateful to Naresh Shanbhag (University of Illinois, Urbana-Champaign) for test driving a draft of the book in a course and providing valuable feedback. The following UCLA students diligently prepared the solutions manual: Lawrence Au, Hamid Hatamkhani, Alireza Mehrnia, Alireza Razzaghi, William Wai-Kwok Tang, and Ning Wang. Ning Wang also produced the Powerpoint slides for the entire book. Eudean Sun (University of California, Berkeley) and John Tyler (Texas A&M University) served as accuracy checkers. I would like to thank them for their hard work. I thank my publisher, Catherine Shultz, for her dedication and exuberance. Lucille Buonocore, Carmen Hernandez, Dana Kellogg, Madelyn Lesure, Christopher Ruel, Kenneth Santor, Lauren Sapira, Daniel Sayre, Gladys Soto, and Carolyn Weisman of Wiley and Bill Zobrist (formerly with Wiley) also deserve my gratitude. In addition, I wish to thank Jessica Knecht and Joyce Poh for their hard work on the second edition. My wife, Angelina, typed the entire book and kept her humor as this project dragged on. My deepest thanks go to her. Behzad Razavi

ix

Contents 1 INTRODUCTION TO MICROELECTRONICS

1

1.1 Electronics versus Microelectronics 1 1.2 Examples of Electronic Systems 2 1.2.1 1.2.2 1.2.3

Cellular Telephone 2 Digital Camera 5 Analog Versus Digital 7

2 BASIC PHYSICS OF SEMICONDUCTORS 9 2.1 Semiconductor Materials and Their Properties 10 2.1.1 2.1.2 2.1.3

Charge Carriers in Solids 10 Modification of Carrier Densities 13 Transport of Carriers 15

2.2 pn Junction 23 2.2.1 2.2.2 2.2.3 2.2.4

pn Junction in Equilibrium 24 pn Junction Under Reverse Bias 29 pn Junction Under Forward Bias 33 I/V Characteristics 36

2.3 Reverse Breakdown 41 2.3.1 2.3.2

Zener Breakdown 42 Avalanche Breakdown 42

Problems 43 Spice Problems 45

3 DIODE MODELS AND CIRCUITS 46 3.1 Ideal Diode 46 3.1.1 3.1.2 3.1.3

Initial Thoughts 46 Ideal Diode 48 Application Examples 52

3.2 pn Junction as a Diode 57

3.3 Additional Examples 59 3.4 Large-Signal and Small-Signal Operation 64 3.5 Applications of Diodes 73 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5

Half-Wave and Full-Wave Rectifiers 73 Voltage Regulation 86 Limiting Circuits 88 Voltage Doublers 92 Diodes as Level Shifters and Switches 96

Problems 99 Spice Problems 106

4 PHYSICS OF BIPOLAR TRANSISTORS 107 4.1 General Considerations 107 4.2 Structure of Bipolar Transistor 109 4.3 Operation of Bipolar Transistor in Active Mode 110 4.3.1 4.3.2

Collector Current 113 Base and Emitter Currents 116

4.4 Bipolar Transistor Models and Characteristics 118 4.4.1 4.4.2 4.4.3

Large-Signal Model 118 I/V Characteristics 120 Concept of Transconductance 122

4.4.4 4.4.5

Small-Signal Model 124 Early Effect 129

4.5 Operation of Bipolar Transistor in Saturation Mode 135 4.6 The PNP Transistor 138 4.6.1 4.6.2 4.6.3

Structure and Operation 139 Large-Signal Model 139 Small-Signal Model 142

Problems 145 Spice Problems 151

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Contents

5 BIPOLAR AMPLIFIERS

Problems 274 Spice Problems 280

153

5.1 General Considerations 153 5.1.1 5.1.2 5.1.3

Input and Output Impedances 154 Biasing 158 DC and Small-Signal Analysis 158

7 CMOS AMPLIFIERS

7.1 General Considerations 281 7.1.1

5.2 Operating Point Analysis and Design 160 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5

Simple Biasing 162 Resistive Divider Biasing 164 Biasing with Emitter Degeneration 167 Self-Biased Stage 171 Biasing of PNP Transistors 174

7.1.2 7.1.3

5.3.2 5.3.3

Common-Emitter Topology 179 Common-Base Topology 205 Emitter Follower 222

Problems 230 Spice Problems 242

7.2.1 7.2.2 7.2.3 7.2.4

6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6

Qualitative Analysis 247 Derivation of I-V Characteristics 253 Channel-Length Modulation 262 MOS Transconductance 264 Velocity Saturation 266 Other Second-Order Effects 266

7.2.5 7.3.1

CG Stage with Biasing 302

7.4 Source Follower 303 7.4.1 7.4.2

Source Follower Core 304 Source Follower with Biasing 306

Problems 308 Spice Problems 319

8 OPERATIONAL AMPLIFIER AS A BLACK BOX 321 8.1 8.2

General Considerations 322 Op-Amp-Based Circuits 324 8.2.1 8.2.2 8.2.3 8.2.4

8.3

8.4

Noninverting Amplifier 324 Inverting Amplifier 326 Integrator and Differentiator 329 Voltage Adder 335

Nonlinear Functions 336 8.3.1 8.3.2 8.3.3

Large-Signal Model 267 Small-Signal Model 269

6.4 PMOS Transistor 270 6.5 CMOS Technology 273 6.6 Comparison of Bipolar and MOS Devices 273

CS Core with Biasing 295

7.3 Common-Gate Stage 297

6.3 MOS Device Models 267 6.3.1 6.3.2

CS Core 286 CS Stage with Current-Source Load 289 CS Stage with Diode-Connected Load 290 CS Stage with Degeneration 292

6 PHYSICS OF MOS TRANSISTORS 244 6.1 Structure of MOSFET 244 6.2 Operation of MOSFET 247

MOS Amplifier Topologies 281 Biasing 281 Realization of Current Sources 285

7.2 Common-Source Stage 286

5.3 Bipolar Amplifier Topologies 178 5.3.1

281

Precision Rectifier 336 Logarithmic Amplifier 338 Square-Root Amplifier 339

Op Amp Nonidealities 339 8.4.1 8.4.2 8.4.3

DC Offsets 339 Input Bias Current 342 Speed Limitations 346

Contents 8.4.4

8.5

Finite Input and Output Impedances 350

Design Examples 351 Problems 353 Spice Problems 358

9 CASCODE STAGES AND CURRENT MIRRORS 359 9.1

Cascode Stage 359 9.1.1 9.1.2

9.2

Cascode as a Current Source 359 Cascode as an Amplifier 366

Current Mirrors 375 9.2.1 9.2.2 9.2.3

Initial Thoughts 375 Bipolar Current Mirror 376 MOS Current Mirror 385

Problems 388 Spice Problems 397

10 DIFFERENTIAL AMPLIFIERS 399 10.1 General Considerations 399 10.1.1 Initial Thoughts 399 10.1.2 Differential Signals 401 10.1.3 Differential Pair 404

10.2 Bipolar Differential Pair 404 10.2.1 Qualitative Analysis 404 10.2.2 Large-Signal Analysis 410 10.2.3 Small-Signal Analysis 414

10.3 MOS Differential Pair 420 10.3.1 Qualitative Analysis 421 10.3.2 Large-Signal Analysis 425 10.3.3 Small-Signal Analysis 429

10.4 Cascode Differential Amplifiers 433 10.5 Common-Mode Rejection 437 10.6 Differential Pair with Active Load 441 10.6.1 Qualitative Analysis 442 10.6.2 Quantitative Analysis 444

Problems 449 Spice Problems 459

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11 FREQUENCY RESPONSE 460

11.1 Fundamental Concepts 460 11.1.1 General Considerations 460 11.1.2 Relationship Between Transfer Function and Frequency Response 463 11.1.3 Bode’s Rules 466 11.1.4 Association of Poles with Nodes 467 11.1.5 Miller’s Theorem 469 11.1.6 General Frequency Response 472

11.2 High-Frequency Models of Transistors 475 11.2.1 High-Frequency Model of Bipolar Transistor 475 11.2.2 High-Frequency Model of MOSFET 476 11.2.3 Transit Frequency 478

11.3 Analysis Procedure 480 11.4 Frequency Response of CE and CS Stages 480 11.4.1 Low-Frequency Response 480 11.4.2 High-Frequency Response 481 11.4.3 Use of Miller’s Theorem 482 11.4.4 Direct Analysis 484 11.4.5 Input Impedance 487

11.5 Frequency Response of CB and CG Stages 488 11.5.1 Low-Frequency Response 488 11.5.2 High-Frequency Response 489

11.6 Frequency Response of Followers 491 11.6.1 Input and Output Impedances 495

11.7 Frequency Response of Cascode Stage 498 11.7.1 Input and Output Impedances 502

11.8 Frequency Response of Differential Pairs 503

xiv

Contents 11.8.1 Common-Mode Frequency Response 504

Problems 506 Spice Problems 512

12 FEEDBACK

513

12.1 General Considerations 513 12.1.1 Loop Gain 516

12.2 Properties of Negative Feedback 518 12.2.1 Gain Desensitization 518 12.2.2 Bandwidth Extension 519 12.2.3 Modification of I/O Impedances 521 12.2.4 Linearity Improvement 525

12.3 Types of Amplifiers 526 12.3.1 Simple Amplifier Models 526

12.3.2 Examples of Amplifier Types 527

Problems 577 Spice Problems 587

13 OSCILLATORS

588

13.1 General Considerations 588 13.2 Ring Oscillators 591 13.3 LC Oscillators 595 13.3.1 Parallel LC Tanks 595 13.3.2 Cross-Coupled Oscillator 599 13.3.3 Colpitts Oscillator 601

13.4 Phase Shift Oscillator 604 13.5 Wien-Bridge Oscillator 607 13.6 Crystal Oscillators 608 13.6.1 Crystal Model 608 13.6.2 Negative-Resistance Circuit 610 13.6.3 Crystal Oscillator Implementation 611

Problems 614 Spice Problems 617

12.4 Sense and Return Techniques 529 14 OUTPUT STAGES AND 12.5 Polarity of Feedback 532 POWER AMPLIFIERS 619 12.6 Feedback Topologies 534 12.6.1 Voltage-Voltage 14.1 General Considerations 619 Feedback 534 14.2 Emitter Follower as Power 12.6.2 Voltage-Current Amplifier 620 Feedback 539 14.3 Push-Pull Stage 623 12.6.3 Current-Voltage 14.4 Improved Push-Pull Stage 626 Feedback 542 12.6.4 Current-Current Feedback 547

12.7 Effect of Nonideal I/O Impedances 550 12.7.1 Inclusion of I/O Effects 551

12.8 Stability in Feedback Systems 563 12.8.1 12.8.2 12.8.3 12.8.4 12.8.5

Review of Bode’s Rules 563 Problem of Instability 565 Stability Condition 568 Phase Margin 571 Frequency Compensation 573

12.8.6 Miller Compensation 576

14.4.1 Reduction of Crossover Distortion 626 14.4.2 Addition of CE Stage 629

14.5 Large-Signal Considerations 633 14.5.1 Biasing Issues 633 14.5.2 Omission of PNP Power Transistor 634 14.5.3 High-Fidelity Design 637

14.6 Short-Circuit Protection 638 14.7 Heat Dissipation 638 14.7.1 Emitter Follower Power Rating 639 14.7.2 Push-Pull Stage Power Rating 640 14.7.3 Thermal Runaway 641

14.8 Efficiency 643

Contents 14.8.1 Efficiency of Emitter Follower 643 14.8.2 Efficiency of Push-Pull Stage 644

14.9 Power Amplifier Classes 645 Problems 646 Spice Problems 650

15 ANALOG FILTERS

651

15.1 General Considerations 651 15.1.1 15.1.2 15.1.3 15.1.4

Filter Characteristics 652 Classification of Filters 653 Filter Transfer Function 656 Problem of Sensitivity 660

15.2 First-Order Filters 661 15.3 Second-Order Filters 664 15.3.1 Special Cases 664 15.3.2 RLC Realizations 668

15.4 Active Filters 673 15.4.1 Sallen and Key Filter 673 15.4.2 Integrator-Based Biquads 679 15.4.3 Biquads Using Simulated Inductors 682

15.5 Approximation of Filter Response 687 15.5.1 Butterworth Response 688 15.5.2 Chebyshev Response 692

Problems 697 Spice Problems 701

16 DIGITAL CMOS CIRCUITS 702 16.1 General Considerations 702 16.1.1 Static Characterization of Gates 703 16.1.2 Dynamic Characterization of Gates 710 16.1.3 Power-Speed Trade-Off 713

16.2 CMOS Inverter 714 16.2.1 Initial Thoughts 715 16.2.2 Voltage Transfer Characteristic 717

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16.2.3 Dynamic Characteristics 723 16.2.4 Power Dissipation 728

16.3 CMOS NOR and NAND Gates 731 16.3.1 NOR Gate 732 16.3.2 NAND Gate 735

Problems 736 Spice Problems 740

17 CMOS AMPLIFIERS

742

17.1 General Considerations 742 17.1.1 Input and Output Impedances 743 17.1.2 Biasing 747 17.1.3 DC and Small-Signal Analysis 748

17.2 Operating Point Analysis and Design 749 17.2.1 Simple Biasing 751 17.2.2 Biasing with Source Degeneration 753 17.2.3 Self-Biased Stage 756 17.2.4 Biasing of PMOS Transistors 757 17.2.5 Realization of Current Sources 758

17.3 CMOS Amplifier Topologies 759 17.4 Common-Source Topology 760 17.4.1 CS Stage with Current-Source Load 765 17.4.2 CS Stage with Diode-Connected Load 766 17.4.3 CS Stage with Source Degeneration 767 17.4.4 Common-Gate Topology 779

17.4.5 Source Follower 790

Problems 796 Spice Problems 806

Appendix A INTRODUCTION TO SPICE 809 Index 829

Chapter

1

Introduction to Microelectronics

Over the past five decades, microelectronics has revolutionized our lives. While beyond the realm of possibility a few decades ago, cellphones, digital cameras, laptop computers, and many other electronic products have now become an integral part of our daily affairs. Learning microelectronics can be fun. As we learn how each device operates, how devices comprise circuits that perform interesting and useful functions, and how circuits form sophisticated systems, we begin to see the beauty of microelectronics and appreciate the reasons for its explosive growth. This chapter gives an overview of microelectronics so as to provide a context for the material presented in this book. We introduce examples of microelectronic systems and identify important circuit “functions” that they employ. We also provide a review of basic circuit theory to refresh the reader’s memory.

1.1

ELECTRONICS VERSUS MICROELECTRONICS The general area of electronics began about a century ago and proved instrumental in the radio and radar communications used during the two world wars. Early systems incorporated “vacuum tubes,” amplifying devices that operated with the flow of electrons between plates in a vacuum chamber. However, the finite lifetime and the large size of vacuum tubes motivated researchers to seek an electronic device with better properties. The first transistor was invented in the 1940s and rapidly displaced vacuum tubes. It exhibited a very long (in principle, infinite) lifetime and occupied a much smaller volume (e.g., less than 1 cm3 in packaged form) than vacuum tubes did. But it was not until 1960s that the field of microelectronics, i.e., the science of integrating many transistors on one chip, began. Early “integrated circuits” (ICs) contained only a handful of devices, but advances in the technology soon made it possible to dramatically increase the complexity of “microchips.”

Example 1.1

Today’s microprocessors contain about 100 million transistors in a chip area of approximately 3 cm × 3 cm. (The chip is a few hundred microns thick.) Suppose integrated circuits were not invented and we attempted to build a processor using 100 million “discrete” transistors. If each device occupies a volume of 3 mm × 3 mm × 3 mm, determine the minimum volume for the processor. What other issues would arise in such an implementation?

1

2

Chapter 1 Introduction to Microelectronics

Solution

The minimum volume is given by 27 mm3 × 108 , i.e., a cube 1.4 m on each side! Of course, the wires connecting the transistors would increase the volume substantially. In addition to occupying a large volume, this discrete processor would be extremely slow; the signals would need to travel on wires as long as 1.4 m! Furthermore, if each discrete transistor costs 1 cent and weighs 1 g, each processor unit would be priced at one million dollars and weigh 100 tons!

Exercise

How much power would such a system consume if each transistor dissipates 10 μW?

This book deals mostly with microelectronics while providing sufficient foundation for general (perhaps discrete) electronic systems as well.

1.2

EXAMPLES OF ELECTRONIC SYSTEMS At this point, we introduce two examples of microelectronic systems and identify some of the important building blocks that we should study in basic electronics. 1.2.1 Cellular Telephone Cellular telephones were developed in the 1980s and rapidly became popular in the 1990s. Today’s cellphones contain a great deal of sophisticated analog and digital electronics that lie well beyond the scope of this book. But our objective here is to see how the concepts described in this book prove relevant to the operation of a cellphone. Suppose you are speaking with a friend on your cellphone. Your voice is converted to an electric signal by a microphone and, after some processing, transmitted by the antenna. The signal produced by your antenna is picked up by your friend’s receiver and, after some processing, applied to the speaker [Fig. 1.1(a)]. What goes on in these black boxes? Why are they needed?

Transmitter (TX)

Receiver (RX)

Microphone

Speaker ?

?

(a) Figure 1.1

(b)

(a) Simplified view of a cellphone, (b) further simplification of transmit and receive

paths.

Let us attempt to omit the black boxes and construct the simple system shown in Fig. 1.1(b). How well does this system work? We make two observations. First, our voice contains frequencies from 20 Hz to 20 kHz (called the “voice band”). Second, for an antenna to operate efficiently, i.e., to convert most of the electrical signal to electromagnetic

1.2 Examples of Electronic Systems

3

radiation, its dimension must be a significant fraction (e.g., 25%) of the wavelength. Unfortunately, a frequency range of 20 Hz to 20 kHz translates to a wavelength1 of 1.5 × 107 m to 1.5 × 104 m, requiring gigantic antennas for each cellphone. Conversely, to obtain a reasonable antenna length, e.g., 5 cm, the wavelength must be around 20 cm and the frequency around 1.5 GHz. How do we “convert” the voice band to a gigahertz center frequency? One possible approach is to multiply the voice signal, x(t), by a sinusoid, A cos(2π fc t) [Fig. 1.2(a)]. Since multiplication in the time domain corresponds to convolution in the frequency domain, and since the spectrum of the sinusoid consists of two impulses at ±f c , the voice spectrum is simply shifted (translated) to ±f c [Fig. 1.2(b)]. Thus, if f c = 1 GHz, the output occupies a bandwidth of 40 kHz centered at 1 GHz. This operation is an example of “amplitude modulation.”2

Voice Signal

Output Waveform

A cos(2 π f C t )

x (t )

t

t

t

(a)

X (f )

Spectrum of Cosine

Output Spectrum

–fC

–fC

+20 kHz

–20 kHz

Voice Spectrum f

+fC f

+fC

f

(b)

(a) Multiplication of a voice signal by a sinusoid, (b) equivalent operation in the frequency domain.

Figure 1.2

We therefore postulate that the black box in the transmitter of Fig. 1.1(a) contains a multiplier,3 as depicted in Fig. 1.3(a). But two other issues arise. First, the cellphone must deliver a relatively large voltage swing (e.g., 20 Vpp ) to the antenna so that the radiated power can reach across distances of several kilometers, thereby requiring a “power amplifier” between the multiplier and the antenna. Second, the sinusoid, A cos 2π fc t, must be produced by an “oscillator.” We thus arrive at the transmitter architecture shown in Fig. 1.3(b).

1

Recall that the wavelength is equal to the (light) velocity divided by the frequency. Cellphones in fact use other types of modulation to translate the voice band to higher frequencies. 3 Also called a “mixer” in high-frequency electronics. 2

4

Chapter 1 Introduction to Microelectronics Power Amplifier

A cos(2 π f C t )

Oscillator

(a) Figure 1.3

(b)

(a) Simple transmitter, (b) more complete transmitter.

Let us now turn our attention to the receive path of the cellphone, beginning with the simple realization illustrated in Fig. 1.1(b). Unfortunately, this topology fails to operate with the principle of modulation: if the signal received by the antenna resides around a gigahertz center frequency, the audio speaker cannot produce meaningful information. In other words, a means of translating the spectrum back to zero center frequency is necessary. For example, as depicted in Fig. 1.4(a), multiplication by a sinusoid, A cos(2π fc t), translates the spectrum to left and right by fc , restoring the original voice band. The newly-generated components at ±2fc can be removed by a low-pass filter. We thus arrive at the receiver topology shown in Fig. 1.4(b).

Output Spectrum Spectrum of Cosine

Received Spectrum

–fC

+fC

f

–fC

+fC f

–2 f C

+2 f C

f

(a)

Low-Noise Amplifier

Amplifier Low-Pass Filter

Low-Pass Filter

Oscillator

Oscillator (b)

(c)

(a) Translation of modulated signal to zero center frequency, (b) simple receiver, (b) more complete receiver.

Figure 1.4

Our receiver design is still incomplete. The signal received by the antenna can be as low as a few tens of microvolts whereas the speaker may require swings of several tens

1.2 Examples of Electronic Systems

5

or hundreds of millivolts. That is, the receiver must provide a great deal of amplification (“gain”) between the antenna and the speaker. Furthermore, since multipliers typically suffer from a high “noise” and hence corrupt the received signal, a “low-noise amplifier” must precede the multiplier. The overall architecture is depicted in Fig. 1.4(c). Today’s cellphones are much more sophisticated than the topologies developed above. For example, the voice signal in the transmitter and the receiver is applied to a digital signal processor (DSP) to improve the quality and efficiency of the communication. Nonetheless, our study reveals some of the fundamental building blocks of cellphones, e.g., amplifiers, oscillators, and filters, with the last two also utilizing amplification. We therefore devote a great deal of effort to the analysis and design of amplifiers. Having seen the necessity of amplifiers, oscillators, and multipliers in both transmit and receive paths of a cellphone, the reader may wonder if “this is old stuff” and rather trivial compared to the state of the art. Interestingly, these building blocks still remain among the most challenging circuits in communication systems. This is because the design entails critical trade-offs between speed (gigahertz center frequencies), noise, power dissipation (i.e., battery lifetime), weight, cost (i.e., price of a cellphone), and many other parameters. In the competitive world of cellphone manufacturing, a given design is never “good enough” and the engineers are forced to further push the above trade-offs in each new generation of the product.

1.2.2 Digital Camera Another consumer product that, by virtue of “going electronic,” has dramatically changed our habits and routines is the digital camera. With traditional cameras, we received no immediate feedback on the quality of the picture that was taken, we were very careful in selecting and shooting scenes to avoid wasting frames, we needed to carry bulky rolls of film, and we would obtain the final result only in printed form. With digital cameras, on the other hand, we have resolved these issues and enjoy many other features that only electronic processing can provide, e.g., transmission of pictures through cellphones or ability to retouch or alter pictures by computers. In this section, we study the operation of the digital camera. The “front end” of the camera must convert light to electricity, a task performed by an array (matrix) of “pixels.”4 Each pixel consists of an electronic device (a “photodiode”) that produces a current proportional to the intensity of the light that it receives. As illustrated in Fig. 1.5(a), this current flows through a capacitance, CL , for a certain period of time, thereby developing a proportional voltage across it. Each pixel thus provides a voltage proportional to the “local” light density. Now consider a camera with, say, 6.25 million pixels arranged in a 2500 × 2500 array [Fig. 1.5(b)]. How is the output voltage of each pixel sensed and processed? If each pixel contains its own electronic circuitry, the overall array occupies a very large area, raising the cost and the power dissipation considerably. We must therefore “time-share” the signal processing circuits among pixels. To this end, we follow the circuit of Fig. 1.5(a) with a simple, compact amplifier and a switch (within the pixel) [Fig. 1.5(c)]. Now, we connect a wire to the outputs of all 2500 pixels in a “column,” turn on only one switch at a time, and apply the corresponding voltage to the “signal processing” block outside the column.

4

The term “pixel” is an abbreviation of “picture cell.”

6

Chapter 1 Introduction to Microelectronics Amplifier

25

00

C

ol

um

2500 Rows

ns

I Diode Light CL

V out

Signal Processing

Photodiode (a) Figure 1.5

(b)

(c)

(a) Operation of a photodiode, (b) array of pixels in a digital camera, (c) one column of

the array.

The overall array consists of 2500 of such columns, with each column employing a dedicated signal processing block.

Example 1.2

A digital camera is focused on a chess board. Sketch the voltage produced by one column as a function of time.

Solution

The pixels in each column receive light only from the white squares [Fig. 1.6(a)]. Thus, the column voltage alternates between a maximum for such pixels and zero for those receiving no light. The resulting waveform is shown in Fig. 1.6(b).

V column

V column t

(a) Figure 1.6

Exercise

(b)

(c)

(a) Chess board captured by a digital camera, (b) voltage waveform of one column.

Plot the voltage if the first and second squares in each row have the same color.

1.2 Examples of Electronic Systems

7

What does each signal processing block do? Since the voltage produced by each pixel is an analog signal and can assume all values within a range, we must first “digitize” it by means of an “analog-to-digital converter” (ADC). A 6.25 megapixel array must thus incorporate 2500 ADCs. Since ADCs are relatively complex circuits, we may time-share one ADC between every two columns (Fig. 1.7), but requiring that the ADC operate twice as fast (why?). In the extreme case, we may employ a single, very fast ADC for all 2500 columns. In practice, the optimum choice lies between these two extremes.

ADC Figure 1.7

Sharing one ADC between two columns of a pixel array.

Once in the digital domain, the “video” signal collected by the camera can be manipulated extensively. For example, to “zoom in,” the digital signal processor (DSP) simply considers only a section of the array, discarding the information from the remaining pixels. Also, to reduce the required memory size, the processor “compresses” the video signal. The digital camera exemplifies the extensive use of both analog and digital microelectronics. The analog functions include amplification, switching operations, and analog-todigital conversion, and the digital functions consist of subsequent signal processing and storage. 1.2.3 Analog Versus Digital Amplifiers and ADCs are examples of analog functions, circuits that must process each point on a waveform (e.g., a voice signal) with great care to avoid effects such as noise and “distortion.” By contrast, digital circuits deal with binary levels (ONEs and ZEROs) and, evidently, contain no analog functions. The reader may then say, “I have no intention of working for a cellphone or camera manufacturer and, therefore, need not learn about analog circuits.” In fact, with digital communications, digital signal processors, and every other function becoming digital, is there any future for analog design? Well, some of the assumptions in the above statements are incorrect. First, not every function can be realized digitally. The architectures of Figs. 1.3 and 1.4 must employ lownoise and low-power amplifiers, oscillators, and multipliers regardless of whether the actual communication is in analog or digital form. For example, a 20-μV signal (analog or digital)

8

Chapter 1 Introduction to Microelectronics received by the antenna cannot be directly applied to a digital gate. Similarly, the video signal collectively captured by the pixels in a digital camera must be processed with low noise and distortion before it appears in the digital domain. Second, digital circuits require analog expertise as the speed increases. Figure 1.8 exemplifies this point by illustrating two binary data waveforms, one at 100 Mb/s and another at 1 Gb/s. The finite risetime and falltime of the latter raises many issues in the operation of gates, flipflops, and other digital circuits, necessitating great attention to each point on the waveform.

10 ns

x 1 (t ) 1 ns

t

x 2 (t ) t Figure 1.8

Data waveforms at 100 Mb/s and 1 Gb/s.

Chapter

2

Basic Physics of Semiconductors

Microelectronic circuits are based on complex semiconductor structures that have been under active research for the past six decades. While this book deals with the analysis and design of circuits, we should emphasize at the outset that a good understanding of devices is essential to our work. The situation is similar to many other engineering problems, e.g., one cannot design a high-performance automobile without a detailed knowledge of the engine and its limitations. Nonetheless, we do face a dilemma. Our treatment of device physics must contain enough depth to provide adequate understanding, but must also be sufficiently brief to allow quick entry into circuits. This chapter accomplishes this task. Our ultimate objective in this chapter is to study a fundamentally important and versatile device called the “diode.” However, just as we need to eat our broccoli before having dessert, we must develop a basic understanding of “semiconductor” materials and their current conduction mechanisms before attacking diodes. In this chapter, we begin with the concept of semiconductors and study the movement of charge (i.e., the flow of current) in them. Next, we deal with the “pn junction,” which also serves as diode, and formulate its behavior. Our ultimate goal is to represent the device by a circuit model (consisting of resistors, voltage or current sources, capacitors, etc.), so that a circuit using such a device can be analyzed easily. The outline is shown below.

Semiconductors • Charge Carriers • Doping • Transport of Carriers

PN Junction

➤

• Structure • Reverse and Forward Bias Conditions • I/V Characteristics • Circuit Models

It is important to note that the task of developing accurate models proves critical for all microelectronic devices. The electronics industry continues to place greater demands

9

10

Chapter 2 Basic Physics of Semiconductors on circuits, calling for aggressive designs that push semiconductor devices to their limits. Thus, a good understanding of the internal operation of devices is necessary.1

2.1

SEMICONDUCTOR MATERIALS AND THEIR PROPERTIES Since this section introduces a multitude of concepts, it is useful to bear a general outline in mind: Charge Carriers in Solids Crystal Structure Bandgap Energy Holes Figure 2.1

Modification of Carrier Densities Intrinsic Semiconductors Extrinsic Semiconductors Doping

Transport of Carriers Diffusion Drift

Outline of this section.

This outline represents a logical thought process: (a) we identify charge carriers in solids and formulate their role in current flow; (b) we examine means of modifying the density of charge carriers to create desired current flow properties; (c) we determine current flow mechanisms. These steps naturally lead to the computation of the current/voltage (I/V) characteristics of actual diodes in the next section. 2.1.1 Charge Carriers in Solids Recall from basic chemistry that the electrons in an atom orbit the nucleus in different “shells.” The atom’s chemical activity is determined by the electrons in the outermost shell, called “valence” electrons, and how complete this shell is. For example, neon exhibits a complete outermost shell (with eight electrons) and hence no tendency for chemical reactions. On the other hand, sodium has only one valence electron, ready to relinquish it, and chloride has seven valence electrons, eager to receive one more. Both elements are therefore highly reactive. The above principles suggest that atoms having approximately four valence electrons fall somewhere between inert gases and highly volatile elements, possibly displaying interesting chemical and physical properties. Shown in Fig. 2.2 is a section of the periodic table containing a number of elements with three to five valence electrons. As the most popular material in microelectronics, silicon merits a detailed analysis.2 Covalent Bonds A silicon atom residing in isolation contains four valence electrons [Fig. 2.3(a)], requiring another four to complete its outermost shell. If processed properly, the silicon material can form a “crystal” wherein each atom is surrounded by exactly four others [Fig. 2.3(b)]. As a result, each atom shares one valence electron with its neighbors, thereby completing its own shell and those of the neighbors. The “bond” thus formed between atoms is called a “covalent bond” to emphasize the sharing of valence electrons. The uniform crystal depicted in Fig. 2.3(b) plays a crucial role in semiconductor devices. But, does it carry current in response to a voltage? At temperatures near absolute zero, the valence electrons are confined to their respective covalent bonds, refusing to move 1 As design managers often say, “If you do not push the devices and circuits to their limit but your competitor does, then you lose to your competitor.” 2 Silicon is obtained from sand after a great deal of processing.

2.1 Semiconductor Materials and Their Properties III

IV

11

V

Boron (B)

Carbon (C)

Aluminum (Al)

Silicon (Si)

Phosphorus (P)

Galium (Ga)

Germanium (Ge)

Arsenic (As)

Section of the periodic table.

Figure 2.2

freely. In other words, the silicon crystal behaves as an insulator for T → 0K. However, at higher temperatures, electrons gain thermal energy, occasionally breaking away from the bonds and acting as free charge carriers [Fig. 2.3(c)] until they fall into another incomplete bond. We will hereafter use the term “electrons” to refer to free electrons. Covalent Bond Si Si

Si

Si Si

Si (a)

Si Si

Si

Si

Si Si e

Si

(b)

Si

Si

Free Electron

(c)

(a) Silicon atom, (b) covalent bonds between atoms, (c) free electron released by thermal energy.

Figure 2.3

Holes When freed from a covalent bond, an electron leaves a “void” behind because the bond is now incomplete. Called a “hole,” such a void can readily absorb a free electron if one becomes available. Thus, we say an “electron-hole pair” is generated when an electron is freed, and an “electron-hole recombination” occurs when an electron “falls” into a hole. Why do we bother with the concept of the hole? After all, it is the free electron that actually moves in the crystal. To appreciate the usefulness of holes, consider the time evolution illustrated in Fig. 2.4. Suppose covalent bond number 1 contains a hole after losing an electron some time before t = t1 . At t = t2 , an electron breaks away from bond t = t1 1

Si

Si Hole Figure 2.4

t = t2 Si

Si Si

Si Si

Si

Si

t = t3 Si

Si Si

2

Movement of electron through crystal.

Si Si

Si

Si 3 Si

Si Si

Si Si

12

Chapter 2 Basic Physics of Semiconductors number 2 and recombines with the hole in bond number 1. Similarly, at t = t3 , an electron leaves bond number 3 and falls into the hole in bond number 2. Looking at the three “snapshots,” we can say one electron has traveled from right to left, or, alternatively, one hole has moved from left to right. This view of current flow by holes proves extremely useful in the analysis of semiconductor devices. Bandgap Energy We must now answer two important questions. First, does any thermal energy create free electrons (and holes) in silicon? No, in fact, a minimum energy is required to dislodge an electron from a covalent bond. Called the “bandgap energy” and denoted by Eg , this minimum is a fundamental property of the material. For silicon, Eg = 1.12 eV.3 The second question relates to the conductivity of the material and is as follows. How many free electrons are created at a given temperature? From our observations thus far, we postulate that the number of electrons depends on both Eg and T: a greater Eg translates to fewer electrons, but a higher T yields more electrons. To simplify future derivations, we consider the density (or concentration) of electrons, i.e., the number of electrons per unit volume, ni , and write for silicon: −Eg (2.1) electrons/cm3 ni = 5.2 × 1015 T 3/2 exp 2kT where k = 1.38 × 10−23 J/K is called the Boltzmann constant. The derivation can be found in books on semiconductor physics, e.g., [1]. As expected, materials having a larger Eg exhibit a smaller ni . Also, as T → 0, so do T 3/2 and exp[−Eg /(2kT)], thereby bringing ni toward zero. The exponential dependence of ni upon Eg reveals the effect of the bandgap energy on the conductivity of the material. Insulators display a high Eg ; for example, Eg = 2.5 eV for diamond. Conductors, on the other hand, have a small bandgap. Finally, semiconductors exhibit a moderate Eg , typically ranging from 1 eV to 1.5 eV.

Example 2.1

Determine the density of electrons in silicon at T = 300 K (room temperature) and T = 600 K.

Solution

Since Eg = 1.12 eV = 1.792 × 10−19 J, we have ni (T = 300 K) = 1.08 × 1010 electrons/cm3

(2.2)

ni (T = 600 K) = 1.54 × 1015 electrons/cm3 .

(2.3)

Since for each free electron, a hole is left behind, the density of holes is also given by (2.2) and (2.3).

Exercise

Repeat the above exercise for a material having a bandgap of 1.5 eV. The ni values obtained in the above example may appear quite high, but, noting that silicon has 5 × 1022 atoms/cm3 , we recognize that only one in 5 × 1012 atoms benefit from a free electron at room temperature. In other words, silicon still seems a very poor conductor. But, do not despair! We next introduce a means of making silicon more useful. 3 The unit eV (electron volt) represents the energy necessary to move one electron across a potential difference of 1 V. Note that 1 eV = 1.6 × 10−19 J.

2.1 Semiconductor Materials and Their Properties

13

2.1.2 Modification of Carrier Densities Intrinsic and Extrinsic Semiconductors The “pure” type of silicon studied thus far is an example of “intrinsic semiconductors,” suffering from a very high resistance. Fortunately, it is possible to modify the resistivity of silicon by replacing some of the atoms in the crystal with atoms of another material. In an intrinsic semiconductor, the electron density, n( = ni ), is equal to the hole density, p. Thus, np = ni2 .

(2.4)

We return to this equation later. Recall from Fig. 2.2 that phosphorus (P) contains five valence electrons. What happens if some P atoms are introduced in a silicon crystal? As illustrated in Fig. 2.5, each P atom shares four electrons with the neighboring silicon atoms, leaving the fifth electron “unattached.” This electron is free to move, serving as a charge carrier. Thus, if N phosphorus atoms are uniformly introduced in each cubic centimeter of a silicon crystal, then the density of free electrons rises by the same amount.

Si

P e

Si Si Figure 2.5

Si Si

Si

Loosely-attached electon with phosphorus doping.

The controlled addition of an “impurity” such as phosphorus to an intrinsic semiconductor is called “doping,” and phosphorus itself a “dopant.” Providing many more free electrons than in the intrinsic state, the doped silicon crystal is now called “extrinsic,” more specifically, an “n-type” semiconductor to emphasize the abundance of free electrons. As remarked earlier, the electron and hole densities in an intrinsic semiconductor are equal. But, how about these densities in a doped material? It can be proved that even in this case, np = ni2 ,

(2.5)

where n and p respectively denote the electron and hole densities in the extrinsic semiconductor. The quantity ni represents the densities in the intrinsic semiconductor (hence the subscript i) and is therefore independent of the doping level [e.g., Eq. (2.1) for silicon]. Example 2.2

The above result seems quite strange. How can np remain constant while we add more donor atoms and increase n?

Solution

Equation (2.5) reveals that p must fall below its intrinsic level as more n-type dopants are added to the crystal. This occurs because many of the new electrons donated by the dopant “recombine” with the holes that were created in the intrinsic material.

Exercise

Why can we not say that n + p should remain constant?

14

Chapter 2 Basic Physics of Semiconductors

Example 2.3

A piece of crystalline silicon is doped uniformly with phosphorus atoms. The doping density is 1016 atoms/cm3 . Determine the electron and hole densities in this material at the room temperature.

Solution

The addition of 1016 P atoms introduces the same number of free electrons per cubic centimeter. Since this electron density exceeds that calculated in Example 2.1 by six orders of magnitude, we can assume n = 1016 electrons/cm3 .

(2.6)

It follows from (2.2) and (2.5) that p=

ni2 n

(2.7)

= 1.17 × 104 holes/cm3 .

(2.8)

Note that the hole density has dropped below the intrinsic level by six orders of magnitude. Thus, if a voltage is applied across this piece of silicon, the resulting current consists predominantly of electrons.

Exercise

At what doping level does the hole density drop by three orders of magnitude? This example justifies the reason for calling electrons the “majority carriers” and holes the “minority carriers” in an n-type semiconductor. We may naturally wonder if it is possible to construct a “p-type” semiconductor, thereby exchanging the roles of electrons and holes. Indeed, if we can dope silicon with an atom that provides an insufficient number of electrons, then we may obtain many incomplete covalent bonds. For example, the table in Fig. 2.2 suggests that a boron (B) atom—with three valence electrons—can form only three complete covalent bonds in a silicon crystal (Fig. 2.6). As a result, the fourth bond contains a hole, ready to absorb a free electron. In other words, N boron atoms contribute N boron holes to the conduction of current in silicon. The structure in Fig. 2.6 therefore exemplifies a p-type semiconductor, providing holes as majority carriers. The boron atom is called an “acceptor” dopant. Si Si

B Si

Figure 2.6

Si Si Si

Available hole with boron doping.

Let us formulate our results thus far. If an intrinsic semiconductor is doped with a density of ND ( ni ) donor atoms per cubic centimeter, then the mobile charge densities are given by (2.9) Majority Carriers: n ≈ ND Minority Carriers: p ≈

ni2 . ND

(2.10)

2.1 Semiconductor Materials and Their Properties

15

Similarly, for a density of NA ( ni ) acceptor atoms per cubic centimeter: Majority Carriers: p ≈ NA Minority Carriers: n ≈

(2.11)

ni2 . NA

(2.12)

Since typical doping densities fall in the range of 1015 to 1018 atoms/cm3 , the above expressions are quite accurate. Example 2.4

Is it possible to use other elements of Fig. 2.2 as semiconductors and dopants?

Solution

Yes, for example, some early diodes and transistors were based on germanium (Ge) rather than silicon. Also, arsenic (As) is another common dopant.

Exercise

Can carbon be used for this purpose?

Figure 2.7 summarizes the concepts introduced in this section, illustrating the types of charge carriers and their densities in semiconductors. Intrinsic Semiconductor Si Valence Electron

Si Covalent Bond

Si

Extrinsic Semiconductor Silicon Crystal

Silicon Crystal

N D Donors/cm3

N A Acceptors/cm

Si Si Si n–Type Dopant (Donor) Figure 2.7

Si P e

Si Si

Si

Free Majority Carrier

Si Si

B

Si

3

Si Free Majority Carrier

Si p–Type Dopant (Acceptor)

Summary of charge carriers in silicon.

2.1.3 Transport of Carriers Having studied charge carriers and the concept of doping, we are ready to examine the movement of charge in semiconductors, i.e., the mechanisms leading to the flow of current.

16

Chapter 2 Basic Physics of Semiconductors Drift We know from basic physics and Ohm’s law that a material can conduct current in response to a potential difference and hence an electric field.4 The field accelerates the charge carriers in the material, forcing some to flow from one end to the other. Movement of charge carriers due to an electric field is called “drift.”5

E

Figure 2.8

Drift in a semiconductor.

Semiconductors behave in a similar manner. As shown in Fig. 2.8, the charge carriers are accelerated by the field and accidentally collide with the atoms in the crystal, eventually reaching the other end and flowing into the battery. The acceleration due to the field and the collision with the crystal counteract, leading to a constant velocity for the carriers.6 We expect the velocity, v, to be proportional to the electric field strength, E: v ∝ E,

(2.13)

v = μE,

(2.14)

and hence

where μ is called the “mobility” and usually expressed in cm2 /(V · s). For example in silicon, the mobility of electrons, μn = 1350 cm2 /(V · s), and that of holes, μ p = 480 cm2 /(V · s). Of course, since electrons move in a direction opposite to the electric field, we must express the velocity vector as →

→

ve = −μn E.

(2.15)

For holes, on the other hand, →

→

vh = μp E.

(2.16)

4 Recall that the potential (voltage) adifference, V, is equal to the negative integral of the electric field, E, with respect to distance: Vab = − b Edx. 5 The convention for direction of current assumes flow of positive charge from a positive voltage to a negative voltage. Thus, if electrons flow from point A to point B, the current is considered to have a direction from B to A. 6 This phenomenon is analogous to the “terminal velocity” that a sky diver with a parachute (hopefully, open) experiences.

2.1 Semiconductor Materials and Their Properties

17

Example 2.5

A uniform piece of n-type of silicon that is 1 μm long senses a voltage of 1 V. Determine the velocity of the electrons.

Solution

Since the material is uniform, we have E = V/L, where L is the length. Thus, E = 10,000 V/cm and hence v = μn E = 1.35 × 107 cm/s. In other words, electrons take (1 μm)/(1.35 × 107 cm/s) = 7.4 ps to cross the 1-μm length.

Exercise

What happens if the mobility is halved?

v meters

t = t1 + 1 s

t = t1 L

W

h

x

x1 V1

Figure 2.9

x

x1 V1

Current flow in terms of charge density.

With the velocity of carriers known, how is the current calculated? We first note that an electron carries a negative charge equal to q = 1.6 × 10−19 C. Equivalently, a hole carries a positive charge of the same value. Now suppose a voltage V1 is applied across a uniform semiconductor bar having a free electron density of n (Fig. 2.9). Assuming the electrons move with a velocity of v m/s, considering a cross section of the bar at x = x1 and taking two “snapshots” at t = t1 and t = t1 + 1 second, we note that the total charge in v meters passes the cross section in 1 second. In other words, the current is equal to the total charge enclosed in v meters of the bar’s length. Since the bar has a width of W, we have: I = −v · W · h · n · q,

(2.17)

where v · W · h represents the volume, n · q denotes the charge density in coulombs, and the negative sign accounts for the fact that electrons carry negative charge. Let us now reduce Eq. (2.13) to a more convenient form. Since for electrons, v = −μn E, and since W · h is the cross section area of the bar, we write Jn = μn E · n · q,

(2.18)

where Jn denotes the “current density,” i.e., the current passing through a unit cross section area, and is expressed in A/cm2 . We may loosely say, “the current is equal to the charge velocity times the charge density,” with the understanding that “current” in fact refers to current density, and negative or positive signs are taken into account properly. In the presence of both electrons and holes, Eq. (2.18) is modified to Jtot = μn E · n · q + μ p E · p · q = q(μn n + μ p p)E.

(2.19) (2.20)

18

Chapter 2 Basic Physics of Semiconductors This equation gives the drift current density in response to an electric field E in a semiconductor having uniform electron and hole densities.

Example 2.6

In an experiment, it is desired to obtain equal electron and hole drift currents. How should the carrier densities be chosen?

Solution

We must impose μn n = μ p p,

(2.21)

n μp . = p μn

(2.22)

and hence

We also recall that np = ni2 . Thus, p= n=

μn ni μp

(2.23)

μp ni . μn

(2.24)

For example, in silicon, μn /μ p = 1350/480 = 2.81, yielding p = 1.68ni

(2.25)

n = 0.596ni .

(2.26)

Since p and n are of the same order as ni , equal electron and hole drift currents can occur for only a very lightly doped material. This confirms our earlier notion of majority carriers in semiconductors having typical doping levels of 1015 –1018 atoms/cm3 . Exercise

How should the carrier densities be chosen so that the electron drift current is twice the hole drift current?

Velocity Saturation* We have thus far assumed that the mobility of carriers in semiconductors is independent of the electric field and the velocity rises linearly with E according to v = μE. In reality, if the electric field approaches sufficiently high levels, v no longer follows E linearly. This is because the carriers collide with the lattice so frequently and the time between the collisions is so short that they cannot accelerate much. As a result, v varies “sublinearly” at high electric fields, eventually reaching a saturated level, vsat (Fig. 2.10). Called “velocity saturation,” this effect manifests itself in some modern transistors, limiting the performance of circuits. In order to represent velocity saturation, we must modify v = μE accordingly. A simple approach is to view the slope, μ, as a field-dependent parameter. The expression ∗

This section can be skipped in a first reading.

2.1 Semiconductor Materials and Their Properties

19

Velocity vsat

µ2 µ1 E

Figure 2.10

Velocity saturation.

for μ must therefore gradually fall toward zero as E rises, but approach a constant value for small E; i.e., μ0 μ= , (2.27) 1 + bE where μ0 is the “low-field” mobility and b a proportionality factor. We may consider μ as the “effective” mobility at an electric field E. Thus, v=

μ0 E. 1 + bE

(2.28)

Since for E → ∞, v → vsat , we have vsat =

μ0 , b

(2.29)

and hence b = μ0 /vsat . In other words, v=

μ0 E. μ0 E 1+ vsat

(2.30)

Example 2.7

A uniform piece of semiconductor 0.2 μm long sustains a voltage of 1 V. If the low-field mobility is equal to 1350 cm2 /(V · s) and the saturation velocity of the carriers 107 cm/s, determine the effective mobility. Also, calculate the maximum allowable voltage such that the effective mobility is only 10% lower than μ0 .

Solution

We have E=

V L

= 50 kV/cm.

(2.31) (2.32)

It follows that μ0 μ0 E 1+ vsat μ0 = 7.75

μ=

= 174 cm2 /(V · s).

(2.33)

(2.34) (2.35)

20

Chapter 2 Basic Physics of Semiconductors If the mobility must remain within 10% of its low-field value, then 0.9μ0 =

μ0 , μ0 E 1+ vsat

(2.36)

and hence E=

1 vsat 9 μ0

= 823 V/cm.

(2.37) (2.38)

A device of length 0.2 μm experiences such a field if it sustains a voltage of (823 V/cm) × (0.2 × 10−4 cm) = 16.5 mV. This example suggests that modern (submicron) devices incur substantial velocity saturation because they operate with voltages much greater than 16.5 mV. Exercise

At what voltage does the mobility fall by 20%?

Diffusion In addition to drift, another mechanism can lead to current flow. Suppose a drop of ink falls into a glass of water. Introducing a high local concentration of ink molecules, the drop begins to “diffuse,” that is, the ink molecules tend to flow from a region of high concentration to regions of low concentration. This mechanism is called “diffusion.” A similar phenomenon occurs if charge carriers are “dropped” (injected) into a semiconductor so as to create a nonuniform density. Even in the absence of an electric field, the carriers move toward regions of low concentration, thereby carrying an electric current so long as the nonuniformity is sustained. Diffusion is therefore distinctly different from drift. Semiconductor Material Injection of Carriers

Nonuniform Concentration Figure 2.11

Diffusion in a semiconductor.

Figure 2.11 conceptually illustrates the process of diffusion. A source on the left continues to inject charge carriers into the semiconductor, a nonuniform charge profile is created along the x-axis, and the carriers continue to “roll down” the profile. The reader may raise several questions at this point. What serves as the source of carriers in Fig. 2.11? Where do the charge carriers go after they roll down to the end of the profile at the far right? And, most importantly, why should we care?! Well, patience is a virtue and we will answer these questions in the next section.

2.1 Semiconductor Materials and Their Properties Example 2.8

21

A source injects charge carriers into a semiconductor bar as shown in Fig. 2.12. Explain how the current flows. Injection of Carriers

x

0 Figure 2.12

Injection of carriers into a semiconductor.

Solution

In this case, two symmetric profiles may develop in both positive and negative directions along the x-axis, leading to current flow from the source toward the two ends of the bar.

Exercise

Is KCL still satisfied at the point of injection?

Our qualitative study of diffusion suggests that the more nonuniform the concentration, the larger the current. More specifically, we can write: I∝

dn , dx

(2.39)

where n denotes the carrier concentration at a given point along the x-axis. We call dn/dx the concentration “gradient” with respect to x, assuming current flow only in the x direction. If each carrier has a charge equal to q, and the semiconductor has a cross section area of A, Eq. (2.39) can be written as I ∝ Aq

dn . dx

(2.40)

Thus, I = AqDn

dn , dx

(2.41)

where Dn is a proportionality factor called the “diffusion constant” and expressed in cm2 /s. For example, in intrinsic silicon, Dn = 34 cm2 /s (for electrons), and D p = 12 cm2 /s (for holes). As with the convention used for the drift current, we normalize the diffusion current to the cross section area, obtaining the current density as Jn = qDn

dn . dx

(2.42)

Similarly, a gradient in hole concentration yields: Jp = −qDp

dp . dx

(2.43)

22

Chapter 2 Basic Physics of Semiconductors With both electron and hole concentration gradients present, the total current density is given by dn dp − Dp . (2.44) Jtot = q Dn dx dx

Example 2.9

Consider the scenario depicted in Fig. 2.11 again. Suppose the electron concentration is equal to N at x = 0 and falls linearly to zero at x = L (Fig. 2.13). Determine the diffusion current. N Injection L

0 Figure 2.13

Solution

x

Current resulting from a linear diffusion profile.

We have Jn = qDn

dn dx

(2.45)

N . (2.46) L The current is constant along the x-axis; i.e., all of the electrons entering the material at x = 0 successfully reach the point at x = L. While obvious, this observation prepares us for the next example. = −qDn ·

Exercise

Repeat the above example for holes.

Example 2.10

Repeat the above example but assume an exponential gradient (Fig. 2.14): N Injection L

0 Figure 2.14

x

Current resulting from an exponential diffusion profile.

n(x) = N exp

−x , Ld

where Ld is a constant.7

7

The factor Ld is necessary to convert the exponent to a dimensionless quantity.

(2.47)

2.2 pn Junction

Solution

23

We have Jn = qDn =

dn dx

(2.48)

−qDn N −x exp . Ld Ld

(2.49)

Interestingly, the current is not constant along the x-axis. That is, some electrons vanish while traveling from x = 0 to the right. What happens to these electrons? Does this example violate the law of conservation of charge? These are important questions and will be answered in the next section. Exercise

At what value of x does the current density drop to 1% of its maximum value?

Einstein Relation Our study of drift and diffusion has introduced a factor for each: μn (or μp ) and Dn (or Dp ), respectively. It can be proved that μ and D are related as: kT D = . μ q

(2.50)

Called the “Einstein Relation,” this result is proved in semiconductor physics texts, e.g., [1]. Note that kT/q ≈ 26 mV at T = 300 K. Figure 2.15 summarizes the charge transport mechanisms studied in this section.

Drift Current

Diffusion Current

E

Figure 2.15

2.2

Jn = q n

μn E

Jp = q p

μp E

dn dx dp J p = –q D p dx Jn = q Dn

Summary of drift and diffusion mechanisms.

pn JUNCTION We begin our study of semiconductor devices with the pn junction for three reasons. (1) The device finds application in many electronic systems, e.g., in adaptors that charge the batteries of cellphones. (2) The pn junction is among the simplest semiconductor devices, thus providing a good entry point into the study of the operation of such complex structures as transistors. (3) The pn junction also serves as part of transistors. We also use the term “diode” to refer to pn junctions.

24

Chapter 2 Basic Physics of Semiconductors We have thus far seen that doping produces free electrons or holes in a semiconductor, and an electric field or a concentration gradient leads to the movement of these charge carriers. An interesting situation arises if we introduce n-type and p-type dopants into two adjacent sections of a piece of semiconductor. Depicted in Fig. 2.16 and called a “pn junction,” this structure plays a fundamental role in many semiconductor devices. The p and n sides are called the “anode” and the “cathode,” respectively.

n

p

Si

Si

Anode

Cathode Si

P e Si

Si B

Si

Si

Si

(a) Figure 2.16

(b)

pn junction.

In this section, we study the properties and I/V characteristics of pn junctions. The following outline shows our thought process, indicating that our objective is to develop circuit models that can be used in analysis and design.

pn Junction in Equilibrium

pn Junction Under Reverse Bias

pn Junction Under Forward Bias

Depletion Region Built-in Potential

Junction Capacitance

I/V Characteristics

Figure 2.17

Outline of concepts to be studied.

2.2.1 pn Junction in Equilibrium Let us first study the pn junction with no external connections, i.e., the terminals are open and no voltage is applied across the device. We say the junction is in “equilibrium.” While seemingly of no practical value, this condition provides insights that prove useful in understanding the operation under nonequilibrium as well. We begin by examining the interface between the n and p sections, recognizing that one side contains a large excess of holes and the other, a large excess of electrons. The sharp concentration gradient for both electrons and holes across the junction leads to two large diffusion currents: electrons flow from the n side to the p side, and holes flow in the opposite direction. Since we must deal with both electron and hole concentrations on each side of the junction, we introduce the notations shown in Fig. 2.18.

2.2 pn Junction Majority Carriers Minority Carriers

n

p

nn

pp

pn

np

25

Majority Carriers Minority Carriers

nn : Concentration of electrons on n side pn : Concentration of holes on n side pp : Concentration of holes on p side np : Concentration of electrons on p side Figure 2.18

Example 2.11

A pn junction employs the following doping levels: NA = 1016 cm−3 and ND = 5 × 1015 cm−3 . Determine the hole and electron concentrations on the two sides.

Solution

From Eqs. (2.11) and (2.12), we express the concentrations of holes and electrons on the p side respectively as: pp ≈ NA = 1016 cm−3 np ≈ =

(2.51) (2.52)

ni2 NA

(2.53)

(1.08 × 1010 cm−3 )2 1016 cm−3

(2.54)

≈ 1.1 × 104 cm−3 .

(2.55)

Similarly, the concentrations on the n side are given by nn ≈ ND = 5 × 1015 cm−3 pn ≈ =

(2.56) (2.57)

ni2 ND

(2.58)

(1.08 × 1010 cm−3 )2 5 × 1015 cm−3

(2.59)

= 2.3 × 104 cm−3 .

(2.60)

Note that the majority carrier concentration on each side is many orders of magnitude higher than the minority carrier concentration on either side. Exercise

Repeat the above example if ND drops by a factor of four.

26

Chapter 2 Basic Physics of Semiconductors The diffusion currents transport a great deal of charge from each side to the other, but they must eventually decay to zero. This is because if the terminals are left open (equilibrium condition), the device cannot carry a net current indefinitely. We must now answer an important question: what stops the diffusion currents? We may postulate that the currents stop after enough free carriers have moved across the junction so as to equalize the concentrations on the two sides. However, another effect dominates the situation and stops the diffusion currents well before this point is reached. To understand this effect, we recognize that for every electron that departs from the n side, a positive ion is left behind, i.e., the junction evolves with time as conceptually shown in Fig. 2.19. In this illustration, the junction is suddenly formed at t = 0, and the diffusion currents continue to expose more ions as time progresses. Consequently, the immediate vicinity of the junction is depleted of free carriers and hence called the “depletion region.” t=0

t = t1

n

p

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Free Free Electrons Holes

Figure 2.19

t=

n

p

– – – – – – – – – – – – – – – – – – – – – – – – – – – –

+ + + + +

– – – – –

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

Positive Negative Donor Acceptor Ions Ions

n – – – – – – – – – – – – – – – – – – – – – – – –

+ + + + +

+ + + + +

– – – – –

– – – – –

p + + + + + + + + + + + + + + + + + + + + + + + +

Depletion Region

Evolution of charge concentrations in a pn junction.

Now recall from basic physics that a particle or object carrying a net (nonzero) charge creates an electric field around it. Thus, with the formation of the depletion region, an electric field emerges as shown in Fig. 2.20.8 Interestingly, the field tends to force positive charge flow from left to right whereas the concentration gradients necessitate the flow of holes from right to left (and electrons from left to right). We therefore surmise that the junction reaches equilibrium once the electric field is strong enough to completely stop the diffusion currents. Alternatively, we can say, in equilibrium, the drift currents resulting from the electric field exactly cancel the diffusion currents due to the gradients. n – – – – – – – – – – – – – – – – – – – – – – – – Figure 2.20

E + + + + +

+ + + + +

– – – – –

– – – – –

p + + + + + + + + + + + + + + + + + + + + + + + +

Electric field in a pn junction.

8 The direction of the electric field is determined by placing a small positive test charge in the region and watching how it moves: away from positive charge and toward negative charge.

2.2 pn Junction Example 2.12

27

In the junction shown in Fig. 2.21, the depletion region has a width of b on the n side and a on the p side. Sketch the electric field as a function of x. n – – – – – – – – – – N – D – – – – – – – – – –

E + + + + +

–b

+ + + + +

– – – – –

– – – – –

p + + + + + + + + + + + NA + + + + + + + + + +

a

x

a

x

E –b Figure 2.21

Electric field profile in a pn junction.

Solution

Beginning at x < −b, we note that the absence of net charge yields E = 0. At x > −b, each positive donor ion contributes to the electric field, i.e., the magnitude of E rises as x approaches zero. As we pass x = 0, the negative acceptor atoms begin to contribute negatively to the field, i.e., E falls. At x = a, the negative and positive charge exactly cancel each other and E = 0.

Exercise

Noting that potential voltage is negative integral of electric field with respect to distance, plot the potential as a function of x.

From our observation regarding the drift and diffusion currents under equilibrium, we may be tempted to write: |Idrift, p + Idrift,n | = |Idiff, p + Idiff,n |,

(2.61)

where the subscripts p and n refer to holes and electrons, respectively, and each current term contains the proper polarity. This condition, however, allows an unrealistic phenomenon: if the number of the electrons flowing from the n side to the p side is equal to that of the holes going from the p side to the n side, then each side of this equation is zero while electrons continue to accumulate on the p side and holes on the n side. We must therefore impose the equilibrium condition on each carrier: |Idrift, p | = |Idiff, p |

(2.62)

|Idrift,n | = |Idiff,n |.

(2.63)

Built-in Potential The existence of an electric field within the depletion region suggests that the junction may exhibit a “built-in potential.” In fact, using (2.62) or (2.63), we can compute this potential. Since the electric field E = −dV/dx, and since (2.62) can be written as dp (2.64) qμp pE = qDp , dx

28

Chapter 2 Basic Physics of Semiconductors we have dp dV = Dp . dx dx Dividing both sides by p and taking the integral, we obtain x2 pp dp −μp dV = Dp , p x1 pn −μp p

(2.65)

(2.66)

where pn and pp are the hole concentrations at x1 and x2 , respectively (Fig. 2.22). Thus, V(x2 ) − V(x1 ) = − n

(2.67)

p

nn

pp

pn

np x1

Figure 2.22

Dp pp ln . μp pn

x2

x

Carrier profiles in a pn junction.

The right side represents the voltage difference developed across the depletion region and will be denoted by V0 . Also, from Einstein’s relation, Eq. (2.50), we can replace Dp /μp with kT/q: kT pp |V0 | = . (2.68) ln q pn Exercise

Writing Eq. (2.64) for electron drift and diffusion currents, and carrying out the integration, derive an equation for V0 in terms of nn and n p . Finally, using (2.11) and (2.10) for pp and pn yields V0 =

kT NA ND . ln q ni2

(2.69)

Expressing the built-in potential in terms of junction parameters, this equation plays a central role in many semiconductor devices. Example 2.13

A silicon pn junction employs NA = 2 × 1016 cm−3 and ND = 4 × 1016 cm−3 . Determine the built-in potential at room temperature (T = 300 K).

Solution

Recall from Example 2.1 that ni (T = 300 K) = 1.08 × 1010 cm−3 . Thus, V0 ≈ (26 mV) ln

(2 × 1016 ) × (4 × 1016 ) (1.08 × 1010 )2

≈ 768 mV.

Exercise

By what factor should ND be changed to lower V0 by 20 mV?

(2.70) (2.71)

2.2 pn Junction

29

Example 2.14

Equation (2.69) reveals that V0 is a weak function of the doping levels. How much does V0 change if NA or ND is increased by one order of magnitude?

Solution

We can write V0 = VT ln

Exercise

10NA · ND NA · ND − VT ln ni2 ni2

(2.72)

= VT ln 10

(2.73)

≈ 60 mV (at T = 300 K).

(2.74)

How much does V0 change if NA or ND is increased by a factor of three?

An interesting question may arise at this point. The junction carries no net current (because its terminals remain open), but it sustains a voltage. How is that possible? We observe that the built-in potential is developed to oppose the flow of diffusion currents (and is, in fact, sometimes called the “potential barrier”). This phenomenon is in contrast to the behavior of a uniform conducting material, which exhibits no tendency for diffusion and hence no need to create a built-in voltage. 2.2.2 pn Junction Under Reverse Bias Having analyzed the pn junction in equilibrium, we can now study its behavior under more interesting and useful conditions. Let us begin by applying an external voltage across the device as shown in Fig. 2.23, where the voltage source makes the n side more positive than the p side. We say the junction is under “reverse bias” to emphasize the connection of the positive voltage to the n terminal. Used as a noun or a verb, the term “bias” indicates operation under some “desirable” conditions. We will study the concept of biasing extensively in this and following chapters. n – – – – – – – – – – – – – – – – – – – – – – – – n – – – – – – – – – – – – – – – –

+ + + + +

+ + + + +

+ + + + +

+ + + + +

+ + + + +

– – – – –

– – – – –

VR Figure 2.23

pn junction under reverse bias.

– – – – –

p + + + + + + + + + + + + + + + + + + + + + + + +

– – – – –

p + + + + + + + + + + + + + + + +

– – – – –

30

Chapter 2 Basic Physics of Semiconductors

n – – – – – – – – – – – – – – – – – – – – – – – –

V R1 + + + + +

+ + + + +

– – – – –

– – – – –

n – – – – – – – – – – – – – – – –

p + + + + + + + + + + + + + + + + + + + + + + + +

+ + + + +

+ + + + +

– – – – –

– – – – –

– – – – –

p + + + + + + + + + + + + + + + + + + + +

V R2 (more negative than VR1)

V R1 (a) Figure 2.24

+ + + + +

– – – –

+ + + +

– – – –

V R2

(b)

Reduction of junction capacitance with reverse bias.

We wish to reexamine the results obtained in equilibrium for the case of reverse bias. Let us first determine whether the external voltage enhances the built-in electric field or → opposes it. Since under equilibrium, E is directed from the n side to the p side, VR enhances the field. But, a higher electric field can be sustained only if a larger amount of fixed charge is provided, requiring that more acceptor and donor ions be exposed and, therefore, the depletion region be widened. What happens to the diffusion and drift currents? Since the external voltage has strengthened the field, the barrier rises even higher than that in equilibrium, thus prohibiting the flow of current. In other words, the junction carries a negligible current under reverse bias.9 With no current conduction, a reverse-biased pn junction does not seem particularly useful. However, an important observation will prove otherwise. We note that in Fig. 2.23, as VB increases, more positive charge appears on the n side and more negative charge on the p side. Thus, the device operates as a capacitor [Fig. 2.24(a)]. In essence, we can view the conductive n and p sections as the two plates of the capacitor. We also assume the charge in the depletion region equivalently resides on each plate. The reader may still not find the device interesting. After all, since any two parallel plates can form a capacitor, the use of a pn junction for this purpose is not justified. But, reverse-biased pn junctions exhibit a unique property that becomes useful in circuit design. Returning to Fig. 2.23, we recognize that, as VR increases, so does the width of the depletion region. That is, the conceptual diagram of Fig. 2.24(a) can be drawn as in Fig. 2.24(b) for increasing values of VR , revealing that the capacitance of the structure decreases as the two plates move away from each other. The junction therefore displays a voltage-dependent capacitance. It can be proved that the capacitance of the junction per unit area is equal to Cj =

9

Cj0 VR 1− V0

,

As explained in Section 2.2.3, the current is not exactly zero.

(2.75)

2.2 pn Junction

31

where Cj0 denotes the capacitance corresponding to zero bias (VR = 0) and V0 is the builtin potential [Eq. (2.69)]. (This equation assumes VR is negative for reverse bias.) The value of Cj0 is in turn given by Cj0 =

si q NA ND 1 , 2 NA + ND V0

(2.76)

where si represents the dielectric constant of silicon and is equal to 11.7 × 8.85 × 10−14 F/cm.10 Plotted in Fig. 2.25, Cj indeed decreases as VR increases.

Cj

0 Figure 2.25

VR

Junction capacitance under reverse bias.

Example 2.15

A pn junction is doped with NA = 2 × 1016 cm−3 and ND = 9 × 1015 cm−3 . Determine the capacitance of the device with (a) VR = 0 and VR = 1 V.

Solution

We first obtain the built-in potential: V0 = VT ln

NA ND ni2

= 0.73 V.

(2.77) (2.78)

Thus, for VR = 0 and q = 1.6 × 10−19 C, we have Cj0 =

si q NA ND 1 · 2 NA + ND V0

= 2.65 × 10−8 F/cm2 .

(2.79) (2.80)

In microelectronics, we deal with very small devices and may rewrite this result as Cj0 = 0.265 fF/μm2 ,

(2.81)

10 The dielectric constant of materials is usually written in the form r 0 , where r is the “relative” dielectric constant and a dimensionless factor (e.g., 11.7), and 0 the dielectric constant of vacuum (8.85 × 10−14 F/cm).

32

Chapter 2 Basic Physics of Semiconductors where 1 fF (femtofarad) = 10−15 F. For VR = 1 V, Cj0

Cj =

1+

VR V0

= 0.172 fF/μm2 . Exercise

(2.82)

(2.83)

Repeat the above example if the donor concentration on the N side is doubled. Compare the results in the two cases.

The variation of the capacitance with the applied voltage makes the device a “nonlinear” capacitor because it does not satisfy Q = CV. Nonetheless, as demonstrated by the following example, a voltage-dependent capacitor leads to interesting circuit topologies.

Example 2.16

A cellphone incorporates a 2-GHz oscillator whose frequency is defined by the resonance frequency of an LC tank (Fig. 2.26). If the tank capacitance is realized as the pn junction of Example 2.15, calculate the change in the oscillation frequency while the reverse voltage goes from 0 to 2 V. Assume the circuit operates at 2 GHz at a reverse voltage of 0 V, and the junction area is 2000 μm2 . Oscillator

VR

Figure 2.26

Solution

L

C

Variable capacitor used to tune an oscillator.

Recall from basic circuit theory that the tank “resonates” if the impedances of the inductor and the capacitor are equal and opposite: jLωres = −( jCωres )−1 . Thus, the resonance frequency is equal to fres =

1 1 . √ 2π LC

(2.84)

At VR = 0, Cj = 0.265 fF/μm2 , yielding a total device capacitance of C j,tot (VR = 0) = (0.265 fF/μm2 ) × (2000 μm2 ) = 530 fF.

(2.85) (2.86)

Setting fres to 2 GHz, we obtain L = 11.9 nH.

(2.87)

2.2 pn Junction

33

If VR goes to 2 V, C j,tot (VR = 2 V) =

Cj0 2 1+ 0.73

× 2000 μm2

= 274 fF.

(2.88)

(2.89)

Using this value along with L = 11.9 nH in Eq. (2.84), we have fres (VR = 2 V) = 2.79 GHz.

(2.90)

An oscillator whose frequency can be varied by an external voltage (VR in this case) is called a “voltage-controlled oscillator” and used extensively in cellphones, microprocessors, personal computers, etc. Exercise

Some wireless systems operate at 5.2 GHz. Repeat the above example for this frequency, assuming the junction area is still 2000 μm2 but the inductor value is scaled to reach 5.2 GHz.

In summary, a reverse-biased pn junction carries a negligible current but exhibits a voltage-dependent capacitance. Note that we have tacitly developed a circuit model for the device under this condition: a simple capacitance whose value is given by Eq. (2.75). Another interesting application of reverse-biased diodes is in digital cameras (Chapter 1). If light of sufficient energy is applied to a pn junction, electrons are dislodged from their covalent bonds and hence electron-hole pairs are created. With a reverse bias, the electrons are attracted to the positive battery terminal and the holes to the negative battery terminal. As a result, a current flows through the diode that is proportional to the light intensity. We say the pn junction operates as a “photodiode.” 2.2.3 pn Junction Under Forward Bias Our objective in this section is to show that the pn junction carries a current if the p side is raised to a more positive voltage than the n side (Fig. 2.27). This condition is called “forward bias.” We also wish to compute the resulting current in terms of the applied voltage and the junction parameters, ultimately arriving at a circuit model.

n – – – – – – – – – – – – – – – – – – – – – – – – – – – –

+ + + + +

– – – – –

VF Figure 2.27

pn junction under forward bias.

p + + + + + + + + + + + + + + + + + + + + + + + + + + + +

34

Chapter 2 Basic Physics of Semiconductors From our study of the device in equilibrium and reverse bias, we note that the potential barrier developed in the depletion region determines the device’s desire to conduct. In forward bias, the external voltage, VF , tends to create a field directed from the p side toward the n side—opposite to the built-in field that was developed to stop the diffusion currents. We therefore surmise that VF in fact lowers the potential barrier by weakening the field, thus allowing greater diffusion currents. To derive the I/V characteristic in forward bias, we begin with Eq. (2.68) for the built-in voltage and rewrite it as pp,e , (2.91) pn,e = V0 exp VT where the subscript e emphasizes equilibrium conditions [Fig. 2.28(a)] and VT = kT/q is called the “thermal voltage” (≈26 mV at T = 300 K). In forward bias, the potential barrier is lowered by an amount equal to the applied voltage: pp, f . (2.92) pn, f = V0 − VF exp VT where the subscript f denotes forward bias. Since the exponential denominator drops considerably, we expect pn, f to be much higher than pn,e (it can be proved that pp, f ≈ pp,e ≈ NA ). In other words, the minority carrier concentration on the p side rises rapidly with the forward bias voltage while the majority carrier concentration remains relatively constant. This statement applies to the n side as well. n

p

n pp,e

nn,e

nn,f

pp,f

pn,f

np,f

np,e

pn,e

p

np,f

pn,e

VF (a) Figure 2.28

(b)

Carrier profiles (a) in equilibrium and (b) under forward bias.

Figure 2.28(b) illustrates the results of our analysis thus far. As the junction goes from equilibrium to forward bias, n p and pn increase dramatically, leading to a proportional change in the diffusion currents.11 We can express the change in the hole concentration on the n side as: (2.93) pn = pn, f − pn,e pp, f pp,e − V0 − VF V0 exp exp VT VT VF NA exp −1 . ≈ V0 VT exp VT

=

11

(2.94)

(2.95)

The width of the depletion region actually decreases in forward bias, but we neglect this effect here.

2.2 pn Junction Similarly, for the electron concentration on the p side: VF ND n p ≈ exp −1 . V0 VT exp VT

35

(2.96)

Note that Eq. (2.69) indicates that exp(V0 /VT ) = NA ND /ni2 . The increase in the minority carrier concentration suggests that the diffusion currents must rise by a proportional amount above their equilibrium value, i.e., VF VF NA ND Itot ∝ exp exp −1 + −1 . (2.97) V0 V0 VT VT exp exp VT VT Indeed, it can be proved that [1]

Itot = IS

VF exp −1 , VT

where IS is called the “reverse saturation current” and given by Dn Dp 2 IS = Aqni . + NA Ln ND L p

(2.98)

(2.99)

In this equation, A is the cross section area of the device, and Ln and Lp are electron and hole “diffusion lengths,” respectively. Diffusion lengths are typically in the range of tens of micrometers. Note that the first and second terms in the parentheses correspond to the flow of electrons and holes, respectively. Example 2.17

Solution

Determine IS for the junction of Example 2.13 at T = 300K if A = 100 μm2 , Ln = 20 μm, and Lp = 30 μm. Using q = 1.6 × 10−19 C, ni = 1.08 × 1010 electrons/cm3 [Eq. (2.2)], Dn = 34 cm2 /s, and Dp = 12 cm2 /s, we have IS = 1.77 × 10−17 A.

(2.100)

Since IS is extremely small, the exponential term in Eq. (2.98) must assume very large values so as to yield a useful amount (e.g., 1 mA) for Itot . Exercise

What junction area is necessary to raise IS to 10−15 A?

An interesting question that arises here is: are the minority carrier concentrations constant along the x-axis? Depicted in Fig. 2.29(a), such a scenario would suggest that electrons continue to flow from the n side to the p side, but exhibit no tendency to go beyond x = x2 because of the lack of a gradient. A similar situation exists for holes, implying that the charge carriers do not flow deep into the p and n sides and hence no net current results! Thus, the minority carrier concentrations must vary as shown in Fig. 2.29(b) so that diffusion can occur. This observation reminds us of Example 2.10 and the question raised in conjunction with it: if the minority carrier concentration falls with x, what happens to the carriers and how can the current remain constant along the x-axis? Interestingly, as the electrons enter

Chapter 2 Basic Physics of Semiconductors

n

Hole Flow

Electron Flow

nn,f pn,f

– ++ – + –– + x1

x2

p

n

pp,f

nn,f

np,f

pn,f

+ +

+

+

– ++ – + –

x1

x

VF

p

pp,f –

x2

– – np,f – x

VF

(a) Figure 2.29

Hole Flow

Electron Flow

(b)

(a) Constant and (b) variable majority carrier profiles outside the depletion region.

the p side and roll down the gradient, they gradually recombine with the holes, which are abundant in this region. Similarly, the holes entering the n side recombine with the electrons. Thus, in the immediate vicinity of the depletion region, the current consists of mostly minority carriers, but towards the far contacts, it is primarily comprised of majority carriers (Fig. 2.30). At each point along the x-axis, the two components add up to Itot . p

n

++ + + ++ + + ++

–– – – –– – – –– ++ + + + + ++ ++

–– – – – – –– ––

36

x VF Figure 2.30

Minority and majority carrier currents.

2.2.4 I/V Characteristics Let us summarize our thoughts thus far. In forward bias, the external voltage opposes the built-in potential, raising the diffusion currents substantially. In reverse bias, on the other hand, the applied voltage enhances the field, prohibiting current flow. We hereafter write the junction equation as: VD −1 , (2.101) ID = IS exp VT where ID and VD denote the diode current and voltage, respectively. As expected, VD = 0 yields ID = 0. (Why is this expected?) As VD becomes positive and exceeds several VT , the exponential term grows rapidly and ID ≈ IS exp(VD /VT ). We hereafter assume exp(VD /VT ) 1 in the forward bias region.

2.2 pn Junction Reverse Bias

37

Forward Bias ID I S exp

–IS Figure 2.31

VD VT VD

I/V characteristic of a pn junction.

It can be proved that Eq. (2.101) also holds in reverse bias, i.e., for negative VD . If VD < 0 and |VD | reaches several VT , then exp(VD /VT ) 1 and ID ≈ −IS .

(2.102)

Figure 2.31 plots the overall I/V characteristic of the junction, revealing why IS is called the “reverse saturation current.” Example 2.17 indicates that IS is typically very small. We therefore view the current under reverse bias as “leakage.” Note that IS and hence the junction current are proportional to the device cross section area [Eq. (2.99)]. For example, two identical devices placed in parallel (Fig. 2.32) behave as a single junction with twice the IS . A n

p

n

p

2A n

p

A VF Figure 2.32

Example 2.18

Solution

VF

Equivalence of parallel devices to a larger device.

Each junction in Fig. 2.32 employs the doping levels described in Example 2.13. Determine the forward bias current of the composite device for VD = 300 mV and 800 mV at T = 300 K. From Example 2.17, IS = 1.77 × 10−17 A for each junction. Thus, the total current is equal to VD ID,tot (VD = 300 mV) = 2IS exp −1 (2.103) VT = 3.63 pA.

(2.104)

38

Chapter 2 Basic Physics of Semiconductors Similarly, for VD = 800 mV: ID,tot (VD = 800 mV) = 82 μA.

(2.105)

Exercise

How many of these diodes must be placed in parallel to obtain a current of 100 μA with a voltage of 750 mV?

Example 2.19

A diode operates in the forward bias region with a typical current level [i.e., ID ≈ IS exp(VD /VT )]. Suppose we wish to increase the current by a factor of 10. How much change in VD is required?

Solution

Let us first express the diode voltage as a function of its current: VD = VT ln

ID . IS

(2.106)

We define I1 = 10ID and seek the corresponding voltage, VD1 : VD1 = VT ln = VT ln

10ID IS

(2.107)

ID + VT ln 10 IS

(2.108)

= VD + VT ln 10.

(2.109)

Thus, the diode voltage must rise by VT ln 10 ≈ 60 mV (at T = 300 K) to accommodate a tenfold increase in the current. We say the device exhibits a 60-mV/decade characteristic, meaning VD changes by 60 mV for a decade (tenfold) change in ID . More generally, an n-fold change in ID translates to a change of VT ln n in VD . Exercise

By what factor does the current change if the voltages changes by 120 mV?

Example 2.20

The cross section area of a diode operating in the forward bias region is increased by a factor of 10. (a) Determine the change in ID if VD is maintained constant. (b) Determine the change in VD if ID is maintained constant. Assume ID ≈ IS exp(VD /VT ).

Solution

(a) Since IS ∝ A, the new current is given by ID1 = 10IS exp = 10ID .

VD VT

(2.110) (2.111)

2.2 pn Junction

39

(b) From the above example, VD1 = VT ln = VT ln

ID 10IS

(2.112)

ID − VT ln 10. IS

(2.113)

Thus, a tenfold increase in the device area lowers the voltage by 60 mV if ID remains constant. Exercise

A diode in forward bias with ID ≈ IS exp(VD /VT ) undergoes two simultaneous changes: the current is raised by a factor of m and the area is increased by a factor of n. Determine the change in the device voltage.

Constant-Voltage Model The exponential I/V characteristic of the diode results in nonlinear equations, making the analysis of circuits quite difficult. Fortunately, the above examples imply that the diode voltage is a relatively weak function of the device current and cross section area. With typical current levels and areas, VD falls in the range of 700–800 mV. For this reason, we often approximate the forward bias voltage by a constant value of 800 mV (like an ideal battery), considering the device fully off if VD < 800 mV. The resulting characteristic is illustrated in Fig. 2.33(a) with the turn-on voltage denoted by VD,on . Note that the current goes to infinity as VD tends to exceed VD,on because we assume the forwardbiased diode operates as an ideal voltage source. Neglecting the leakage current in reverse bias, we derive the circuit model shown in Fig. 2.33(b). We say the junction operates as an open circuit if VD < VD,on and as a constant voltage source if we attempt to increase VD beyond VD,on . While not essential, the voltage source placed in series with the switch in the off condition helps simplify the analysis of circuits: we can say that in the transition from off to on, only the switch turns on and the battery always resides in series with the switch. A number of questions may cross the reader’s mind at this point. First, why do we subject the diode to such a seemingly inaccurate approximation? Second, if we indeed intend to use this simple approximation, why did we study the physics of semiconductors and pn junctions in such detail? The developments in this chapter are representative of our treatment of all semiconductor devices: we carefully analyze the structure and physics of the device to understand its operation; we construct a “physics-based” circuit model; and we seek to approximate the resulting model, thus arriving at progressively simpler representations. Device models Reverse Bias

ID

V D,on Forward Bias V D,on

VD

(a) Figure 2.33

Constant-voltage diode model.

V D,on (b)

40

Chapter 2 Basic Physics of Semiconductors having different levels of complexity (and, inevitably, different levels of accuracy) prove essential to the analysis and design of circuits. Simple models allow a quick, intuitive understanding of the operation of a complex circuit, while more accurate models reveal the true performance.

Example 2.21

Consider the circuit of Fig. 2.34. Calculate IX for VX = 3 V and VX = 1 V using (a) an exponential model with IS = 10−16 A and (b) a constant-voltage model with VD,on = 800 mV. IX R 1 = 1 kΩ

VX

Figure 2.34

Solution

VD

D1

Simple circuit using a diode.

(a) Noting that ID = IX , we have VX = IX R1 + VD VD = VT ln

IX . IS

(2.114) (2.115)

This equation must be solved by iteration: we guess a value for VD , compute the corresponding IX from IX R1 = VX − VD , determine the new value of VD from VD = VT ln (IX /IS ) and iterate. Let us guess VD = 750 mV and hence IX = =

VX − VD R1

(2.116)

3 V − 0.75 V 1 k

(2.117)

= 2.25 mA.

(2.118)

Thus, IX IS

(2.119)

= 799 mV.

(2.120)

VD = VT ln

With this new value of VD , we can obtain a more accurate value for IX : IX =

3 V − 0.799 V 1 k

= 2.201 mA.

(2.121) (2.122)

2.3 Reverse Breakdown

41

We note that the value of IX rapidly converges. Following the same procedure for VX = 1 V, we have IX =

1 V − 0.75 V 1 k

(2.123)

= 0.25 mA,

(2.124)

which yields VD = 0.742 V and hence IX = 0.258 mA. (b) A constant-voltage model readily gives IX = 2.2 mA for VX = 3 V

(2.125)

IX = 0.2 mA for VX = 1 V.

(2.126)

The value of IX incurs some error, but it is obtained with much less computational effort than that in part (a). Exercise

2.3

Repeat the above example if the cross section area of the diode is increased by a factor of 10.

REVERSE BREAKDOWN∗ Recall from Fig. 2.31 that the pn junction carries only a small, relatively constant current in reverse bias. However, as the reverse voltage across the device increases, eventually “breakdown” occurs and a sudden, enormous current is observed. Figure 2.35 plots the device I/V characteristic, displaying this effect.

ID

V BD VD Breakdown Figure 2.35

Reverse breakdown characteristic.

The breakdown resulting from a high voltage (and hence a high electric field) can occur in any material. A common example is lightning, in which case the electric field in the air reaches such a high level as to ionize the oxygen molecules, thus lowering the resistance of the air and creating a tremendous current. ∗

This section can be skipped in a first reading.

42

Chapter 2 Basic Physics of Semiconductors The breakdown phenomenon in pn junctions occurs by one of two possible mechanisms: “Zener effect” and “avalanche effect.”

2.3.1 Zener Breakdown The depletion region in a pn junction contains atoms that have lost an electron or a hole and, therefore, provide no loosely-connected carriers. However, a high electric field in this region may impart enough energy to the remaining covalent electrons to tear them from their bonds [Fig. 2.36(a)]. Once freed, the electrons are accelerated by the field and swept to the n side of the junction. This effect occurs at a field strength of about 106 V/cm (1 V/μm). E

n Si

p

Si

Si

Si e e Si Si

e Si

Si Si e Si

VR (a) Figure 2.36

E

n

p

e e e e e

e e e

e

VR (b)

(a) Release of electrons due to high electric field, (b) avalanche effect.

In order to create such high fields with reasonable voltages, a narrow depletion region is required, which from Eq. (2.76) translates to high doping levels on both sides of the junction (why?). Called the “Zener effect,” this type of breakdown appears for reverse bias voltages on the order of 3-8 V. 2.3.2 Avalanche Breakdown Junctions with moderate or low doping levels (<1015 cm3 ) generally exhibit no Zener breakdown. But, as the reverse bias voltage across such devices increases, an avalanche effect takes place. Even though the leakage current is very small, each carrier entering the depletion region experiences a very high electric field and hence a large acceleration, thus gaining enough energy to break the electrons from their covalent bonds. Called “impact ionization,” this phenomenon can lead to avalanche: each electron freed by the impact may itself speed up so much in the field as to collide with another atom with sufficient energy, thereby freeing one more covalent-bond electron. Now, these two electrons may again acquire energy and cause more ionizing collisions, rapidly raising the number of free carriers. An interesting contrast between Zener and avalanche phenomena is that they display opposite temperature coefficients (TCs): VBD has a negative TC for Zener effect and positive TC for avalanche effect. The two TCs cancel each other for VBD ≈ 3.5 V. For this reason, Zener diodes with 3.5-V rating find application in some voltage regulators. The Zener and avalanche breakdown effects do not damage the diodes if the resulting current remains below a certain limit given by the doping levels and the geometry of the junction. Both the breakdown voltage and the maximum allowable reverse current are specified by diode manufacturers.

Problems

43

PROBLEMS 2.1. The intrinsic carrier concentration of germanium (GE) is expressed as ni = 1.66 × 1015 T 3/2 exp

−Eg cm−3 , 2kT

(2.127)

where Eg = 0.66 eV. (a) Calculate ni at 300 K and 600 K and compare the results with those obtained in Example 2.1 for Si. (b) Determine the electron and hole concentrations if Ge is doped with P at a density of 5 × 1016 cm−3 . 2.2. The electrons in a piece of n-type semiconductor take 10 ps to cross from one end to another end when a potential of 1 V is applied across it. Find the length of the semiconductor bar. 2.3. A current of 0.05 μA flows through an n-type silicon bar of length 0.2 μm and cross section area of 0.01μm × 0.01 μm when a voltage of 1 V is applied across it. Find the doping level at room temperature.

2.7. Repeat Problem 2.6 for Example 2.10 but for x = 0 to x = ∞. Compare the results for linear and exponential profiles. *2.8. Repeat Problem 2.7 if the electron and hole profiles are “sharp” exponentials, i.e., they fall to negligible values at x = 2 μm and x = 0, respectively (Fig. 2.38). 16

5 x 10

16

2 x 10

Electrons

Holes

2

µm

x

Figure 2.38

2.9. A Si semiconductor cube with side equal to 1 μm is doped with 4 × 10−17 cm−3 phosphorous impurities. Calculate the drift current when a voltage of 5 V is applied across it.

2.4. Repeat Problem 2.3 for Ge. Assume μn = 2.10. One side of pn junction is doped with 3900 cm2 /(V · s) and μ p = 1900 cm2 /(V · s). pentavalent impurities which gives a net 2.5. Figure 2.37 shows a p-type bar of silidoping of 5 × 1018 cm−3 . Find the doping con that is subjected to electron injection concentration to be added to the other side from the left and hole injection from the to get a built-in potential of 0.6 V at room right. Determine the total current flowing temperature. through the device if the cross section area 2.11. The built-in potential of an equally doped is equal to 1 μm × 1 μm. pn junction is 0.65 V at room temperature. When the doping level in n-side 16 16 2 x 10 5 x 10 is doubled, keeping the doping of the p-side unchanged, calculate the new builtElectrons Holes in potential and the doping level in P and N region. 0

2

µm

x

Figure 2.37

2.6. In Example 2.9, compute the total number of electrons “stored” in the material from x = 0 to x = L. Assume the cross section area of the bar is equal to a.

2.12. A silicon pn junction diode having ND = 1015 cm−3 and NA = 1017 cm−3 gives a total depletion capacitance of 0.41 pF/m2 . Determine the voltage applied across the diode. 2.13. An oscillator application requires a variable capacitance with the characteristic shown in Fig. 2.39. Determine NA and ND .

44

Chapter 2 Basic Physics of Semiconductors C j (fF/ µ m 2 )

2.2

2.18. Consider the circuit shown in Fig. 2.42, where IS = 2 × 10−15 A. Calculate VD1 and IX for VX = 0.5 V, 0.8 V, 1 V, and 1.2 V. Note that VD1 changes little for VX ≥ 0.8 V. IX

1.3 –1.5

–0.5

V R (V)

R1

VX

2 kΩ D1

Figure 2.39

2.14. Two identical pn junction diodes are connected in series. Calculate the current flowing through each diode when a forward bias of 1 V is applied across the series combination. Assume the reverse saturation current is 1.44 × 10−17 A for each diode. 2.15. Figure 2.40 shows two diodes with reverse saturation currents of IS1 and IS2 placed in parallel. (a) Prove that the parallel combination operates as an exponential device. (b) If the total current is Itot , determine the current carried by each diode.

Figure 2.42

2.19. For what value of VX in Fig. 2.42, does R1 sustain a voltage equal to VX /2? Assume IS = 2 × 10−16 A. 2.20. We have received the circuit shown in Fig. 2.43 and wish to determine R1 and IS . We note that VX = 1 V → IX = 0.2 mA and VX = 2 V → IX = 0.5 mA. Calculate R1 and IS . IX R1

VX

D1

I tot Figure 2.43

VB

D1

D2

Figure 2.40

2.16. Consider a pn junction in forward bias. Initially a current of 1 mA flows through it, and the current increases by 10 times when the forward voltage is increased by 1.5 times. Determine the initial bias applied and reverse saturation current.

*2.21. Figure 2.44 depicts a parallel resistor-diode combination. If IS = 3 × 10−16 A, calculate VD1 for IX = 1 mA, 2 mA, and 4 mA. IX

R1

1 kΩ

D1

Figure 2.44

2.22. In the circuit of Fig. 2.44, we wish D1 to carry a current of 0.5 mA for IX = 1.3 mA. Determine the required IS .

2.17. Figure 2.41 shows two diodes with reverse saturation currents of IS1 and IS2 placed in series. Calculate IB , VD1 , and VD2 in terms * 2.23. We have received the circuit shown in of VB , IS1 , and IS2 . Fig. 2.45 and wish to determine R1 and IS . Measurements indicate that IX = D1 D1 1 mA → VX = 1.2 V and IX = 2 mA → VX = 1.8 V. Calculate R1 and IS . IB

V D1

V D2

IX VB Figure 2.41

VX

Figure 2.45

R1

D1

Reference **2.24. In the circuit of Fig. 2.46, determine the **2.25. value of R1 such that this resistor carries 0.5 mA. Assume IS = 5 × 10−16 A for each diode.

IX

D1 1 mA R 1

D2

Figure 2.46

45

The circuit illustrated in Fig. 2.47 employs two identical diodes with IS = 5 × 10−16 A. Calculate the voltage across R1 for IX = 2 mA.

IX

R1

2 kΩ

D1 D2

Figure 2.47

SPICE PROBLEMS In the following problems, assume IS = 5 × 10−16 A. 2.1. For the circuit shown in Fig. 2.48, plot Vout as a function of Iin . Assume Iin varies from 0 to 2 mA. I in

D1

Vout

value of Iin are the currents flowing through D1 and R1 equal?

I in

D1

R1

Vout

Figure 2.49

Figure 2.48

2.2. Repeat Problem 2.1 for the circuit depicted in Fig. 2.49, where R1 = 1 k. At what

2.3. Using SPICE, determine the value of R1 in Fig. 2.49 such that D1 carries 1 mA if Iin = 2 mA.

REFERENCE 1. B. Streetman and S. Banerjee, Solid-State Electronic Device, fifth edition, Prentice-Hall, 1999.

Chapter

3

Diode Models and Circuits

Having studied the physics of diodes in Chapter 2, we now rise to the next level of abstraction and deal with diodes as circuit elements, ultimately arriving at interesting and real-life applications. This chapter also prepares us for understanding transistors as circuit elements in subsequent chapters. We proceed as follows:

Diodes as Circuit Elements • Ideal Diode • Circuit Characteristics • Actual Diode

3.1

Applications

➤

• Regulators • Rectifiers • Limiting and Clamping Circuits

IDEAL DIODE 3.1.1 Initial Thoughts In order to appreciate the need for diodes, let us briefly study the design of a cellphone charger. The charger converts the line ac voltage at 110 V1 and 60 Hz2 to a dc voltage of 3.5 V. As shown in Fig. 3.1(a), this is accomplished by first stepping down the ac voltage by means of a transformer to about 4 V and subsequently converting the ac voltage to a dc quantity.3 The same principle applies to adaptors that power other electronic devices. How does the black box in Fig. 3.1(a) perform this conversion? As depicted in Fig. 3.1(b), the output of the transformer exhibits a zero dc content because the negative and positive half cycles enclose equal areas, leading to a zero average. Now suppose this waveform is applied to a mysterious device that passes the positive half cycles but √ This value refers to the root-mean-square (rms) voltage. The peak value is therefore equal to 110 2. 2 The line ac voltage in most countries is at 220 V and 50 Hz. 3 The actual operation of adaptors is somewhat different. 1

46

3.1 Ideal Diode V1

47

60 Hz 4 2 t

60 Hz

V line 110 2

Block Box

V1

t

Vout

3.5 V t

(a) V1 ?

4 2 t

t Positive Areas

Equal Positive and Negative Areas (b) Figure 3.1

(a) Charger circuit, (b) elimination of negative half cycles.

blocks the negative ones. The result displays a positive average and some ac components, which can be removed by a low-pass filter (Section 3.5.1). The waveform conversion in Fig. 3.1(b) points to the need for a device that discriminates between positive and negative voltages, passing only one and blocking the other. A simple resistor cannot serve in this role because it is linear. That is, Ohm’s law, V = IR, implies that if the voltage across a resistor goes from positive to negative, so does the current through it. We must therefore seek a device that behaves as a short for positive voltages and as an open for negative voltages. Figure 3.2 summarizes the result of our thought process thus far. The mysterious device generates an output equal to the input for positive half cycles and equal to zero for negative half cycles. Note that the device is nonlinear because it does not satisfy y = αx; if x → −x, y → / −y.

y (t ) t

x (t ) t Figure 3.2

Conceptual operation of a diode.

48

Chapter 3 Diode Models and Circuits 3.1.2 Ideal Diode The mysterious device mentioned above is called an “ideal diode.” Shown in Fig. 3.3(a), the diode is a two-terminal device, with the triangular head denoting the allowable direction of current flow and the vertical bar representing the blocking behavior for currents in the opposite direction. The corresponding terminals are called the “anode” and the “cathode,” respectively.

D1 Anode

Forward Bias

Reverse Bias

IX

Cathode

(a)

(b) Forward Bias

Hinge

Pipe

Reverse Bias

Valve Stopper Figure 3.3

(c)

(a) Diode symbol, (b) equivalent circuit, (c) water pipe analogy.

Forward and Reverse Bias To serve as the mysterious device in the charger example of Fig. 3.3(a), the diode must turn “on” if Vanode > Vcathode and “off” if Vanode

Example 3.1

As with other two-terminal devices, diodes can be placed in series (or in parallel). Determine which one of the configurations in Fig. 3.4 can conduct current.

A

D1

D2 B

C

A

(a) Figure 3.4

D1

D2 B (b)

C

A

D1

D2 B (c)

Series combinations of diodes.

4 In our drawings, we sometimes place more positive nodes higher to provide a visual picture of the circuit’s operation. The diodes in Fig. 3.3(b) are drawn according to this convention.

3.1 Ideal Diode

49

Solution

In Fig. 3.4(a), the anodes of D1 and D2 point to the same direction, allowing the flow of current from A to B to C but not in the reverse direction. In Fig. 3.4(b), D1 stops current flow from B to A, and D2 , from B to C. Thus, no current can flow in either direction. By the same token, the topology of Fig. 3.4(c) behaves as an open for any voltage. Of course, none of these circuits appears particularly useful at this point, but they help us become comfortable with diodes.

Exercise

Determine all possible series combinations of three diodes and study their conduction properties.

I/V Characteristics In studying electronic devices, it is often helpful to accompany equations with graphical visualizations. A common type of plot is that of the current/voltage (I/V) characteristic, i.e., the current that flows through the device as a function of the voltage across it. Since an ideal diode behaves as a short or an open, we first construct the I/V characteristics for two special cases of Ohm’s law: V R=0 ⇒ I= =∞ (3.1) R V = 0. (3.2) R=∞ ⇒ I= R The results are illustrated in Fig. 3.5(a). For an ideal diode, we combine the positive-voltage region of the first with the negative-voltage region of the second, arriving at the ID /VD characteristic in Fig. 3.5(b). Here, VD = Vanode − Vcathode , and ID is defined as the current flowing into the anode and out of the cathode. I

I R=0 V

ID Reverse Bias

R= V

(a) Figure 3.5

Forward Bias VD

(b)

I/V characteristics of (a) zero and infinite resistors, (b) ideal diode.

Example 3.2

We said that an ideal diode turns on for positive anode-cathode voltages. But the characteristic in Fig. 3.5(b) does not appear to show any ID values for VD > 0. How do we interpret this plot?

Solution

This characteristic indicates that as VD exceeds zero by a very small amount, then the diode turns on and conducts infinite current if the circuit surrounding the diode can provide such a current. Thus, in circuits containing only finite currents, a forward-biased ideal diode sustains a zero voltage—similar to a short circuit.

Exercise

How is the characteristic modified if we place a 1- resistor in series with the diode?

50

Chapter 3 Diode Models and Circuits

Example 3.3

Plot the I/V characteristic for the “antiparallel” diodes shown in Fig. 3.6(a).

IA

IA VA

D1

D2 VA

(a) Figure 3.6

(b)

(a) Antiparallel diodes, (b) resulting I/V characteristic.

Solution

If VA > 0, D1 is on and D2 is off, yielding IA = ∞. If VA < 0, D1 is off, but D2 is on, again leading to IA = ∞. The result is illustrated in Fig. 3.6(b). The antiparallel combination therefore acts as a short for all voltages. Seemingly a useless circuit, this topology becomes much more interesting with actual diodes (Section 3.5.3).

Exercise

Repeat the above example if a 1-V battery is placed in series with the parallel combination of the diodes.

Example 3.4

Plot the I/V characteristic for the diode-resistor combination of Fig. 3.7(a).

IA

VA

D1

IA

IA

D1

R1

R1

R1 (a)

D1

(b)

R1

R1

(c) IA

IA 1 R1

VA VA

(d)

D1 R1 (e)

(a) Diode-resistor series combination, (b) equivalent circuit under forward bias, (c) equivalent circuit under reverse bias, (d) I/V characteristic, (e) equivalent circuit if D1 is on.

Figure 3.7

3.1 Ideal Diode

51

Solution

We surmise that, if VA > 0, the diode is on [Fig. 3.7(b)] and IA = VA /R1 because VD1 = 0 for an ideal diode. On the other hand, if VA < 0, D1 is probably off [Fig. 3.7(c)] and ID = 0. Figure 3.7(d) plots the resulting I/V characteristic. The above observations are based on guesswork. Let us study the circuit more rigorously. We begin with VA < 0, postulating that the diode is off. To confirm the validity of this guess, let us assume D1 is on and see if we reach a conflicting result. If D1 is on, the circuit is reduced to that in Fig. 3.7(e), and if VA is negative, so is IA ; i.e., the actual current flows from right to left. But this implies that D1 carries a current from its cathode to its anode, violating the definition of the diode. Thus, for VA < 0, D1 remains off and IA = 0. As VA rises above zero, it tends to forward bias the diode. Does D1 turn on for any VA > 0 or does R1 shift the turn-on point? We again invoke proof by contradiction. Suppose for some VA > 0, D1 is still off, behaving as an open circuit and yielding IA = 0. The voltage drop across R1 is therefore equal to zero, suggesting that VD1 = VA and hence ID1 = ∞ and contradicting the original assumption. In other words, D1 turns on for any VA > 0.

Exercise

Repeat the above analysis if the terminals of the diode are swapped.

The above example leads to two important points. First, the series combination of D1 and R1 acts as an open for negative voltages and as a resistor of value R1 for positive voltages. Second, in the analysis of circuits, we can assume an arbitrary state (on or off) for each diode and proceed with the computation of voltages and currents; if the assumptions are incorrect, the final result contradicts the original assumptions. Of course, it is helpful to first examine the circuit carefully and make an intuitive guess.

Example 3.5

Why are we interested in I/V characteristics rather than V/I characteristics?

Solution

In the analysis of circuits, we often prefer to consider the voltage to be the “cause” and the current, the “effect.” This is because in typical circuits, voltage polarities can be predicted more readily and intuitively than current polarities. Also, devices such as transistors fundamentally produce current in response to voltage.

Exercise

Plot the V/I characteristic of an ideal diode.

Example 3.6

In the circuit of Fig. 3.8, each input can assume a value of either zero or +3 V. Determine the response observed at the output.

Solution

If VA = +3 V, and VB = 0, then we surmise that D1 is forward-biased and D2 , reversebiased. Thus, Vout = VA = +3 V. If uncertain, we can assume both D1 and D2 are

52

Chapter 3 Diode Models and Circuits forward-biased, immediately facing a conflict: D1 enforces a voltage of +3 V at the output whereas D2 shorts Vout to VB = 0. This assumption is therefore incorrect.

VA VB

D1 Vout

D2 RL

Figure 3.8

OR gate realized by diodes.

The symmetry of the circuit with respect to VA and VB suggests that Vout = VB = +3 V if VA = 0 and VB = +3 V. The circuit operates as a logical OR gate and was in fact used in early digital computers. Exercise

Construct a three-input OR gate.

Example 3.7

Is an ideal diode on or off if VD = 0?

Solution

An ideal diode experiencing a zero voltage must carry a zero current (why?). However, this does not mean it acts as an open circuit. After all, a piece of wire experiencing a zero voltage behaves similarly. Thus, the state of an ideal diode with VD = 0 is somewhat arbitrary and ambiguous. In practice, we consider slightly positive or negative voltages to determine the response of a diode circuit.

Exercise

Repeat the above example if a 1- resistor is placed in series with the diode.

Input/Output Characteristics Electronic circuits process an input and generate a corresponding output. It is therefore instructive to construct the input/output characteristics of a circuit by varying the input across an allowable range and plotting the resulting output. As an example, consider the circuit depicted in Fig. 3.9(a), where the output is defined as the voltage across D1 . If Vin < 0, D1 is reverse biased, reducing the circuit to that in Fig. 3.9(b). Since no current flows through R1 , we have Vout = Vin . If Vin > 0, then D1 is forward biased, shorting the output and forcing Vout = 0 [Fig. 3.9(c)]. Figure 3.9(d) illustrates the overall input/output characteristic. 3.1.3 Application Examples Recall from Fig. 3.2 that we arrived at the concept of the ideal diode as a means of converting x(t) to y(t). Let us now design a circuit that performs this function. We may naturally construct the circuit as shown in Fig. 3.10(a). Unfortunately, however, the cathode of the diode is “floating,” the output current is always equal to zero, and the state of the diode is ambiguous. We therefore modify the circuit as depicted in Fig. 3.10(b) and analyze

3.1 Ideal Diode V in < 0 R1 V in

V in > 0

R1

R1

V in

Vout

D1

Vout

(a)

53

V in

Vout

(c)

(b) Vout

V in 1 (d) Figure 3.9 (a) Resistor-diode circuit, (b) equivalent circuit for negative input, (c) equivalent circuit

for positive input, (d) input/output characteristic.

D1

D1

V in

V in

Vout

(a)

R1

Vout

(b)

V in t

V in

V in

R1

Vout 1

R1

V in Rectified Half Cycles

Vout 0

T 2

T (c)

3T 2

2T t (d)

Figure 3.10 (a) A diode operating as a rectifier, (b) complete rectifier, (c) input and output waveforms, (d) input/output characteristic.

54

Chapter 3 Diode Models and Circuits its response to a sinusoidal input [Fig. 3.10(c)]. Since R1 has a tendency to maintain the cathode of D1 near zero, as Vin rises, D1 is forward biased, shorting the output to the input. This state holds for the positive half cycle. When Vin falls below zero, D1 turns off and R1 ensures that Vout = 0 because ID R1 = 0.5 The circuit of Fig. 3.10(b) is called a “rectifier.” It is instructive to plot the input/output characteristic of the circuit as well. Noting that if Vin < 0, D1 is off and Vout = 0, and if Vin > 0, D1 is on and Vout = Vin , we obtain the behavior shown in Fig. 3.10(d). The rectifier is a nonlinear circuit because if Vin → −Vin then Vout → / −Vout .

Example 3.8

Is it a coincidence that the characteristics in Figs. 3.7(d) and 3.10(d) look similar?

Solution

No, we recognize that the output voltage in Fig. 3.10(b) is simply equal to IA R1 in Fig. 3.7(a). Thus, the two plots differ by only a scaling factor equal to R1 .

Exercise

Construct the characteristic if the terminals of D1 are swapped.

We now determine the time average (dc value) of the output waveform in Fig. 3.10(c) to arrive at another interesting application. Suppose Vin = Vp sin ωt, where ω = 2π/T denotes the frequency in radians per second and T the period. Then, in the first cycle after t = 0, we have T (3.3) Vout = Vp sin ωt for 0 ≤ t ≤ 2 T ≤ t ≤ T. (3.4) = 0 for 2 To compute the average, we obtain the area under Vout and normalize the result to the period: 1 T Vout,avg = Vout (t) dt (3.5) T 0 1 T

T/2

Vp sin ωt dt

(3.6)

=

1 Vp T/2 · [−cos ωt]0 T ω

(3.7)

=

Vp . π

(3.8)

=

Thus, the average is proportional to Vp , an expected result because a larger input amplitude yields a greater area under the rectified half cycles. The above observation reveals that the average value of a rectified output can serve as a measure of the “strength” (amplitude) of the input. That is, a rectifier can operate as a “signal strength indicator.” For example, since cellphones receive varying levels of signal depending on the user’s location and environment, they require an indicator to determine how much the signal must be amplified. 5

Note that without R1 , the output voltage is not defined because a floating node can assume any potential.

3.1 Ideal Diode

55

Example 3.9

A cellphone receives a 1.8-GHz signal with a peak amplitude ranging from 2 μV to 10 mV. If the signal is applied to a rectifier, what is the corresponding range of the output average?

Solution

The rectified output exhibits an average value ranging from 2 μV/(π ) = 0.637 μV to 10 mV/(π) = 3.18 mV.

Exercise

Do the above results change if a 1- resistor is placed in series with the diode?

In our effort toward understanding the role of diodes, we examine another circuit that will eventually (in Section 3.5.3) lead to some important applications. First, consider the topology in Fig. 3.11(a), where a 1-V battery is placed in series with an ideal diode. How does this circuit behave? If V1 < 0, the cathode voltage is higher than the anode voltage, placing D1 in reverse bias. Even if V1 is slightly greater than zero, e.g., equal to 0.9 V, the anode is not positive enough to forward bias D1 . Thus, V1 must approach +1 V for D1

I1 I1 D1

V1

VB

1V +1 V

V1

(a)

V in

Vout

V in

R1 Vout

D1

t V in

Vout 1 t

(b)

V in

+ Vp

V in

R1 D1 VB

1V

Vout

t Vp Vout

Vout +1 V

+1V t Vp

+1 V

V in

1

(c) Figure 3.11

(a) Diode-battery circuit, (b) resistor-diode circuit, (c) addition of series battery to (b).

56

Chapter 3 Diode Models and Circuits to turn on. Shown in Fig. 3.11(a), the I/V characteristic of the diode-battery combination resembles that of a diode, but shifted to the right by 1 V. Now, let us examine the circuit in Fig. 3.11(b). Here, for Vin < 0, D1 remains off, yielding Vout = Vin . For Vin > 0, D1 acts a short, and Vout = 0. The circuit therefore does not allow the output to exceed zero, as illustrated in the output waveform and the input/output characteristic. But suppose we seek a circuit that must not allow the output to exceed +1 V (rather than zero). How should the circuit of Fig. 3.11(b) be modified? In this case, D1 must turn on only when Vout approaches +1 V, implying that a 1-V battery must be inserted in series with the diode. Depicted in Fig. 3.11(c), the modification indeed guarantees Vout ≤ +1 V for any input level. We say the circuit “clips” or “limits” at +1 V. “Limiters” prove useful in many applications and are described in Section 3.5.3.

Example 3.10

Sketch the time average of Vout in Fig. 3.11(c) for a sinusoidal input as the battery voltage, VB , varies from −∞ to +∞.

Solution

If VB is very negative, D1 is always on because Vin ≥ −Vp . In this case, the output average is equal to VB [Fig. 3.12(a)]. For −Vp

VB < –Vp V in

V in t

VB

VB

– Vp

t – Vp

Vout = VB VB = 0

+ Vp < VB

VB

V in VB

Vout

Vout

+ Vp

t

t

Vout

– Vp

(a) Vout – Vp

+ Vp – Vp – Vp

VB

π

1 (b)

Figure 3.12

Exercise

Repeat the above example if the terminals of the diode are swapped.

3.2 pn Junction as a Diode

57

Example 3.11

Is the circuit of Fig. 3.11(b) a rectifier?

Solution

Yes, indeed. The circuit passes only negative cycles to the output, producing a negative average.

Exercise

How should the circuit of Fig. 3.11(b) be modified to pass only positive cycles to the output?

3.2

pn JUNCTION AS A DIODE The operation of the ideal diode is somewhat reminiscent of the current conduction in pn junctions. In fact, the forward and reverse bias conditions depicted in Fig. 3.3(b) are quite similar to those studied for pn junctions in Chapter 2. Figures 3.13(a) and (b) plot the I/V characteristics of the ideal diode and the pn junction, respectively. The latter can serve as an approximation of the former by providing “unilateral” current conduction. Shown in Fig. 3.13 is the constant-voltage model developed in Chapter 2, providing a simple approximation of the exponential function and also resembling the characteristic plotted in Fig. 3.11(a). ID

Ij

Vj

VD (a)

(b) ID V D,on V D,on

VD

V D,on (c)

Figure 3.13 Diode characteristics: (a) ideal model, (b) exponential model, (c) constantvoltage model.

Given a circuit topology, how do we choose one of the above models for the diodes? We may utilize the ideal model so as to develop a quick, rough understanding of the circuit’s operation. Upon performing this exercise, we may discover that this idealization is inadequate and hence employ the constant-voltage model. This model suffices in most cases, but we may need to resort to the exponential model for some circuits. The following examples illustrate these points. It is important to bear in mind two peinciples: (1) if a diode is at the edge of turning on or off, then ID ≈ 0 and VD ≈ VD,on ; (2) if a diode is on I D must flow from anode to cathode.

58

Chapter 3 Diode Models and Circuits

Example 3.12

Plot the input/output characteristic of the circuit shown in Fig. 3.14(a) using (a) the ideal model and (b) the constant-voltage model.

V in

R1

Vout

Vout

R2 R2 + R1

R2

V in

D1 1 (a)

V in

(b) Vout

R1

Vout

R2 R2 + R1

V D,on

R2 V D,on

V D,on

V in

1 (c)

(d)

Figure 3.14 (a) Diode circuit, (b) input/output characteristic with ideal diode model, (c) input/output characteristic with constant-voltage diode model. Solution

(a) We begin with Vin = −∞, recognizing that D1 is reverse biased. In fact, for Vin < 0, the diode remains off and no current flows through the circuit. Thus, the voltage drop across R1 is zero and Vout = Vin . As Vin exceeds zero, D1 turns on, operating as a short and reducing the circuit to a voltage divider. That is, Vout =

R2 Vin R1 + R 2

for

Vin > 0.

(3.9)

Figure 3.14(b) plots the overall characteristic, revealing a slope equal to unity for Vin < 0 and R2 /(R2 + R1 ) for Vin > 0. In other words, the circuit operates as a voltage divider once the diode turns on and loads the output node with R2 . (b) In this case, D1 is reverse biased for Vin < VD,on , yielding Vout = Vin . As Vin exceeds VD,on , D1 turns on, operating as a constant voltage source with a value VD,on [as illustrated in Fig. 3.13(c)]. Reducing the circuit to that in Fig. 3.14(c), we apply Kirchoff’s current law to the output node: Vin − Vout Vout − VD,on = . R1 R2

(3.10)

It follows that

Vout

R2 Vin + VD,on R = 1 . R2 1+ R1

(3.11)

3.3 Additional Examples

59

As expected, Vout = VD,on if Vin = VD,on . Figure 3.14(d) plots the resulting characteristic, displaying the same shape as that in Fig. 3.14(b) but with a shift in the break point. Exercise

In the above example, plot the current through R1 as a function of Vin .

It is important to remember that a diode about to turn on or off carries no current but sustains a voltage equal to VD,on .

3.3 Example 3.13

ADDITIONAL EXAMPLES* In the circuit of Fig. 3.15, D1 and D2 have different cross section areas but are otherwise identical. Determine the current flowing through each diode.

1

in

D1

1

Figure 3.15 Solution

D2

Diode circuit.

In this case, we must resort to the exponential equation because the ideal and constantvoltage models do not include the device area. We have Iin = ID1 + ID2 . (3.12) We also equate the voltages across D1 and D2 : VT ln that is,

ID1 ID2 = VT ln ; IS1 IS2

(3.13)

ID2 ID1 = . IS1 IS2

(3.14)

Solving (3.13) and (3.15) together yields Iin IS2 1+ IS1 Iin = . IS1 1+ IS2

ID1 =

(3.15)

ID2

(3.16)

As expected, ID1 = ID2 = Iin /2 if IS1 = IS2 . Exercise

For the circuit of Fig. 3.15, calculate VD is terms of Iin , IS1 , and IS2 . ∗

This section can be skipped in a first reading.

60

Chapter 3 Diode Models and Circuits

Example 3.14

Using the constant-voltage model, plot the input/output characteristics of the circuit depicted in Fig. 3.16(a). Note that a diode about to turn on carries zero current but sustains VD,on .

V in

R1

V in

Vout

R1

R2 D1

Vout R2

(a)

(b) Vout

V D,on

R2 R2 + R1

(1 +

R1 ) V D,on R2

V in

(c) Figure 3.16 (a) Diode circuit, (b) equivalent circuit when D1 is off, (c) input/output characteristic. Solution

In this case, the voltage across the diode happens to be equal to the output voltage. We note that if Vin = −∞, D1 is reverse biased and the circuit reduces to that in Fig. 3.16(b). Consequently, vout =

R2 Vin . R1 + R 2

(3.17)

At what point does D1 turn on? The diode voltage must reach VD,on , requiring an input voltage given by: R2 Vin = VD,on , R1 + R 2

(3.18)

R1 Vin = 1 + VD,on . R2

(3.19)

and hence

The reader may question the validity of this result: if the diode is indeed on, it draws current and the diode voltage is no longer equal to [R2 /(R1 + R2 )]Vin . So why did we express the diode voltage as such in Eq. (3.18)? To determine the break point, we assume Vin gradually increases so that it places the diode at the edge of the turn-on, e.g., it creates

3.3 Additional Examples

61

Vout ≈ 799 mV. The diode therefore still draws no current, but the voltage across it and hence the input voltage are almost sufficient to turn it on. For Vin > (1 + R1 /R2 )VD,on , D1 remains forward-biased, yielding Vout = VD,on . Figure 3.16(c) plots the overall characteristic. Exercise

Repeat the above example but assume the terminals of D1 are swapped, i.e., the anode is tied to ground and the cathode the output node.

Exercise

For the above example, plot the current through R1 as a function of Vin .

Example 3.15

Plot the input/output characteristic for the circuit shown in Fig. 3.17(a). Assume a constant-voltage model for the diode.

D1 V in

X R2

X

Vout V D,on

R1

R1

D1

Vout R2

V in = – (a)

(b) Vout

V in

R2

Vout R1

R1 R1 + R2

R ( 1 + 1 ) V D,on R2

V in 1 (c)

(d)

Figure 3.17 (a) Diode circuit, (b) illustration for very negative inputs, (c) equivalent circuit when D1 is off, (d) input/output characteristic. Solution

We begin with Vin = −∞, and redraw the circuit as depicted in Fig. 3.17(b), placing the more negative voltages on the bottom and the more positive voltages on the top. This diagram suggests that the diode operates in forward bias, establishing a voltage at node X equal to Vin + VD,on . Note that in this regime, VX is independent of R2 because D1 acts as a battery. Thus, so long as D1 is on, we have Vout = Vin + VD,on .

(3.20)

62

Chapter 3 Diode Models and Circuits We also compute the current flowing through R2 and R1 : IR2 =

VD,on R2

(3.21)

IR1 =

0 − VX R1

(3.22)

−(Vin + VD,on ) . R1

(3.23)

=

Thus, as Vin increases from −∞, IR2 remains constant but |IR1 | decreases; i.e., at some point IR2 = IR1 . At what point does D1 turn off? Interestingly, in this case it is simpler to seek the condition that results in a zero current through the diode rather than insufficient voltage across it. The observation that at some point, IR2 = IR1 proves useful here as this condition also implies that D1 carries no current (KCL at node X). In other words, D1 turns off if Vin is chosen to yield IR2 = IR1 . From (3.21) and (3.23), VD,on Vin + VD,on =− R2 R1 and hence

R1 Vin = − 1 + R2

(3.24)

VD,on .

(3.25)

As Vin exceeds this value, the circuit reduces to that shown in Fig. 3.17(c) and Vout =

R1 Vin . R1 + R 2

(3.26)

The overall characteristic is shown in Fig. 3.17(d). The reader may find it interesting to recognize that the circuits of Figs. 3.16(a) and 3.17(a) are identical: in the former, the output is sensed across the diode whereas in the latter it is sensed across the series resistor. Exercise

Repeat the above example if the terminals of the diode are swapped.

As mentioned in Example 3.4, in more complex circuits, it may be difficult to correctly predict the region of operation of each diode by inspection. In such cases, we may simply make a guess, proceed with the analysis, and eventually determine if the final result agrees or conflicts with the original guess. Of course, we still apply intuition to minimize the guesswork. The following example illustrates this approach.

Example 3.16

Plot the input/output characteristic of the circuit shown in Fig. 3.18(a) using the constantvoltage diode model.

Solution

We begin with Vin = −∞, predicting intuitively that D1 is on. We also (blindly) assume that D2 is on, thus reducing the circuit to that in Fig. 3.18(b). The path through VD,on and

3.3 Additional Examples

I R2 = D1

I R1

V in Y

R1

VB = 2 V

Vout

VB

R1

Vout D2

R2 Vout

R1

X

R2

X

Y

V D,on

X

V in = –

(b) X

D1

Y

R1

VB

R1 Vout

D2

(d)

Y

VB = 2 V

R1

(e)

Vout

Vout D1

X

– V D,on V in

R1

– V D,on

V in

Vout Y

D2 D 1 turns off.

(f)

X

V in = – V D,on

Vout D2

(c)

R1

V in

Y

V D,on

V in = –

D1

VB

R1 I1=

V D,on

(a)

63

VB = 2 V

V in

R1

(g)

(h)

Figure 3.18 (a) Diode circuit, (b) possible equivalent circuit for very negative inputs, (c) simplified circuit, (d) equivalent circuit, (e) equivalent circuit for Vin = −VD,on , (f) section of input/output characteristic, (g) equivalent circuit, (f) complete input/ output characteristic.

VB creates a difference of VD,on + VB between Vin and Vout , i.e., Vout = Vin − (VD,on + VB ). This voltage difference also appears across the branch consisting of R1 and VD,on , yielding R1 IR1 + VD,on = −(VB + VD,on ),

(3.27)

and hence IR1 =

−VB − 2VD,on . R1

(3.28)

That is, IR1 is independent of Vin . We must now analyze these results to determine whether they agree with our assumptions regarding the state of D1 and D2 .

64

Chapter 3 Diode Models and Circuits Consider the current flowing through R2 : IR2 = − =−

Vout R2

(3.29)

Vin − (VD,on − VB ) , R2

(3.30)

which approaches +∞ for Vin = −∞. The large value of IR2 and the constant value of IR1 indicate that the branch consisting of VB and D2 carries a large current with the direction shown. That is, D2 must conduct current from its cathode to its anode, which is not possible. In summary, we have observed that the forward bias assumption for D2 translates to a current in a prohibited direction. Thus, D2 operates in reverse bias for Vin = −∞. Redrawing the circuit as in Fig. 3.18(c) and noting that VX = Vin + VD,on , we have Vout = (Vin + VD,on )

R2 . R1 + R 2

(3.31)

We now raise Vin and determine the first break point, i.e., the point at which D1 turns off or D2 turns on. Which one occurs first? Let us assume D1 turns off first and obtain the corresponding value of Vin . Since D2 is assumed off, we draw the circuit as shown in Fig. 3.18(d). Assuming that D1 is still slightly on, we recognize that at Vin ≈ −VD,on , VX = Vin + VD,on approaches zero, yielding a zero current through R1 , R2 , and hence D1 . The diode therefore turns off at Vin = −VD,on . We must now verify the assumption that D2 remains off. Since at this break point, VX = Vout = 0, the voltage at node Y is equal to +VB whereas the cathode of D2 is at −VD,on [Fig. 3.18(e)]. In other words, D2 is indeed off. Fig. 3.18(f) plots the input/output characteristic to the extent computed thus far, revealing that Vout = 0 after the first break point because the current flowing through R1 and R2 is equal to zero. At what point does D2 turn on? The input voltage must exceed VY by VD,on . Before D2 turns on, Vout = 0, and VY = VB ; i.e., Vin must reach VB + VD,on , after which the circuit is configured as shown in Fig. 3.18(g). Consequently, Vout = Vin − VD,on − VB .

(3.32)

Figure 3.18(h) plots the overall result, summarizing the regions of operation. Exercise

3.4

In the above example, assume D2 turns on before D1 turns off and show that the results conflict with the assumption.

LARGE-SIGNAL AND SMALL-SIGNAL OPERATION Our treatment of diodes thus far has allowed arbitrarily large voltage and current changes, thereby requiring a “general” model such as the exponential I/V characteristic. We call this regime “large-signal operation” and the exponential characteristic the “large-signal model” to emphasize that the model can accommodate arbitrary signal levels. However, as seen in previous examples, this model often complicates the analysis, making it difficult to develop an intuitive understanding of the circuit’s operation. Furthermore, as the

3.4 Large-Signal and Small-Signal Operation

65

number of nonlinear devices in the circuit increases, “manual” analysis eventually becomes impractical. The ideal and constant-voltage diode models resolve the issues to some extent, but the sharp nonlinearity at the turn-on point still proves problematic. The following example illustrates the general difficulty. Example 3.17

Having lost his 2.4-V cellphone charger, an electrical engineering student tries several stores but does not find adaptors with outputs less than 3 V. He then decides to put his knowledge of electronics to work and constructs the circuit shown in Fig. 3.19, where three identical diodes in forward bias produce a total voltage of Vout = 3VD ≈ 2.4 V and resistor R1 sustains the remaining 600 mV. Neglect the current drawn by the cellphone.6 (a) Determine the reverse saturation current, IS1 so that Vout = 2.4 V. (b) Compute Vout if the adaptor voltage is in fact 3.1 V. IX 600 mV Vad = 3 V

R 1 = 100 Ω

Adaptor Vout

Figure 3.19

Solution

Cellphone

Adaptor feeding a cellphone.

(a) With Vout = 2.4 V, the current flowing through R1 is equal to IX =

Vad − Vout R1

= 6 mA.

(3.33) (3.34)

We note that each diode carries IX and hence VD . VT

(3.35)

800 mV 26 mV

(3.36)

IS = 2.602 × 10−16 A.

(3.37)

IX = IS exp It follows that 6 mA = IS exp and

(b) If Vad increases to 3.1 V, we expect that Vout increases only slightly. To understand why, first suppose Vout remains constant and equal to 2.4 V. Then, the additional 0.1 V must drop across R1 , raising IX to 7 mA. Since the voltage across each diode has a 6

Made for the sake of simplicity here, this assumption may not be valid.

66

Chapter 3 Diode Models and Circuits logarithmic dependence upon the current, the change from 6 mA to 7 mA indeed yields a small change in Vout .7 To examine the circuit quantitatively, we begin with IX = 7 mA and iterate: Vout = 3VD = 3VT ln

(3.38) IX IS

= 2.412 V.

(3.39) (3.40)

This value of Vout gives a new value for IX : IX =

Vad − Vout R1

= 6.88 mA,

(3.41) (3.42)

which translates to a new Vout : Vout = 3VD = 2.411 V.

(3.43) (3.44)

Noting the very small difference between (3.40) and (3.44), we conclude that Vout = 2.411 V with good accuracy. The constant-voltage diode model would not be useful in this case. Exercise

Repeat the above example if an output voltage of 2.35 is desired.

The situation6 described above is an example of small “perturbations” in circuits. The change in Vad from 3 V to 3.1 V results in a small change in the circuit’s voltages and currents, motivating us to seek a simpler analysis method that can replace the nonlinear equations and the inevitable iterative procedure. Of course, since the above example does not present an overwhelmingly difficult problem, the reader may wonder if a simpler approach is really necessary. But, as seen in subsequent chapters, circuits containing complex devices such as transistors may indeed become impossible to analyze if the nonlinear equations are retained. These thoughts lead us to the extremely important concept of “small-signal operation,” whereby the circuit experiences only small changes in voltages and currents and can therefore be simplified through the use of “small-signal models” for nonlinear devices. The simplicity arises because such models are linear, allowing standard circuit analysis and obviating the need for iteration. The definition of “small” will become clear later. To develop our understanding of small-signal operation, let us consider diode D1 in Fig. 3.20(a), which sustains a voltage VD1 and carries a current ID1 [point A in Fig. 3.20(b)]. Now suppose a perturbation in the circuit changes the diode voltage by a small amount 67 Recall from Eq. (2.109) that a tenfold change in a diode’s current translates to a 60-mV change in its voltage.

3.4 Large-Signal and Small-Signal Operation

ID V D1 D1

67

ID

I D1 I D1

I D1

V D1 (a)

B

I D2

A

?

A V D1 V D2

VD

(b)

ΔV D VD

(c)

Figure 3.20 (a) General circuit containing a diode, (b) operating point of D1 , (c) change in ID as a result of change in VD .

VD [point B in Fig. 3.20(c)]. How do we predict the change in the diode current, ID ? We can begin with the nonlinear characteristic: ID2 = IS exp = IS exp

VD1 + V VT

(3.45)

VD1 V exp . VT VT

(3.46)

If V VT , then exp(V/VT ) ≈ 1 + V/VT and ID2 = IS exp

= ID1 +

VD1 V VD1 + IS exp VT VT VT

(3.47)

V ID1 . VT

(3.48)

That is, ID =

V ID1 . VT

(3.49)

The key observation here is that ID is a linear function of V, with a proportionality factor equal to ID1 /VT . (Note that larger values of ID1 lead to a greater ID for a given VD . The significance of this trend becomes clear later.) The above result should not come as a surprise: if the change in VD is small, the section of the characteristic in Fig. 3.20(c) between points A and B can be approximated by a straight line (Fig. 3.21), with a slope equal to the local slope of the characteristic.

I D2

ID I D2 I D1

Figure 3.21

A

A V D1 V D2

ΔI D

I D1

B

VD

Approximation of characteristic by a straight line.

B

ΔV D

68

Chapter 3 Diode Models and Circuits In other words, dI D ID = VD dVD VD=VD1

(3.50)

=

IS VD1 exp VT VT

(3.51)

=

ID1 , VT

(3.52)

which yields the same result as that in Eq. (3.49).8 Let us summarize our results thus far. If the voltage across a diode changes by a small amount (much less than VT ), then the change in the current is given by Eq. (3.49). Equivalently, for small-signal analysis, we can assume the operation is at a point such as A in Fig. 3.21 and, due to a small perturbation, it moves on a straight line to point B with a slope equal to the local slope of the characteristic (i.e., dI D /dVD calculated at VD = VD1 or ID = ID1 ). Point A is called the “bias” point, the “quiescent” point, or the “operating” point. Example 3.18

A diode is biased at a current of 1 mA. (a) Determine the current change if VD changes by 1 mV. (b) Determine the voltage change if ID changes by 10%.

Solution

(a) We have ID =

ID VD VT

= 38.4 μA.

(3.53) (3.54)

(b) Using the same equation yields VT ID ID 26 mV = × (0.1 mA) 1 mA

VD =

= 2.6 mV. Exercise

(3.55) (3.56) (3.57)

In response to a current change of 1 mA, a diode exhibits a voltage change of 3 mV. Calculate the bias current of the diode.

Equation (3.58) in the above example reveals an interesting aspect of small-signal operation: as far as (small) changes in the diode current and voltage are concerned, the 8 This is also to be expected. Writing Eq. (3.45) to obtain the change in ID for a small change in VD is in fact equivalent to taking the derivative.

3.4 Large-Signal and Small-Signal Operation

69

device behaves as a linear resistor. In analogy with Ohm’s Law, we define the “small-signal resistance” of the diode as: rd =

VT . ID

(3.58)

This quantity is also called the “incremental” resistance to emphasize its validity for small changes. In the above example, rd = 26 . Figure 3.22(a) summarizes the results of our derivations for a forward-biased diode. For bias calculations, the diode is replaced with an ideal voltage source of value VD,on , and for small changes, with a resistance equal to rd . For example, the circuit of Fig. 3.22(b) is transformed to that in Fig. 3.22(c) if only small changes in V1 and Vout are of interest. Note that v1 and vout in Fig. 3.22(c) represent changes in voltage and are called smallsignal quantities. In general, we denote small-signal voltages and currents by lower-case letters.

R1 VD,on

rd

Bias Model

V1

R1 D1

Vout

v1

v out

rd

Small-Signal Model (a)

(b)

(c)

Figure 3.22 Summary of diode models for bias and signal calculations, (b) circuit example, (c) small-signal model.

Example 3.19

A sinusoidal signal having a peak amplitude of Vp and a dc value of V0 can be expressed as V(t) = V0 + Vp cos ωt. If this signal is applied across a diode and Vp VT , determine the resulting diode current.

Solution

The signal waveform is illustrated in Fig. 3.23(a). As shown in Fig. 3.23(b), we rotate this diagram by 90◦ so that its vertical axis is aligned with the voltage axis of the diode characteristic. With a signal swing much less than VT , we can view V0 and the corresponding current, I0 , as the bias point of the diode and Vp as a small perturbation. It follows that I0 = IS exp

V0 , VT

(3.59)

and rd =

VT . I0

(3.60)

70

Chapter 3 Diode Models and Circuits ID

ID Ip

V (t )

I0

Vp

t

VD

V0

t

V0

t (a) Figure 3.23

(b)

(a) Sinusoidal input along with a dc level, (b) response of a diode to the sinusoid.

Thus, the peak current is simply equal to I p = Vp /rd = yielding

I0 Vp , VT

ID (t) = I0 + I p cos ωt = IS exp

Exercise

V0 I0 + Vp cos ωt. VT VT

(3.61) (3.62)

(3.63) (3.64)

The diode in the above example produces a peak current of 0.1 mA in response to V0 = 800 mV and Vp = 1.5 mV. Calculate IS .

The above example demonstrates the utility of small-signal analysis. If Vp were large, we would need to solve the following equation: ID (t) = IS exp

V0 + Vp cos ωt , VT

a task much more difficult than the above linear calculations.9

9

The function exp(a sin bt) can be approximated by a Taylor expansion or Bessel functions.

(3.65)

3.4 Large-Signal and Small-Signal Operation

71

Example 3.20

In the derivation leading to Eq. (3.49), we assumed a small change in VD and obtained the resulting change in ID . Beginning with VD = VT ln (ID /Is ), investigate the reverse case, i.e., ID changes by a small amount and we wish to compute the change in VD .

Solution

Denoting the change in VD by VD , we have ID1 + ID IS ID ID1 = VT ln 1+ IS ID1 ID1 ID = VT ln . + VT ln 1 + IS ID1

VD1 + VD = VT ln

(3.66) (3.67) (3.68)

For small-signal operation, we assume ID ID1 and note that ln (1 + ) ≈ if 1. Thus, VD = VT ·

ID , ID1

(3.69)

which is the same as Eq. (3.49). Figure 3.24 illustrates the two cases, distinguishing between the cause and the effect.

ΔID ΔV D

ΔID =

D1

= (a) Figure 3.24

Exercise

ΔV D

ΔID

rd

ΔV D

I D1 VT

D1

ΔV D

ΔV D = Δ I D r d =

ΔI D

(b)

VT I D1

Change in diode current (voltage) due to a change in voltage (current).

Repeat the above example by taking the derivative of the diode voltage equation with respect to ID .

With our understanding of small-signal operation, we now revisit Example 3.17. Example 3.21

Repeat part (b) of Example 3.17 with the aid of a small-signal model for the diodes.

Solution

Since each diode carries ID1 = 6 mA with an adaptor voltage of 3 V and VD1 = 800 mV, we can construct the small-signal model shown in Fig. 3.25, where vad = 100 mV and rd = (26 mV)/(6 mA) = 4.33 . (As mentioned earlier, the voltages shown in this model denote small changes.) We can thus write: vout =

3rd vad R1 + 3rd

= 11.5 mV.

(3.70) (3.71)

72

Chapter 3 Diode Models and Circuits R1

rd

v ad

rd

v out

rd Figure 3.25

Small-signal model of adaptor.

That is, a 100-mV change in Vad yields an 11.5-mV change in Vout . In Example 3.17, solution of nonlinear diode equations predicted an 11-mV change in Vout . The small-signal analysis therefore offers reasonable accuracy while requiring much less computational effort. Exercise

Repeat Examples (3.17) and (3.21) if the value of R1 in Fig. 3.19 is changed to 200 .

Considering the power of today’s computer software tools, the reader may wonder if the small-signal model is really necessary. Indeed, we utilize sophisticated simulation tools in the design of integrated circuits today, but the intuition gained by hand analysis of a circuit proves invaluable in understanding fundamental limitations and various trade-offs that eventually lead to a compromise in the design. A good circuit designer analyzes and understands the circuit before giving it to the computer for a more accurate analysis. A bad circuit designer, on the other hand, allows the computer to think for him/her.

Example 3.22

In Examples 3.17 and 3.21, the current drawn by the cellphone is neglected. Now suppose, as shown in Fig. 3.26, the load pulls a current of 0.5 mA10 and determine Vout .

~6 mA

R 1 = 100 Ω 0.5 mA

V ad Vout

Figure 3.26

10

Adaptor feeding a cellphone.

A cellphone in reality draws a much higher current.

Cellphone

3.5 Applications of Diodes Solution

Since the current flowing through the diodes decreases by 0.5 mA and since this change is much less than the bias current (6 mA), we write the change in the output voltage as: Vout = ID · (3rd )

Exercise

73

(3.72)

= 0.5 mA(3 × 4.33 )

(3.73)

= 6.5 mV.

(3.74)

Repeat the above example if R1 is reduced to 80 .

In summary, the analysis of circuits containing diodes (and other nonlinear devices such as transistors) proceeds in three steps: (1) determine—perhaps with the aid of the constant-voltage model—the initial values of voltages and currents (before an input change is applied); (2) develop the small-signal model for each diode (i.e., calculate rd ); (3) replace each diode with its small-signal model and compute the effect of the input change.

3.5

APPLICATIONS OF DIODES The remainder of this chapter deals with circuit applications of diodes. A brief outline is shown below.

Half-Wave and Full-Wave rectifiers Figure 3.27

Limiting Circuits

Voltage Doublers

Level Shifters and Switches

Applications of diodes.

3.5.1 Half-Wave and Full-Wave Rectifiers Half-Wave Rectifier Let us return to the rectifier circuit of Fig. 3.10(b) and study it more closely. In particular, we no longer assume D1 is ideal, but use a constant-voltage model. As illustrated in Fig. 3.28, Vout remains equal to zero until Vin exceeds VD,on , at which point D1 turns on and Vout = Vin − VD,on . For Vin

D1 V in

R1

Vout

V out

V D,on t V D,on

Figure 3.28

11

Simple rectifier.

If Vin < 0, D1 carries a small leakage current, but the effect is negligible.

74

Chapter 3 Diode Models and Circuits

Example 3.23

Prove that the circuit shown in Fig. 3.29(a) is also a rectifier.

V in

D1 V in

R1

Vout

t V out

(a) Figure 3.29

(b)

Rectification of positive cycles.

Solution

In this case, D1 remains on for negative values of Vin , specifically, for Vin ≤ −VD,on . As Vin exceeds −VD,on , D1 turns off, allowing R2 to maintain Vout = 0. Depicted in Fig. 3.29, the resulting output reveals that this circuit is also a rectifier, but it blocks the positive cycles.

Exercise

Plot the output if D1 is an ideal diode.

Called a “half-wave rectifier,” the circuit of Fig. 3.28 does not produce a useful output. Unlike a battery, the rectifier generates an output that varies considerably with time and cannot supply power to electronic devices. We must therefore attempt to create a constant output. Fortunately, a simple modification solves the problem. As depicted in Fig. 3.30(a), the resistor is replaced with a capacitor. The operation of this circuit is quite different from that of the above rectifier. Assuming a constant-voltage model for D1 in forward bias, we begin with a zero initial condition acrossC 1 and study the behavior of the circuit [Fig. 3.30(b)]. As Vin rises from zero, D1 is off until Vin > VD,on , at which point D1 begins to act as a battery and Vout = Vin − VD,on . Thus, Vout reaches a peak value of Vp − VD,on . What happens as Vin

Vp

V out

V p – V D,on V in V D,on

D1

t1 t2 V in

C1

t3

t4 t5

Vout Maximum Reverse Voltage

(a) Figure 3.30

(b)

(a) Diode-capacitor circuit, (b) input and output waveforms.

t

3.5 Applications of Diodes

75

passes its peak value? At t = t1 , we have Vin = Vp and Vout = Vp − VD,on . As Vin begins to fall, Vout must remain constant. This is because if Vout were to fall, then C 1 would need to be discharged by a current flowing from its top plate through the cathode of D1 , which is impossible.12 The diode therefore turns off after t1 . At t = t2 , Vin = Vp − VD,on = Vout , i.e., the diode sustains a zero voltage difference. At t > t2 , Vin

Example 3.24

Assuming an ideal diode model, (a) Repeat the above analysis. (b) Plot the voltage across D1 , VD1 , as a function of time.

Solution

(a) With a zero initial condition acrossC 1 , D1 turns on as Vin exceeds zero and Vout = Vin . After t = t1 , Vin falls below Vout , turning D1 off. Figure 3.31(a) shows the input and output waveforms.

V out

t1

t

V in (a) t1 t V D1 –2 V p (b) Figure 3.31 (a) Input and output waveforms of the circuit in Fig. 3.30 with an ideal diode, (b) voltage across the diode.

12

The water pipe analogy in Fig. 3.3(c) proves useful here.

76

Chapter 3 Diode Models and Circuits (b) The voltage across the diode is VD1 = Vin − Vout . Using the plots in Fig. 3.31(a), we readily arrive at the waveform in Fig. 3.31(b). Interestingly, VD1 is similar to Vin but with the average value shifted from zero to −Vp . We will exploit this result in the design of voltage doublers (Section 3.5.4).

Exercise

Repeat the above example if the terminals of the diode are swapped.

The circuit of Fig. 3.30(a) achieves the properties required of an “ac-dc converter,” generating a constant output equal to the peak value of the input sinusoid.13 But how is the value of C1 chosen? To answer this question, we consider a more realistic application where this circuit must provide a current to a load. Example 3.25

A laptop computer consumes an average power of 25 W with a supply voltage of 3.3 V. Determine the average current drawn from the batteries or the adaptor.

Solution

Since P = V · I, we have I ≈ 7.58 A. If the laptop is modeled by a resistor, RL , then RL = V/I = 0.436 .

Exercise

What power dissipation does a 1- load represent for such a supply voltage?

As suggested by the above example, the load can be represented by a simple resistor in some cases [Fig. 3.32(a)]. We must therefore repeat our analysis with RL present. From the waveforms in Fig. 3.32(b), we recognize that Vout behaves as before until t = t1 , still exhibiting a value of Vin − VD,on = Vp − VD,on if the diode voltage is assumed relatively constant. However, as Vin begins to fall after t = t1 , so does Vout because RL provides a discharge path for C 1 . Of course, since changes in Vout are undesirable, C 1 must be so large that the current drawn by RL does not reduce Vout significantly. With such a choice of C 1 , Vout falls slowly and D1 remains reverse biased.

V p – V D,on

Vp

V out

VR

V in D1 V in

C1

RL

Vout

(a) Figure 3.32 13

t3 t2

t1

(b)

(a) Rectifier driving a resistive load, (b) input and output waveforms.

This circuit is also called a “peak detector.”

t

3.5 Applications of Diodes

77

The output voltage continues to decrease while Vin goes through a negative excursion and returns to positive values. At some point, t = t2 , Vin and Vout become equal and slightly later, at t = t3 , Vin exceeds Vout by VD,on , thereby turning D1 on and forcing Vout = Vin − VD,on . Hereafter, the circuit behaves as in the first cycle. The resulting variation in Vout is called the “ripple.” Also, C 1 is called the “smoothing” or “filter” capacitor. Example 3.26

Sketch the output waveform of Fig. 3.32 as C 1 varies from very large values to very small values.

Solution

If C 1 is very large, the current drawn by RL when D1 is off creates only a small change in Vout . Conversely, if C 1 is very small, the circuit approaches that in Fig. 3.28, exhibiting large variations in Vout . Figure 3.33 illustrates several cases. V in

Large C1 V out

Small C1 t

Very Small C 1

Figure 3.33

Exercise

Output waveform of rectifier for different values of smoothing capacitor.

Repeat the above example for different values of RL with C 1 constant.

Ripple Amplitude* In typical applications, the (peak-to-peak) amplitude of the ripple, VR , in Fig. 3.32(b) must remain below 5 to 10% of the input peak voltage. If the maximum current drawn by the load is known, the value of C1 is chosen large enough to yield an acceptable ripple. To this end, we must compute VR analytically (Fig. 3.34). Since Vout = Vp − VD,on at t = t1 , the discharge of C1 through RL can be expressed as: Vout (t) = (Vp − VD,on ) exp

−t 0 ≤ t ≤ t3 , RLC1

(3.75)

where we have chosen t1 = 0 for simplicity. To ensure a small ripple, RLC1 must be much greater than t3 − t1 ; thus, noting that exp(− ) ≈ 1 − for 1, Vout (t) ≈ (Vp − VD,on ) 1 −

≈ (Vp − VD,on ) −

∗

This section can be skipped in a first reading.

t RLC1

Vp − VD,on t · . RL C1

(3.76)

(3.77)

78

Chapter 3 Diode Models and Circuits V p – V D,on

Vp

V out

VR

V in D1 V in

C1

RL

(a) Figure 3.34

t 3t 4 t2

t1

Vout

t

(b)

Ripple at output of a rectifier.

The first term on the right-hand side represents the initial condition across C1 and the second term, a falling ramp—as if a constant current equal to (Vp − VD,on )/RL discharges C1 .14 This result should not come as a surprise because the nearly constant voltage across RL results in a relatively constant current equal to (Vp − VD,on )/RL . The peak-to-peak amplitude of the ripple is equal to the amount of discharge at t = t3 . Since t4 − t3 is equal to the input period, Tin , we write t3 − t1 = Tin − T, where T(= t4 − t3 ) denotes the time during which D1 is on. Thus, VR =

Vp − VD,on Tin − T . RL C1

(3.78)

Recognizing that if C1 discharges by a small amount, then the diode turns on for only a brief period, we can assume T Tin and hence VR ≈ ≈

Vp − VD,on Tin · RL C1

(3.79)

Vp − VD,on , RLC1 fin

(3.80)

−1 where fin = Tin .

Example 3.27

A transformer converts the 110-V, 60-Hz line voltage to a peak-to-peak swing of 9 V. A half-wave rectifier follows the transformer to supply the power to the laptop computer of Example 3.25. Determine the minimum value of the filter capacitor that maintains the ripple below 0.1 V. Assume VD,on = 0.8 V.

Solution

We have Vp = 4.5 V, RL = 0.436 , and Tin = 16.7 ms. Thus, C1 =

Vp − VD,on Tin · VR RL

= 1.417 F. 14

Recall that I = CdV/dt and hence dV = (I/C )dt.

(3.81) (3.82)

3.5 Applications of Diodes

79

This is a very large value. The designer must trade the ripple amplitude with the size, weight, and cost of the capacitor. In fact, limitations on size, weight, and cost of the adaptor may dictate a much greater ripple, e.g., 0.5 V, thereby demanding that the circuit following the rectifier tolerate such a large, periodic variation. Exercise

Repeat the above example for 220-V, 50-Hz line voltage, assuming the transformer still produces a peak-to-peak swing of 9 V. Which mains frequency gives a more desirable choice of C1 ?

In many cases, the current drawn by the load is known. Repeating the above analysis with the load represented by a constant current source or simply viewing (Vp − VD,on )/RL in Eq. (3.80) as the load current, IL , we can write VR =

IL . C1 fin

(3.83)

Diode Peak Current∗ We noted in Fig. 3.30(b) that the diode must exhibit a reverse breakdown voltage of at least 2 Vp . Another important parameter of the diode is the maximum forward bias current that it must tolerate. For a given junction doping profile and geometry, if the current exceeds a certain limit, the power dissipated in the diode (= VD ID ) may raise the junction temperature so much as to damage the device. D1 V in

V in C1

RL

V out

t1

Figure 3.35

Vp

Vout

Vp – VR t

Rectifier circuit for calculation of ID .

We recognize from Fig. 3.35, that the diode current in forward bias consists of two components: (1) the transient current drawn byC1 ,C1 dVout /dt, and (2) the current supplied to RL , approximately equal to (Vp − VD,on )/RL . The peak diode current therefore occurs when the first component reaches a maximum, i.e., at the point D1 turns on because the slope of the output waveform is maximum. Assuming VD,on Vp for simplicity, we note that the point at which D1 turns on is given by Vin (t1 ) = Vp − VR . Thus, for Vin (t) = Vp sin ωin t, Vp sin ωin t1 = Vp − VR ,

(3.84)

and hence sin ωin t1 = 1 −

∗

This section can be skipped in a first reading.

VR . Vp

(3.85)

80

Chapter 3 Diode Models and Circuits With VD,on neglected, we also have Vout (t) ≈ Vin (t), obtaining the diode current as ID1 (t) = C1

dV out Vp + dt RL

= C1 ωin Vp cos ωin t +

(3.86) Vp . RL

(3.87)

This current reaches a peak at t = t1 : I p = C1 ωin Vp cos ωin t1 +

Vp , RL

(3.88)

which, from (3.85), reduces to I p = C1 ωin Vp

VR 2 Vp 1− 1− + Vp RL

= C1 ωin Vp

2VR V2 Vp − R2 + . Vp Vp RL

Since VR Vp , we neglect the second term under the square root: 2VR Vp I p ≈ C1 ωin Vp + Vp RL Vp 2VR ≈ RLC1 ωin +1 . RL Vp

(3.89)

(3.90)

(3.91)

(3.92)

Example 3.28

Determine the peak diode current in Example 3.27 assuming VD,on ≈ 0 andC1 = 1.417 F.

Solution

We have Vp = 4.5 V, RL = 0.436 , ωin = 2π (60 Hz), and VR = 0.1 V. Thus, I p = 517 A.

(3.93)

This value is extremely large. Note that the current drawn by C1 is much greater than that flowing through RL . Exercise

Repeat the above example if C1 = 1000 μF.

Full-Wave Rectifier The half-wave rectifier studied above blocks the negative half cycles of the input, allowing the filter capacitor to be discharged by the load for almost the entire period. The circuit therefore suffers from a large ripple in the presence of a heavy load (a high current). It is possible to reduce the ripple voltage by a factor of two through a simple modification. Illustrated in Fig. 3.36(a), the idea is to pass both positive and negative

3.5 Applications of Diodes

81

Vout

y (t )

Vout

t V in

x (t ) t

t

(a) Figure 3.36

t

(b)

(a) Input and output waveforms and (b) input/output characteristic of a full-wave

rectifier.

half cycles to the output, but with the negative half cycles inverted (i.e., multiplied by −1). We first implement a circuit that performs this function [called a “full-wave rectifier” (FWR)] and next prove that it indeed exhibits a smaller ripple. We begin with the assumption that the diodes are ideal to simplify the task of circuit synthesis. Figure 3.36(b) depicts the desired input/output characteristic of the full-wave rectifier. Consider the two half-wave rectifiers shown in Fig. 3.37(a), where one blocks negative half cycles and the other, positive half cycles. Can we combine these circuits to realize a full-wave rectifier? We may attempt the circuit in Fig. 3.37(b), but, unfortunately, the output contains both positive and negative half cycles, i.e., no rectification is performed because the negative half cycles are not inverted. Thus, the problem is reduced to that illustrated in Fig. 3.37(c): we must first design a half-wave rectifier that inverts. Shown in Fig. 3.37(d) is such a topology, which can also be redrawn as in Fig. 3.37(e) for simplicity. Note the polarity of Vout in the two diagrams. Here, if Vin < 0, both D2 and D1 are on and Vout = −Vin . Conversely, if Vin > 0, both diodes are off, yielding a zero current through RL and hence Vout = 0. In analogy with this circuit, we also compose that in Fig. 3.37(f), which simply blocks the negative input half cycles; i.e., Vout = 0 for Vin < 0 and Vout = Vin for Vin > 0.

D1

D2

RL

RL

RL

(a)

(b) D2

D3

D2 RL

?

RL

Vin D1

(c)

(d)

Vout

Vin

RL D1

Vout

Vin

RL

Vout

D4

(e)

(f)

Figure 3.37 (a) Rectification of each half cycle, (b) no rectification, (c) rectification and inversion, (d) realization of (c), (e) path for negative half cycles, (f) path for positive half cycles.

82

Chapter 3 Diode Models and Circuits D2 RL

Vin

Vin

Vout

Vout RL

D1

D4 (a)

D2

D3

(b)

D3

Vin

D3

D2 Vin

D4

D4

D1

(c)

D1

(d)

Figure 3.38 (a) Full-wave rectifier, (b) simplified diagram, (c) current path for negative input, (d) current path for positive input.

With the foregoing developments, we can now combine the topologies of Figs. 3.37(d) and (f) to form a full-wave rectifier. Depicted in Fig. 3.38(a), the resulting circuit passes the negative half cycles through D1 and D2 with a sign reversal [as in Fig. 3.37(d)] and the positive half cycles through D3 and D4 with no sign reversal [as in Fig. 3.37(f)]. This configuration is usually drawn as in Fig. 3.38(b)and called a “bridge rectifier.” Let us summarize our thoughts with the aid of the circuit shown in Fig. 3.38(b). If Vin <0, D2 and D1 are on and D3 and D4 are off, reducing the circuit to that shown in Fig. 3.38(c) and yielding Vout = −Vin . On the other hand, if Vin > 0, the bridge is simplified as shown in Fig. 3.38(d), and Vout = Vin . How do these results change if the diodes are not ideal? Figures 3.38(c) and (d) reveal that the circuit introduces two forward-biased diodes in series with RL , yielding Vout = −Vin − 2VD,on for Vin < 0. By contrast, the half-wave rectifier in Fig. 3.28 produces Vout = Vin − VD,on . The drop of 2VD,on may pose difficulty if Vp is relatively small and the output voltage must be close to Vp .

Example 3.29

Assuming a constant-voltage model for the diodes, plot the input/output characteristic of a full-wave rectifier.

Solution

The output remains equal to zero for |Vin | < 2VD,on and “tracks” the input for |Vin | > VD,on with a slope of unity. Figure 3.39 plots the result.

Exercise

What is the slope of the characteristic for |Vin | > 2VD,on ?

We now redraw the bridge once more and add the smoothing capacitor to arrive at the complete design [Fig. 3.40(a)]. Since the capacitor discharge occurs for about half of

3.5 Applications of Diodes

83

Vout Vout

–2 V D,on +2V D,on

V in

t

t Figure 3.39

Input/output characteristic of full-wave rectifier with nonideal diodes.

the input cycle, the ripple is approximately equal to half of that in Eq. (3.80): VR ≈

1 Vp − 2VD,on · , 2 RLC1 fin

(3.94)

where the numerator reflects the drop of 2VD,on due to the bridge. In addition to a lower ripple, the full-wave rectifier offers another important advantage: the maximum reverse bias voltage across each diode is approximately equal to Vp rather than 2Vp . As illustrated in Fig. 3.40(b), when Vin is near Vp and D3 is on, the voltage across D2 , VAB , is simply equal to VD,on + Vout = Vp − VD,on . A similar argument applies to the other diodes.

D2

V in

D3

Vin

t D4

RL

D1

C1

Vout V out t

(a) A D3

D2 Vin

V D,on

B D4

D1

RL

C1

(b) Figure 3.40

(a) Ripple in full-wave rectifier, (b) equivalent circuit.

Vout

84

Chapter 3 Diode Models and Circuits Another point of contrast between half-wave and full-wave rectifiers is that the former has a common terminal between the input and output ports (node G in Fig. 3.28),whereas the latter does not. In Problem 3.40, we study the effect of shorting the input and output grounds of a full-wave rectifier and conclude that it disrupts the operation of the circuit.

Example 3.30

Plot the currents carried by each diode in a bridge rectifier as a function of time for a sinusoidal input. Assume no smoothing capacitor is connected to the output.

Solution

From Figs. 3.38(c) and (d), we have Vout = −Vin + 2VD,on for Vin < −2VD,on and Vout = Vin − 2VD,on for Vin > +2VD,on . In each half cycle, two of the diodes carry a current equal to Vout /RL and the other two remain off. Thus, the diode currents appear as shown in Fig. 3.41.

V in

t Vp – 2V D,on RL

I D1 = I D2

t I D3 = I D4 t Vp – 2V D,on RL Figure 3.41

Exercise

Currents carried by diodes in a full-wave rectifier.

Sketch the power consumed in each diode as a function of time.

The results of our study are summarized in Fig. 3.42. While using two more diodes, fullwave rectifiers exhibit a lower ripple and require only half the diode breakdown voltage, well justifying their use in adaptors and chargers.15

15

The four diodes are typically manufactured in a single package having four terminals.

3.5 Applications of Diodes D1 V in

C1

RL

D2

D3

D4

D1

85

Vin

V p – V D,on

RL

C1

Vp – 2VD,on

V out

Vout V in

V in t

Reverse Bias

t

2 Vp

Reverse Bias

(a)

Figure 3.42

Vp

(b)

Summary of rectifier circuits.

Example 3.31

Design a full-wave rectifier to deliver an average power of 2 W to a cellphone with a voltage of 3.6 V and a ripple of 0.2 V.

Solution

We begin with the required input swing. Since the output voltage is approximately equal to Vp − 2VD,on , we have Vin, p = 3.6 V + 2VD,on ≈ 5.2 V.

(3.95) (3.96)

Thus, the transformer preceding the rectifier must step the line voltage (110 Vrms or 220 Vrms ) down to a peak value of 5.2 V. Next, we determine the minimum value of the smoothing capacitor that ensures VR ≤ 0.2 V. Rewriting Eq. (3.83) for a full-wave rectifier gives VR = =

IL 2C1 fin

(3.97)

2W 1 . · 3.6 V 2C1 fin

(3.98)

For VR = 0.2 V and fin = 60 Hz, C1 = 23,000 μF.

(3.99)

The diodes must withstand a reverse bias voltage of 5.2 V. Exercise

If cost and size limitations impose a maximum value of 1000 μF on the smoothing capacitor, what is the maximum allowable power drain in the above example?

86

Chapter 3 Diode Models and Circuits

Example 3.32

A radio frequency signal received and amplified by a cellphone exhibits a peak swing of 10 mV. We wish to generate a dc voltage representing the signal amplitude [Eq. (3.8)]. Is it possible to use the half-wave or full-wave rectifiers studied above?

Solution

No, it is not. Owing to its small amplitude, the signal cannot turn actual diodes on and off, resulting in a zero output. For such signal levels, “precision rectification” is necessary, a subject studied in Chapter 8.

Exercise

What if a constant voltage of 0.8 V is added to the desired signal?

3.5.2 Voltage Regulation ∗ The adaptor circuit studied above generally proves inadequate. Due to the significant variation of the line voltage, the peak amplitude produced by the transformer and hence the dc output vary considerably, possibly exceeding the maximum level that can be tolerated by the load (e.g., a cellphone). Furthermore, the ripple may become seriously objectionable in many applications. For example, if the adaptor supplies power to a stereo, the 120-Hz ripple can be heard from the speakers. Moreover, the finite output impedance of the transformer leads to changes in Vout if the current drawn by the load varies. For these reasons, the circuit of Fig. 3.40(a) is often followed by a “voltage regulator” so as to provide a constant output. We have already encountered a voltage regulator without calling it such: the circuit studied in Example 3.17 provides a voltage of 2.4 V, incurring only an 11-mV change in the output for a 100-mV variation in the input. We may therefore arrive at the circuit shown in Fig. 3.43 as a more versatile adaptor having a nominal output of 3VD,on ≈ 2.4 V. Unfortunately, as studied in Example 3.22, the output voltage varies with the load current. Diode Bridge R1 Vin C1

Figure 3.43

Load

Voltage regulator block diagram.

Figure 3.44(a) shows another regulator circuit employing a Zener diode. Operating in the reverse breakdown region, D1 exhibits a small-signal resistance, rD , in the range of 1 to 10 , thus providing a relatively constant output despite input variations if rD R1 .

∗

This section can be skipped in a first reading.

3.5 Applications of Diodes V in

R1

R1

v in

Vout

v out rd

D1

(a) Figure 3.44

87

(b)

(a) Regulator using a Zener diode, (b) small-signal equivalent of (a).

This can be seen from the small-signal model of Fig. 3.44(b): vout =

rD vin . r D + R1

(3.100)

For example, if rD = 5 and R1 = 1 k, then changes in Vin are attenuated by approximately a factor of 200 as they appear in Vout . The Zener regulator nonetheless has the same drawback as the circuit of Fig. 3.43, namely, poor stability if the load current varies significantly. Our brief study of regulators thus far reveals two important aspects of their design: the stability of the output with respect to input variations, and the stability of the output with respect to load current variations. The former is quantified by “line regulation,” defined as Vout /Vin , and the latter by “load regulation,” defined as Vout /IL .

Example 3.33

In the circuit of Fig. 3.45(a), Vin has a nominal value of 5 V, R1 = 100 , and D2 has a reverse breakdown of 2.7 V and a small-signal resistance of 5 . Assuming VD,on ≈ 0.8 V for D1 , determine the line and load regulation of the circuit.

V in

R1

Vout D1

VD,on

D2

VDz

v in

Solution

v out r d1

(a) Figure 3.45

R1

v in

iL

R1

Constant

r d1

r d2

r d2

(b)

(c)

v out

Circuit using two diodes, (b) small-signal equivalent, (c) load regulation.

We first determine the bias current of D1 and hence its small-signal resistance: ID1 =

Vin − VD,on − VD2 R1

= 15 mA.

(3.101) (3.102)

88

Chapter 3 Diode Models and Circuits Thus, VT ID1

(3.103)

= 1.73 .

(3.104)

rD1 =

From the small-signal model of Fig. 3.44(b), we compute the line regulation as vout rD1 + rD2 = vin rD1 + rD2 + R1

(3.105)

= 0.063.

(3.106)

For load regulation, we assume the input is constant and study the effect of load current variations. Using the small-signal circuit shown in Fig. 3.45(c) (where vin = 0 to represent a constant input), we have

That is,

vout = −i L . (rD1 + rD2 )||R1

(3.107)

vout i = (rD1 + rD2 )||R1 L

(3.108)

= 6.31 .

(3.109)

This value indicates that a 1-mA change in the load current results in a 6.31-mV change in the output voltage. Exercise

Repeat the above example for R1 = 50 and compare the results.

Figure 3.46 summarizes the results of our study in this section. D1 Vin

C1

Figure 3.46

Load

Vin

Vin Load

Load

Summary of regulators.

3.5.3 Limiting Circuits Consider the signal received by a cellphone as the user comes closer to a base station (Fig. 3.47). As the distance decreases from kilometers to hundreds of meters, the signal level may become large enough to “saturate” the circuits as it travels through the receiver chain. It is therefore desirable to “limit” the signal amplitude at a suitable point in the receiver.

3.5 Applications of Diodes Base Station

Receiver

Base Station

Receiver

(a)

Figure 3.47

89

(b)

Signals received (a) far from or (b) near a base station.

How should a limiting circuit behave? For small input levels, the circuit must simply pass the input to the output, e.g., Vout = Vin , and as the input level exceeds a “threshold” or “limit,” the output must remain constant. This behavior must hold for both positive and negative inputs, translating to the input/output characteristic shown in Fig. 3.48(a). As illustrated in Fig. 3.48(b), a signal applied to the input emerges at the output with its peak values “clipped” at ±VL . We now implement a circuit that exhibits the above behavior. The nonlinear input/ output characteristic suggests that one or more diodes must turn on or off as Vin approaches ±VL . In fact, we have already seen simple examples in Figs. 3.11(b)and (c), where the positive half cycles of the input are clipped at 0 V and +1 V, respectively. We reexamine the former assuming a more realistic diode, e.g., the constant-voltage model. As illustrated in Fig. 3.49(a), Vout is equal to Vin for Vin

Vout

Vout + VL – VL

– VL + VL

(a) Figure 3.48

V in

Vout – VL

t

+ VL

V in

+ VL

– VL

(b)

(a) Input/output characteristic of a limiting circuit, (b) response to a sinusoid.

t

90

Chapter 3 Diode Models and Circuits Vout

R1 V in

V D,on D1

Vout

V D,on

(a)

V D,on

Vout V in

t

t

Vout R1

V D,on + V B1 D1

V in

VB1

V D,on + V B1

Vout

(b)

V D,on + V B1

Vout V in

t

t

(a) Simple limiter, (b) limiter with level shift.

Figure 3.49

Vout

R1 V in

D1

Vout

– V D,on

Vout

– V D,on

V in

t

t (a)

Vout

R1 V in

D1

D2

Vout

– V D,on

Vout

+ V D,on + V D,on – V D,on

t (b) Figure 3.50

(a) Negative-cycle limiter, (b) limiter for both half cycles.

V in

t

3.5 Applications of Diodes Vout

R1 D1

V in

91

VB1

– V D,on – V B2

D2

V D,on + V B1

Vout

VB2

Vout V D,on + V B1

V in

t

– V D,on – V B2

t

Figure 3.51

General limiter and its characteristic.

Example 3.34

A signal must be limited at ±100 mV. Assuming VD,on = 800 mV, design the required limiting circuit.

Solution

Figure 3.52(a) illustrates how the voltage sources must shift the break points. Since the positive limiting point must shift to the left, the voltage source in series with D1 must be negative and equal to 700 mV. Similarly, the source in series with D2 must be positive and equal to 700 mV. Figure 3.52(b) shows the result.

Vout

R1

+ V D,on – 100 mV

V in + V D,on +100 mV (a)

Figure 3.52

Exercise

D1

D2

Vout

V in 700 mV (b)

(a) Example of a limiting circuit, (b) input/output characteristic.

Repeat the above example if the positive values of the signal must be limited at +200 mV and the negative values at −1.1 V.

Before concluding this section, we make two observations. First, the circuits studied above actually display a nonzero slope in the limiting region (Fig. 3.53). This is because, as Vin increases, so does the current through the diode that is forward biased and hence the diode voltage.16 Nonetheless, the 60-mV/decade rule expressed by Eq. (2.109) implies that this effect is typically negligible. Second, we have thus far assumed Vout = Vin for −VL < Vin < +VL , but it is possible to realize a non-unity slope in the region: Vout = αVin .

16

Recall that VD = VT ln (ID /IS ).

92

Chapter 3 Diode Models and Circuits Vout

V in

Figure 3.53

Effect of nonideal diodes on limiting characteristic.

3.5.4 Voltage Doublers ∗ Electronic systems typically employ a “global” supply voltage, e.g., 3 V, requiring that the discrete and integrated circuits operate with such a value. However, the design of some circuits in the system is greatly simplified if they run from a higher supply voltage, e.g., 6 V. “Voltage doublers” may serve this purpose.17 Before studying doublers, it is helpful to review some basic properties of capacitors. First, to charge one plate of a capacitor to +Q , the other plate must be charged to −Q . Thus, in the circuit of Fig. 3.54(a), the voltage across C1 cannot change even if Vin changes because the right plate of C1 cannot receive or release charge (Q = CV). Since VC 1 remains constant, an input change Vin appears directly at the output. This is an important observation. V C1

ΔV in

V in

C1

Vout

ΔV in

V in

(a) Figure 3.54

C1

C2

Vout

(b)

(a) Voltage change at one plate of a capacitor, (b) voltage division.

Second, a capacitive voltage divider such as that in Fig. 3.54(b) operates as follows. If Vin becomes more positive, the left plate of C1 receives positive charge from Vin , thus requiring that the right plate absorb negative charge of the same magnitude from the top plate of C2 . Having lost negative charge, the top plate of C2 equivalently holds more positive charge, and hence the bottom plate absorbs negative charge from ground. Note that all four plates receive or release equal amounts of charge because C1 and C2 are in series. To determine the change in Vout , Vout , resulting from Vin , we write the change in the charge on C2 as Q 2 = C2 · Vout , which also holds for C1 : Q 2 = Q 1 . Thus, the voltage change across C 1 is equal to C2 · Vout /C 1 . Adding these two voltage changes and equating the result to Vin , we have Vin =

∗

C2 Vout + Vout . C1

This section can be skipped in a first reading. Voltage doublers are an example of “dc-dc converters.”

17

(3.110)

3.5 Applications of Diodes

93

That is,

Vout =

C1 Vin . C1 + C 2

(3.111)

This result is similar to the voltage division expression for resistive dividers, except that C1 (rather than C2 ) appears in the numerator. Interestingly, the circuit of Fig. 3.54(a) is a special case of the capacitive divider with C2 = 0 and hence Vout = Vin . As our first step toward realizing a voltage doubler, recall the result illustrated in Fig. 3.31: the voltage across the diode in the peak detector exhibits an average value of −Vp and, more importantly, a peak value of −2Vp (with respect to zero). For further investigation, we redraw the circuit as shown in Fig. 3.55, where the diode and the capacitors are exchanged and the voltage across D1 is labeled Vout . While Vout in this circuit behaves exactly the same as VD1 in Fig. 3.30(a), we derive the output waveform from a different perspective so as to gain more insight.

t1 V out

V in V in

C1

D1

Vout

– Vp t1

V in V in

(a) Figure 3.55

t

t – 2V p – Vp (b)

(a) Capacitor-diode circuit and (b) its waveforms.

Assuming an ideal diode and a zero initial condition across C1 , we note that as Vin exceeds zero, the input tends to place positive charge on the left plate of C1 and hence draw negative charge from D1 . Consequently, D1 turns on, forcing Vout = 0.18 As the input rises toward Vp , the voltage acrossC1 remains equal to Vin because its right plate is “pinned” at zero by D1 . After t = t1 , Vin begins to fall and tends to discharge C 1 , i.e., draw positive charge from the left plate and hence from D1 . The diode therefore turns off, reducing the circuit to that in Fig. 3.54(a). From this time, the output simply tracks the changes in the input while C 1 sustains a constant voltage equal to Vp . In particular, as Vin varies from +Vp to −Vp , the output goes from zero to −2Vp , and the cycle repeats indefinitely. The output waveform is thus identical to that obtained in Fig. 3.31(b).

18 If we assume D1 does not turn on, then the circuit resembles that in Fig. 3.54(a), requiring that Vout rise and D1 turn on.

94

Chapter 3 Diode Models and Circuits

Example 3.35

Plot the output waveform of the circuit shown in Fig. 3.56 if the initial condition across C1 is zero.

+2 V p

V out

V in

t

C1

D1

Vout

V in t2

t4 t

t1

V in

Vp

V in V in (a) Figure 3.56

(b)

Capacitor-diode circuit and (b) its waveforms.

Solution

As Vin rises from zero, attempting to place positive charge on the left plate of C1 and hence draw negative charge from D1 , the diode turns off. As a result,C1 directly transfers the input change to the output for the entire positive half cycle. After t = t1 , the input tends to push negative charge into C1 , turning D1 on and forcing Vout = 0. Thus, the voltage across C1 remains equal to Vin until t = t2 , at which point the direction of the current through C1 and D1 must change, turning D1 off. Now, C1 carries a voltage equal to Vp and transfers the input change to the output; i.e., the output tracks the input but with a level shift of +Vp , reaching a peak value of +2Vp .

Exercise

Repeat the above example if the right plate of C1 is 1 V more positive than its left plate at t = 0.

We have thus far developed circuits that generate a periodic output with a peak value of −2Vp or +2Vp for an input sinusoid varying between −Vp and +Vp . We surmise that if these circuits are followed by a peak detector [e.g., Fig. 3.30(a)], then a constant output equal to −2Vp or +2Vp may be produced. Figure 3.57 exemplifies this concept, combining the circuit of Fig. 3.56 with the peak detector of Fig. 3.30(a). Of course, since the peak detector “loads” the first stage when D2 turns on, we must still analyze this circuit carefully and determine whether it indeed operates as a voltage doubler.

3.5 Applications of Diodes

C1 V in

D2

X D1

95

Vp

V out C2

Vout

2

Vp t V in

t4 t5

t1 V in

t2 t3

C1

t

V in

C1 C2

C2

V in

C1

V in

C1 C 2 Vp

V in

C1 C2

C2

Figure 3.57

Voltage doubler circuit and its waveforms.

We assume ideal diodes, zero initial conditions across C1 and C2 , and C1 = C2 . In this case, the analysis is simplified if we begin with a negative cycle. As Vin falls below zero, D1 turns on, pinning node X to zero.19 Thus, for t < t1 , D2 remains off and Vout = 0. At t = t1 , the voltage across C1 reaches −Vp . For t > t1 , the input begins to rise and tends to deposit positive charge on the left plate of C1 , turning D1 off and yielding the circuit shown in Fig. 3.57. How does D2 behave in this regime? Since Vin is now rising, we postulate that VX also tends to increase (from zero), turning D2 on. (If D2 remains off, then C1 simply transfers the change in Vin to node X, raising VX and hence turning D2 on.) As a result, the circuit reduces to a simple capacitive divider that follows Eq. (3.111): Vout =

1 Vin , 2

(3.112)

because C1 = C2 . In other words, VX and Vout begin from zero, remain equal, and vary sinusoidally but with an amplitude equal to Vp /2. Thus, from t1 to t2 , a change of 2Vp in Vin appears as a change equal to Vp in VX and Vout . Note at t = t2 , the voltage across C1 is zero because both Vin and Vout are equal to +Vp . What happens after t = t2 ? Since Vin begins to fall and tends to draw charge from C1 , D2 turns off, maintaining Vout at +Vp . The reader may wonder if something is wrong 19

As always, the reader is encouraged to assume otherwise (i.e., D1 remains off) and arrive at a conflicting result.

96

Chapter 3 Diode Models and Circuits here; our objective was to generate an output equal to 2Vp rather than Vp . But again, patience is a virtue and we must continue the transient analysis. For t > t2 , both D1 and D2 are off, and each capacitor holds a constant voltage. Since the voltage across C1 is zero, VX = Vin , falling to zero at t = t3 . At this point, D1 turns on again, allowing C1 to charge to −Vp at t = t4 . As Vin begins to rise again, D1 turns off and D2 remains off because VX = 0 and Vout = +Vp . Now, with the right plate of C1 floating, VX tracks the change at the input, reaching +Vp as Vin goes from −Vp to 0. Thus, D2 turns on at t = t5 , forming a capacitive divider again. After this time, the output change is equal to half of the input change, i.e., Vout increases from +Vp to +Vp + Vp /2 as Vin goes from 0 to +Vp . The output has now reached 3Vp /2. As is evident from the foregoing analysis, the output continues to rise by Vp , Vp /2, Vp /4, etc., in each input cycle, approaching a final value of 1 1 Vout = Vp 1 + + + · · · 2 4 =

Vp 1 1− 2

= 2Vp .

(3.113)

(3.114)

(3.115)

The reader is encouraged to continue the analysis for a few more cycles and verify this trend.

Example 3.36

Sketch the current through D1 in the doubler circuit as function of time.

Solution

Using the diagram in Fig. 3.58(a), noting that D1 and C1 carry equal currents when D1 is forward biased, and writing the current as ID1 = −C1 dV in /dt, we construct the plot shown in Fig. 3.58(b).20 For 0 < t < t1 , D1 conducts and the peak current corresponds to the maximum slope of Vin , i.e., immediately after t = 0. From t = t1 to t = t3 , the diode remains off, repeating the same behavior in subsequent cycles.

Exercise

Plot the current through D2 in the above example as a function of time.

3.5.5 Diodes as Level Shifters and Switches ∗ In the design of electronic circuits, we may need to shift the average level of a signal up or down because the subsequent stage (e.g., an amplifier) may not operate properly with the present dc level. 20 ∗

As usual, ID1 denotes the current flowing from the anode to the cathode. This section can be skipped in a first reading.

3.5 Applications of Diodes

97

V in t4 t5

t1 t2 t3

C1

V in

t

V in

C1 C2

C2

V in

V in

C1

C1 C 2 Vp

V in

C1 C2

C2

I D1 t4

t1 t2 t3

Figure 3.58

t

Diode current in a voltage doubler.

Sustaining a relatively constant voltage in forward bias, a diode can be viewed as a battery and hence a device capable of shifting the signal level. In our first attempt, we consider the circuit shown in Fig. 3.59(a) as a candidate for shifting the level down by VD,on . However, the diode current remains unknown and dependent on the next stage. To alleviate this issue we modify the circuit as depicted in Fig. 3.59(b), where I1 draws a constant current, establishing VD,on across D1 .21 If the current pulled by the next stage is negligible (or at least constant), Vout is simply lower than Vin by a constant amount, VD,on .

Vin

D1 Vin

Vout

(a) Figure 3.59

21

D1

V D,on

Vin Vout

V D,on

Vout

I1 (b)

(a) Use of a diode for level shift, (b) practical implementation.

The diode is drawn vertically to emphasize that Vout is lower than Vin .

t

98

Chapter 3 Diode Models and Circuits

Example 3.37

Design a circuit that shifts up the dc level of a signal by 2VD,on .

Solution

To shift the level up, we apply the input to the cathode. Also, to obtain a shift of 2VD,on , we place two diodes in series. Figure 3.60 shows the result. VCC I1

Vout Vout

2 V D,on

Vin

2 V D,on Vin t Figure 3.60 Exercise

Positive voltage shift by two diodes.

What happens if I1 is extremely small?

The level shift circuit of Fig. 3.59(b) can be transformed to an electronic switch. For example, many applications employ the topology shown in Fig. 3.61(a) to “sample” Vin across C1 and “freeze” the value when S 1 turns off. Let us replace S 1 with the level shift circuit and allow I1 to be turned on and off [Fig. 3.61(b)]. If I1 is on, Vout tracks Vin except for a level shift equal to VD,on . When I1 turns off, so does D1 , evidently disconnecting C1 from the input and freezing the voltage across C1 . Vin

V in

Vin

Vout

CK

Vin D1

Vout

C1 CK

I1

D1

Vout I1

C1

Vout

C1

D 1 turns on. D 1 turns off.

(a)

(b)

(c)

t1 t2

VCC CK

I1

Vin

Vout

Vin

Vout

C1 CK

C1

I1

(d)

(e)

Figure 3.61 (a) Switched-capacitor circuit, (b) realization of (a) using a diode as a switch, (c) problem of diode conduction, (d) more complete circuit, (e) equivalent circuit when I1 and I2 are off.

t

Problems

99

We used the term “evidently” in the last sentence because the circuit’s true behavior somewhat differs from the above description. The assumption that D1 turns off holds only ifC1 draws no current from D1 , i.e., only if Vin − Vout remains less than VD,on . Now consider the case illustrated in Fig. 3.61(c), where I1 turns off at t = t1 , allowing C1 to store a value equal to Vin1 − VD,on . As the input waveform completes a negative excursion and exceeds Vin1 at t = t2 , the diode is forward-biased again, charging C1 with the input (in a manner similar to a peak detector). That is, even though I1 is off, D1 turns on for part of the cycle. To resolve this issue, the circuit is modified as shown in Fig. 3.61(d), where D2 is inserted between D1 andC1 , and I2 provides a bias current for D2 . With both I1 and I2 on, the diodes operate in forward bias, VX = Vin − VD1 , and Vout = VX + VD2 = Vin if VD1 = VD2 . Thus, Vout tracks Vin with no level shift. When I1 and I2 turn off, the circuit reduces to that in Fig. 3.61(e), where the back-to-back diodes fail to conduct for any value of Vin − Vout , thereby isolating C1 from the input. In other words, the two diodes and the two current sources form an electronic switch.

Example 3.38

Recall from Chapter 2 that diodes exhibit a junction capacitance in reverse bias. Study the effect of this capacitance on the operation of the above circuit.

Solution

Figure 3.62 shows the equivalent circuit for the case where the diodes are off, suggesting that the conduction of the input through the junction capacitances disturbs the output. Specifically, invoking the capacitive divider of Fig. 3.54(b) and assuming Vin

Vout C j1

Figure 3.62

C j2

C1

Feedthrough in the diode switch.

Cj1 = Cj2 = Cj , we have Vout =

C j /2 Vin . C j /2 + C1

(3.116)

To ensure this “feedthrough” is small, C1 must be sufficiently large. Exercise

Calculate the change in the voltage at the left plate ofC j1 (with respect to ground) in terms of Vin .

PROBLEMS In the following problems, assume VD,on = 800 mV for the constant-voltage diode model. 3.1. For the circuit shown in Fig 3.63, plot the I/V characteristics.

IX

R1

D1

D2

Ideal Ideal VX

Figure 3.63

R2

100

Chapter 3 Diode Models and Circuits IX

3.2. If the input in Fig. 3.63 is expressed as VX = V0 sin ωt, plot the current through the circuit as a function of time. 3.3. Plot I X as a function of V X for the circuit shown in Fig. 3.64. IX VX

R1 Ideal

D1

R1 VX

R2

Ideal

VB

Ideal

Figure 3.67

R2

D2

VB

3.8. For the circuit shown in Fig. 3.68, plot I X and I R1 as a function of V X . IX

Figure 3.64

Ideal R1 D1

3.4. For the circuit shown in Fig. 3.65 plot I X as a function of V X for two different cases: VB = +1 V and VB = −1 V.

VX

D2

R2

Ideal

VB

Figure 3.68

IX VX

R1 Ideal

D1 R2

D2

VB

3.9. Plot input/output characteristics for the Fig. 3.69 using an ideal model for the diode. Assume VX = V0 sin ωt and VB = 3 V. R1

Figure 3.65

Ideal

3.5. If the input in Fig. 3.65 is expressed as VX = V0 sin ωt, plot I X as a function of time for VB = 3 V.

VX

3.6. Plot the I X as a function of V X for the circuit shown in Fig. 3.66. Assume VB > 0.

Figure 3.69

IX

R1 R2

VX Figure 3.66

D1 VB

Ideal

Ideal

R2

Vout VB = 3 V

*3.10. If the input is given by Vin = V0 cos ωt, plot the output of each circuit in Fig. 3.70 as a function of time. Assume an ideal diode model. **3.11. Plot the input/output characteristics of the circuits shown in Fig. 3.70 using an ideal model for the diodes. **3.12. Repeat Problem 3.11 with a constantvoltage diode model.

**3.13. Assuming a constant-voltage diode model, plot Vout as a function of Iin for the circuits 3.7. For the circuit shown in Fig. 3.67, plot I X as shown in Fig. 3.71. a function of V X . Assume VB > 0.

Problems R1

VB

V in

D1

R1 Vout

D1 D1

V in

VB

V in

Vout

R1

VB (a)

(b)

Vout

(c)

VB

D1 R1

V in

101

D1

R1

V in

Vout

Vout

VB

(d)

(e)

Figure 3.70

I in

Vout

D1

R1

I in

(a)

I in

VB

Vout

(b)

R1

D1

D1

R1

VB

Vout

(c)

VB

I in D1

R1

Vout

(d)

Figure 3.71

**3.14. In the circuits of Fig. 3.71, plot the current *3.17. Plot V out as a function of V X for the cirflowing through R1 as a function of Vin . cuit shown in Fig. 3.72. Assume a constantvoltage diode model. Assume a constant-voltage diode model. **3.15. Plot the V out as a function of V X in the circuit of Fig. 3.72. Assume VX = V0 sin ωt and a constant-voltage diode model.

Vx

VB

R Vout

Figure 3.72

*3.16. Plot the current flowing through R1 in the circuit of Fig. 3.72 as a function of V X . Assume a constant-voltage diode model.

3.18. For the circuits shown in Fig. 3.73, plot Vout as a function of Iin assuming a constantvoltage model for the diodes. 3.19. Plot the input/output characteristics of the circuits illustrated in Fig. 3.74 assuming a constant-voltage diode model. 3.20. Plot the current flowing through R1 and D1 as a function of V X for the circuit shown in Fig 3.74(b) assuming a constant-voltage diode model. 3.21. Plot the input/output characteristic of the circuits illustrated in Fig. 3.75 assuming a constant-voltage model.

102

Chapter 3 Diode Models and Circuits D1 I in

R1

Vout

D2

R1

I in

D1

(a)

I in

Vout

D2

R1

I in

(b)

R1

Vout

D2

D1

R1

I in

(d)

D1

Vout

D2

I in

R1

(e)

(f)

D1

D1

D2

I in

Vout

R1

D2

I in

Vout

R1 (h)

(g) Figure 3.73

R1

R D1

Vx

Vout

D1

R2

Vx

VB

Vout

VB

(a)

(b)

Figure 3.74

D1 V in

R1

D 1 VB Vout

V in

R2

Vout

R1

R2

VB (a)

(b)

D1 V in

Vout R2 (c)

Figure 3.75

R1

VB

R1

Vout

(c)

D2

D1

D2

D1

V in

D1

(d)

VB Vout R2

Vout

Problems

103

**3.22. Plot the currents flowing through R1 and **3.24. Plot the input/output characteristic of the D1 as a function of Vin for the circuits of circuits illustrated in Fig. 3.77 assuming a Fig. 3.75. Assume a constant-voltage diode constant-voltage model. model. **3.25. Plot the currents flowing through R and 1

D1 as a function of Vin for the circuits of Fig. 3.77. Assume constant-voltage diode model.

**3.23. Plot the input/output characteristic of the circuits illustrated in Fig. 3.76 assuming a constant-voltage model and VB = 2 V.

D1

R1 V in

V in

Vout D1

Vout D1

D2

VB

R1

R2

VB

R2 (a)

(b)

R1 V in D1

R2

D1 R1

V in

Vout

Vout

D2

D2

VB

VB

(c)

R2

(d)

Figure 3.76

V in

D1

R1 D2

D1 Vout

V in

R1

R2

(a) D1 V in

R1

Vout D2

Figure 3.77

D2

R2

(b) V in

D1 D2

D1 V in

R1

R1

Vout

R2

(c)

Vout

R2 (d)

D2 R2

(e)

Vout

104

Chapter 3 Diode Models and Circuits D1

V in

D1

V in

Vout R 1 = 1 kΩ

Vout R 1 = 1 kΩ D2

(a) D1

V in

(b)

R1 1 kΩ

Vout

R1

V in

Vout

1 kΩ R2

D2

(c)

2kΩ

D2

(d)

Figure 3.78

D1

D1

Vout

I in

Vout

I in

R 1 = 1 kΩ

R 1 = 1 kΩ D2

(a) D1

R1 1 kΩ

I in

(b) R1

Vout D2

1 kΩ R2

I in

(c)

Vout 2kΩ

D2

(d)

Figure 3.79

*3.26. Beginning with VD,on ≈ 800 mV for each diode, determine the change in Vout if Vin changes from +2.4 V to +2.5 V for the circuits shown in Fig. 3.78. *3.27. Beginning with VD,on ≈ 800 mV for each diode, calculate the change in Vout if Iin changes from 3 mA to 3.1 mA in the circuits of Fig. 3.79. 3.28. Assuming VX = V0 sin ωt, plot the output waveform of the circuit shown in Fig. 3.80 using a constant-voltage diode model. R Vx

Figure 3.80

D1

D3

D2

D4

Vout

3.29. Assuming VX = V0 sin ωt, plot the waveforms V C and V 0 for the circuit shown in Fig. 3.81. Assume V0 = 5 V and VB = 3 V. D1 Vx

C

Vc

Vout

VB Figure 3.81

3.30. Suppose the rectifier of Fig. 3.32 drives a 100- load with a peak voltage of 3.5 V. For a 1000-μF smoothing capacitor, calculate the ripple amplitude if the frequency is 60 Hz. 3.31. A 5 V charger using a half-wave rectifier is used to charge a battery, with a smoothing

Problems

105

capacitor of 100 μF with a maximum ripple of 500 mV. Compute the charging current, for a frequency of 60 Hz.

(b) Using the small-signal model of the diodes, determine the ripple amplitude across the load.

*3.32. While constructing a full-wave rectifier, a student mistakenly has swapped the terminals of D3 as depicted in Fig. 3.82. Explain what happens.

3.38. Design the limiting circuit of Fig. 3.51 for a negative threshold of −1.9 V and a positive threshold of +2.2 V. Assume the input peak voltage is equal to 5 V, the maximum allowable current through each diode is 2 mA, and VD,on ≈ 800 mV.

D2 Vin D4

Vout RL

D3

D1

Figure 3.82

3.33. Plot the voltage across each diode in Fig. 3.38(b) as a function of time if Vin = V0 cos ωt. Assume a constant-voltage diode model and VD > VD,on .

*3.39. In the limiting circuit of Fig. 3.51, plot the currents flowing through D1 and D2 as a function of time if the input is given by V0 cos ωt and V0 > VD,on + VB1 and −V0 > −VD,on − VB2 . 3.40. We wish to design a circuit that exhibits the input/output characteristic shown in Fig. 3.83. Using 1-k resistors, ideal diodes, and other components, construct the circuit.

3.34. A full-wave rectifier is driven by a sinusoidal input Vin = V0 cos ωt, where V0 = 3 V and ω = 2π (60 Hz). Assuming VD,on = 800 mV, determine the ripple amplitude with a 1000-μF smoothing capacitor and a load resistance of 30 . 3.35. Suppose the negative terminals of Vin and Vout in Fig. 3.38(b) are shorted together. Plot the input-output characteristic assuming an ideal diode model and explaining why the circuit does not operate as a full-wave rectifier. 3.36. Suppose in Fig. 3.43, the diodes carry a current of 5 mA and the load, a current of 20 mA. If the load current increases to 21 mA, what is the change in the total voltage across the three diodes? Assume R1 is much greater than 3rd . 3.37. In this problem, we estimate the ripple seen by the load in Fig. 3.43 so as to appreciate the regulation provided by the diodes. For simplicity, neglect the load. Also, fin = 60 Hz, C1 = 100 μF, R1 = 1000 , and the peak voltage produced by the transformer is equal to 5 V. (a) Assuming R1 carries a relatively constant current and VD,on ≈ 800 mV, estimate the ripple amplitude across C1 .

Vout +2V

0.5

–2 V +2V

V in

–2 V 0.5 Figure 3.83

*3.41. “Wave-shaping” applications require the input/output characteristic illustrated in Fig. 3.84. Using ideal diodes and other components, construct a circuit that provides such a characteristic. (The value of resistors is not unique.) Vout +2V –4 V

0.5

–2 V +2V –2 V 0.5

Figure 3.84

+4V

V in

106

Chapter 3 Diode Models and Circuits

SPICE PROBLEMS In the following problems, assume IS = 5× 10−16 A. 3.1. The half-wave rectifier of Fig. 3.85 must deliver a current of 5 mA to R1 for a peak input level of 2 V. (a) Using hand calculations, determine the required value of R1 . (b) Verify the result by SPICE.

D1 V in

Vout R1

Figure 3.85

3.2. In the circuit of Fig. 3.86, R1 = 500 and R2 = 1 k. Use SPICE to construct the input/output characteristic for −2 V < Vin < +2 V. Also, plot the current flowing through R1 as a function of Vin .

D1

R1 D2

V in

R2

Vout

Figure 3.86

3.3. The rectifier shown in Fig. 3.87 is driven by a 60-Hz sinusoid input with a peak amplitude of 5 V. Using the transient analysis in SPICE, (a) Determine the peak-to-peak ripple at the output. (b) Determine the peak current flowing through D1 . (c) Compute the heaviest load (smallest RL ) that the circuit can drive while maintaining a ripple less than 200 mVpp . D1 V in Figure 3.87

Vout 1 μF

100 Ω

Chapter

4

Physics of Bipolar Transistors

The bipolar transistor was invented in 1945 by Shockley, Brattain, and Bardeen at Bell Laboratories, subsequently replacing vacuum tubes in electronic systems and paving the way for integrated circuits. In this chapter, we analyze the structure and operation of bipolar transistors, preparing ourselves for the study of circuits employing such devices. Following the same thought process as in Chapter 2 for pn junctions, we aim to understand the physics of the transistor, derive equations that represent its I/V characteristics, and develop an equivalent model that can be used in circuit analysis and design. The outline below illustrates the sequence of concepts introduced in this chapter.

Voltage-Controlled Device as Amplifying Element

4.1

®

Structure of Bipolar Transistor

®

Operation of Bipolar Transistor

®

Large-Signal Model

®

Small-Signal Model

GENERAL CONSIDERATIONS In its simplest form, the bipolar transistor can be viewed as a voltage-dependent current source. We first show how such a current source can form an amplifier and hence why bipolar devices are useful and interesting. Consider the voltage-dependent current source depicted in Fig. 4.1(a), where I1 is proportional to V1 : I1 = KV 1 . Note that K has a dimension of resistance−1 . For example, with K = 0.001 −1 , an input voltage of 1 V yields an output current of 1 mA. Let us now construct the circuit shown in Fig. 4.1(b), where a voltage source Vin controls I1 and the output current flows through a load resistor RL , producing Vout . Our objective is to demonstrate that this circuit can operate as an amplifier, i.e., Vout is an amplified replica of Vin . Since V1 = Vin and Vout = −RL I1 , we have Vout = −KRL Vin .

(4.1)

107

108

Chapter 4 Physics of Bipolar Transistors V in

Vp t

V1

I1

KV1

V in

V1

I1

KV1

R L Vout

V out

K R L Vp

t

(a)

Figure 4.1

(b)

(a) Voltage-dependent current source, (b) simple amplifier.

Interestingly, if KRL > 1, then the circuit amplifies the input. The negative sign indicates that the output is an “inverted” replica of the input circuit [Fig. 4.1(b)]. The amplification factor or “voltage gain” of the circuit, AV , is defined as Vout Vin

(4.2)

= −KRL ,

(4.3)

AV =

and depends on both the characteristics of the controlled current source and the load resistor. Note that K signifies how strongly V1 controls I1 , thus directly affecting the gain.

Example 4.1

Consider the circuit shown in Fig. 4.2, where the voltage-controlled current source exhibits an “internal” resistance of rin . Determine the voltage gain of the circuit.

V in

Figure 4.2

r in

V1

I1

KV1

RL

Vout

Voltage-dependent current source with an internal resistance rin .

Solution

Since V1 is equal to Vin regardless of the value of rin , the voltage gain remains unchanged. This point proves useful in our analyses later.

Exercise

Repeat the above example if rin = ∞.

The foregoing study reveals that a voltage-controlled current source can indeed provide signal amplification. Bipolar transistors are an example of such current sources and can ideally be modeled as shown in Fig. 4.3.Note that the device contains three terminals and its output current is an exponential function of V1 . We will see in Section 4.4.4 that under certain conditions, this model can be approximated by that in Fig. 4.1(a).

4.2 Structure of Bipolar Transistor 1

I S exp

V1

V1

109

3

VT

2

Figure 4.3

Exponential voltage-dependent current source.

As three-terminal devices, bipolar transistors make the analysis of circuits more difficult. Having dealt with two-terminal components such as resistors, capacitors, inductors, and diodes in elementary circuit analysis and the previous chapters of this book, we are accustomed to a one-to-one correspondence between the current through and the voltage across each device. With three-terminal elements, on the other hand, one may consider the current and voltage between every two terminals, arriving at a complex set of equations. Fortunately, as we develop our understanding of the transistor’s operation, we discard some of these current and voltage combinations as irrelevant, thus obtaining a relatively simple model.

4.2

STRUCTURE OF BIPOLAR TRANSISTOR The bipolar transistor consists of three doped regions forming a sandwich. Shown in Fig. 4.4(a) is an example comprising of a p layer sandwiched between two n regions and called an “npn” transistor. The three terminals are called the “base,” the “emitter,” and the “collector.” As explained later, the emitter “emits” charge carriers and the collector “collects” them while the base controls the number of carriers that make this journey. The circuit symbol for the npn transistor is shown in Fig. 4.4(b). We denote the terminal voltages by VE , VB , and VC , and the voltage differences by VBE , VCB , and VCE . The transistor is labeled Q 1 here. Collector (C)

Collector

n Base

p n

Figure 4.4

VCB Base (B)

Q 1 VCE VBE

Emitter

Emitter (E)

(a)

(b)

(a) Structure and (b) circuit symbol of bipolar transistor.

We readily note from Fig. 4.4(a) that the device contains two pn junction diodes: one between the base and the emitter and another between the base and the collector. For example, if the base is more positive than the emitter, VBE > 0, then this junction is forward-biased. While this simple diagram may suggest that the device is symmetric with

110

Chapter 4 Physics of Bipolar Transistors respect to the emitter and the collector, in reality, the dimensions and doping levels of these two regions are quite different. In other words, E and C cannot be interchanged. We ˚ in modern will also see that proper operation requires a thin base region, e.g., about 100 A integrated bipolar transistors. As mentioned in the previous section, the possible combinations of voltages and currents for a three-terminal device can prove overwhelming. For the device in Fig. 4.4(a), VBE , VBC , and VCE can assume positive or negative values, leading to 23 possibilities for the terminal voltages of the transistor. Fortunately, only one of these eight combinations finds practical value and comes into our focus here. Before continuing with the bipolar transistor, it is instructive to study an interesting effect in pn junctions. Consider the reverse-biased junction depicted in Fig. 4.5(a) and recall from Chapter 2 that the depletion region sustains a strong electric field. Now suppose an electron is somehow “injected” from outside into the right side of the depletion region. What happens to this electron? Serving as a minority carrier on the p side, the electron experiences the electric field and is rapidly swept away into the n side. The ability of a reverse-biased pn junction to efficiently “collect” externally-injected electrons proves essential to the operation of the bipolar transistor. Electron injected

e n – – – – – – – – – – – – – – – – – – – – – – – – – – – –

+ + + + +

– – – – –

p + + + + + + + + + + + + + + + + + + + + + + + + + + + +

E

VR

Figure 4.5

4.3

Injection of electrons into depletion region.

OPERATION OF BIPOLAR TRANSISTOR IN ACTIVE MODE In this section, we analyze the operation of the transistor, aiming to prove that, under certain conditions, it indeed acts as a voltage-controlled current source. More specifically, we intend to show that (a) the current flow from the emitter to the collector can be viewed as a current source tied between these two terminals, and (b) this current is controlled by the voltage difference between the base and the emitter, VBE . We begin our study with the assumption that the base-emitter junction is forwardbiased (VBE > 0) and the base-collector junction is reverse-biased (VBC < 0). Under these conditions, we say the device is biased in the “forward active region” or simply in the “active mode.” For example, with the emitter connected to ground, the base voltage is set to about 0.8 V and the collector voltage to a higher value, e.g., 1 V [Fig. 4.6(a)]. The base-collector junction therefore experiences a reverse bias of 0.2 V. Let us now consider the operation of the transistor in the active mode. We may be tempted to simplify the example of Fig. 4.6(a) to the equivalent circuit shown in Fig. 4.6(b). After all, it appears that the bipolar transistor simply consists of two diodes sharing their

4.3 Operation of Bipolar Transistor in Active Mode

111

I2 D2

V CE = +1 V

V CE = +1 V

V BE = +0.8 V

V BE = +0.8 V

I1

(a)

Figure 4.6

D1 (b)

(a) Bipolar transistor with base and collector bias voltages, (b) simplistic view of bipolar

transistor.

anodes at the base terminal. This view implies that D1 carries a current and D2 does not; i.e., we should anticipate current flow from the base to the emitter but no current through the collector terminal. Were this true, the transistor would not operate as a voltage-controlled current source and would prove of little value. To understand why the transistor cannot be modeled as merely two back-to-back diodes, we must examine the flow of charge inside the device, bearing in mind that the base region is very thin. Since the base-emitter junction is forward-biased, electrons flow from the emitter to the base and holes from the base to the emitter. For proper transistor operation, the former current component must be much greater than the latter, requiring that the emitter doping level be much greater than that of the base (Chapter 2). Thus, we denote the emitter region with n+ , where the superscript emphasizes the high doping level. Figure 4.7(a) summarizes our observations thus far, indicating that the emitter

n p V BE = +0.8 V

+ h

– e

p V BE = +0.8 V

n

n

Depletion Region

V CE = +1 V

+

+ h

(a)

– e n

+

(b)

n

Depletion Region

V BE = +0.8 V

– e p + h

n

V CE = +1 V

+

(c)

(a) Flow of electrons and holes through base-emitter junction, (b) electrons approaching collector junction, (c) electrons passing through collector junction.

Figure 4.7

V CE = +1 V

112

Chapter 4 Physics of Bipolar Transistors injects a large number of electrons into the base while receiving a small number of holes from it. What happens to electrons as they enter the base? Since the base region is thin, most of the electrons reach the edge of the collector-base depletion region, beginning to experience the built-in electric field. Consequently, as illustrated in Fig. 4.5, the electrons are swept into the collector region (as in Fig. 4.5) and absorbed by the positive battery terminal. Figures 4.7(b) and (c) illustrate this effect in “slow motion.” We therefore observe that the reverse-biased collector-base junction carries a current because minority carriers are “injected” into its depletion region. Let us summarize our thoughts. In the active mode, an npn bipolar transistor carries a large number of electrons from the emitter, through the base, to the collector while drawing a small current of holes through the base terminal. We must now answer several questions. First, how do electrons travel through the base: by drift or diffusion? Second, how does the resulting current depend on the terminal voltages? Third, how large is the base current? Operating as a moderate conductor, the base region sustains but a small electric field, i.e., it allows most of the field to drop across the base-emitter depletion layer. Thus, as explained for pn junctions in Chapter 2, the drift current in the base is negligible,1 leaving diffusion as the principal mechanism for the flow of electrons injected by the emitter. In fact, two observations directly lead to the necessity of diffusion: (1) redrawing the diagram of Fig. 2.29 for the emitter-base junction [Fig. 4.8(a)], we recognize that the density of electrons at x = x1 is very high; (2) since any electron arriving at x = x2 in Fig. 4.8(b) is swept away, the density of electrons falls to zero at this point. As a result,

n

V CE

p

e V BE

Reverse Biased

x

x1

h

n

n

e

V BE

+

p n

x x2

V CE

+

Forward Biased (a)

(b)

n p

e

x x2

V CE

x1

V BE n

+

Electron Density (c)

(a) Hole and electron profiles at base-emitter junction, (b) zero electron density near collector, (c) electron profile in base.

Figure 4.8

1

This assumption simplifies the analysis here but may not hold in the general case.

4.3 Operation of Bipolar Transistor in Active Mode

113

the electron density in the base assumes the profile depicted in Fig. 4.8(c), providing a gradient for the diffusion of electrons. 4.3.1 Collector Current We now address the second question raised previously and compute the current flowing from the collector to the emitter.2 As a forward-biased diode, the base-emitter junction exhibits a high concentration of electrons at x = x1 in Fig. 4.8(c) given by Eq. (2.96): VBE NE n(x1 ) = exp −1 (4.4) V0 VT exp VT NB VBE = 2 exp −1 . VT ni

(4.5)

Here, NE and NB denote the doping levels in the emitter and the base, respectively, and we have utilized the relationship exp (V0 /VT ) = NE NB /ni2 . In this chapter, we assume VT = 26 mV. Applying the law of diffusion [Eq. (2.42)], we determine the flow of electrons into the collector as Jn = qDn

dn dx

= qDn ·

0 − n(x1 ) , WB

(4.6)

(4.7)

where WB is the width of the base region. Multipling this quantity by the emitter cross section area, AE , substituting for n(x1 ) from Eq. (4.5), and changing the sign to obtain the conventional current, we obtain AE qDn ni2 VBE IC = exp −1 . (4.8) NB WB VT In analogy with the diode current equation and assuming exp (VBE /VT ) 1, we write VBE , VT

(4.9)

AE qDn ni2 . NB WB

(4.10)

IC = IS exp where IS =

Equation (4.9) implies that the bipolar transistor indeed operates as a voltagecontrolled current source, proving a good candidate for amplification. We may alternatively say the transistor performs “voltage-to-current conversion.” 2 In an npn transistor, electrons go from the emitter to the collector. Thus, the conventional direction of the current is from the collector to the emitter.

114

Chapter 4 Physics of Bipolar Transistors

Example 4.2

Determine the current IX in Fig. 4.9(a) if Q1 and Q2 are identical and operate in the active mode and V1 = V2 .

IX I C1

I C2 Q1

V1

Q2

V2

V3

(a)

IX I C1

I C2 Q1

V1

IX

Q2

V3

2A E

V3

V1 Q eq C C

B

B

AE

2A E

AE

E

E (b)

Figure 4.9 (a) Two identical transistors drawing current from VC , (b) equivalence to a single transistor having twice the area. Solution

Since IX = IC 1 + IC 2 , we have

IX ≈ 2

AE qDn ni2 V1 exp . NB WB VT

(4.11)

This result can also be viewed as the collector current of a single transistor having an emitter area of 2AE . In fact, redrawing the circuit as shown in Fig. 4.9(b) and noting that Q1 and Q2 experience identical voltages at their respective terminals, we say the two transistors are “in parallel,” operating as a single transistor with twice the emitter area of each. Exercise

Repeat the above example if Q1 has an emitter area of AE and Q2 an emitter area of 8AE .

4.3 Operation of Bipolar Transistor in Active Mode

115

Example 4.3

In the circuit of Fig. 4.9 (a), Q1 and Q2 are identical and operate in the active mode. Determine V1 − V2 such that IC 1 = 10IC 2 .

Solution

From Eq. (4.9), we have IC 1 = IC 2 and hence exp

V1 VT , V2 IS exp VT IS exp

(4.12)

V1 − V2 = 10. VT

(4.13)

That is, V1 − V2 = VT ln 10

(4.14)

≈ 60 mV at T = 300 K.

(4.15)

Identical to Eq. (2.109), this result is, of course, expected because the exponential dependence of IC upon VBE indicates a behavior similar to that of diodes. We therefore consider the base-emitter voltage of the transistor relatively constant and approximately equal to 0.8 V for typical collector current levels. Exercise

Repeat the above example if Q1 and Q2 have different emitter areas, i.e., AE1 = nAE2 .

Example 4.4

Typical discrete bipolar transistors have a large area, e.g., 500 μm × 500 μm, whereas modern integrated devices may have an area as small as 0.5 μm × 0.2 μm. Assuming other device parameters are identical, determine the difference between the base-emitter voltage of two such transistors for equal collector currents.

Solution

From Eq. (4.9), we have VBE = VT ln(IC /IS ) and hence VBEint − VBEdis = VT ln

IS1 , IS2

(4.16)

where VBEint = VT ln(IC 2 /IS2 ) and VBEdis = VT ln(IC 1 /IS1 ) denote the base-emitter voltages of the integrated and discrete devices, respectively. Since IS ∝ AE , AE2 VBEint − VBEdis = VT ln . (4.17) AE1 For this example, AE2 /AE1 = 2.5 × 106 , yielding VBEint − VBEdis = 383 mV.

(4.18)

In practice, however, VBEint − VBEdis falls in the range of 100 to 150 mV because of differences in the base width and other parameters. The key point here is that VBE = 800 mV is a reasonable approximation for integrated transistors and should be lowered to about 700 mV for discrete devices. Exercise

Repeat the above comparison for a very small integrated device with an emitter area of 0.15 μm × 0.15 μ.

116

Chapter 4 Physics of Bipolar Transistors Since many applications deal with voltage quantities, the collector current generated by a bipolar transistor typically flows through a resistor to produce a voltage.

Example 4.5

Determine the output voltage in Fig. 4.10 if IS = 5 × 10−16 A.

RL

1 kΩ

IC 750 mV

Figure 4.10 Solution

Q1

3V

Vout

Simple stage with biasing.

Using Eq. (4.9), we write IC = 1.69 mA. This current flows through RL , generating a voltage drop of 1 k × 1.69 mA = 1.69 V. Since VCE = 3 V − IC RL , we obtain Vout = 1.31 V.

Exercise

(4.19)

What happens if the load resistor is halved?

Equation (4.9) reveals an interesting property of the bipolar transistor: the collector current does not depend on the collector voltage (so long as the device remains in the active mode). Thus, for a fixed base-emitter voltage, the device draws a constant current, acting as a current source [Fig. 4.11(a)]. Plotted in Fig. 4.11(b) is the current as a function of the collector-emitter voltage, exhibiting a constant value for VCE > V1 .3 Constant current sources find application in many electronic circuits and we will see numerous examples of their usage in this book. In Section 4.5, we study the behavior of the transistor for VCE < VBE . IC

V1

Q1

I S exp

V1

Forward Active Region

VT V1

(a)

Figure 4.11

V CE (b)

(a) Bipolar transistor as a current source, (b) I/V characteristic.

4.3.2 Base and Emitter Currents Having determined the collector current, we now turn our attention to the base and emitter currents and their dependence on the terminal voltages. Since the bipolar transistor must satisfy Kirchoff’s current law, calculation of the base current readily yields the emitter current as well.

3

Recall that VCE > V1 is necessary to ensure the collector-base junction remains reverse biased.

4.3 Operation of Bipolar Transistor in Active Mode

117

IC n IB V BE

e

p

n V CE

p V BE

+ h

n

+

V CE

e

+ h

n

+

IE (a)

Figure 4.12

(b)

Base current resulting from holes (a) crossing to emitter and (b) recombining with

electrons.

In the npn transistor of Fig. 4.12 (a), the base current, IB , results from the flow of holes. Recall from Eq. (2.99) that the hole and electron currents in a forward-biased pn junction bear a constant ratio given by the doping levels and other parameters. Thus, the number of holes entering from the base to the emitter is a constant fraction of the number of electrons traveling from the emitter to the base. As an example, for every 200 electrons injected by the emitter, one hole must be supplied by the base. In practice, the base current contains an additional component of holes. As the electrons injected by the emitter travel through the base, some may “recombine” with the holes [Fig. 4.12 (b)]; inessence, some electrons and holes are “wasted” as a result of recombination. For example, on the average, out of every 200 electrons injected by the emitter, one recombines with a hole. In summary, the base current must supply holes for both reverse injection into the emitter and recombination with the electrons traveling toward the collector. We can therefore view IB as a constant fraction of IE or a constant fraction of IC . It is common to write IC = βIB ,

(4.20)

where β is called the “current gain” of the transistor because it shows how much the base current is “amplified.” Depending on the device structure, the β of npn transistors typically ranges from 50 to 200. In order to determine the emitter current, we apply the KCL to the transistor with the current directions depicted in Fig. 4.12 (a): IE = IC + IB 1 = IC 1 + . β

(4.21) (4.22)

We can summarize our findings as follows: IC = IS exp

VBE VT

(4.23)

IB =

1 VBE IS exp β VT

(4.24)

IE =

β +1 VBE . IS exp β VT

(4.25)

118

Chapter 4 Physics of Bipolar Transistors It is sometimes useful to write IC = [β/(β + 1)]IE and denote β/(β + 1) by α. For β = 100, α = 0.99, suggesting that α ≈ 1 and IC ≈ IE are reasonable approximations. In this book, we assume that the collector and emitter currents are approximately equal.

Example 4.6

A bipolar transistor having IS = 5 × 10−16 A is biased in the forward active region with VBE = 750 mV. If the current gain varies from 50 to 200 due to manufacturing variations, calculate the minimum and maximum terminal currents of the device.

Solution

For a given VBE , the collector current remains independent of β: VBE VT

(4.26)

= 1.685 mA.

(4.27)

IC = IS exp

The base current varies from IC /200 to IC /50: 8.43 μA < IB < 33.7 μA.

(4.28)

On the other hand, the emitter current experiences only a small variation because (β + 1)/β is near unity for large β: 1.005IC < IE < 1.02IC

(4.29)

1.693 mA < IE < 1.719 mA. Exercise

4.4

(4.30)

Repeat the above example if the area of the transistor is doubled.

BIPOLAR TRANSISTOR MODELS AND CHARACTERISTICS 4.4.1 Large-Signal Model With our understanding of the transistor operation in the forward active region and the derivation of Eqs. (4.23)–(4.25), we can now construct a model that proves useful in the analysis and design of circuits—in a manner similar to the developments in Chapter 2 for the pn junction. Since the base-emitter junction is forward-biased in the active mode, we can place a diode between the base and emitter terminals. Moreover, since the current drawn from the collector and flowing into the emitter depends on only the base-emitter voltage, we add a voltage-controlled current source between the collector and the emitter, arriving at the model shown in Fig. 4.13. As illustrated in Fig. 4.11, this current remains independent of the collector-emitter voltage. B

C

I S exp

VBE IS

β Figure 4.13

exp

V BE VT

V BE VT

E

Large-signal model of bipolar transistor in active region.

4.4 Bipolar Transistor Models and Characteristics

119

But how do we ensure that the current flowing through the diode is equal to 1/β times the collector current? Equation (4.24) suggests that the base current is equal to that of a diode having a reverse saturation current of IS /β. Thus, the base-emitter junction is modeled by a diode whose cross section area is 1/β times that of the actual emitter area. With the interdependencies of currents and voltages in a bipolar transistor, the reader may wonder about the cause and effect relationships. We view the chain of dependencies as VBE → IC → IB → IE ; i.e., the base-emitter voltage generates a collector current, which requires a proportional base current, and the sum of the two flows through the emitter.

Example 4.7

Consider the circuit shown in Fig. 4.14 (a), where IS,Q1 = 5 × 10−17 A and VBE = 800 mV. Assume β = 100. (a) Determine the transistor terminal currents and voltages and verify that the device indeed operates in the active mode. (b) Determine the maximum value of RC that permits operation in the active mode. VX (V)

IC V BE

2.0

500 Ω

RC

X Q1

VCC

2V

1.424 0.800 500

(a)

1041

R C (Ω )

(b)

Figure 4.14 (a) Simple stage with biasing, (b) variation of collector voltage as a function of collector resistance. Solution

(a) Using Eq. (4.23)–(4.25), we have IC = 1.153 mA

(4.31)

IB = 11.53 μA

(4.32)

IE = 1.165 mA.

(4.33)

The base and emitter voltages are equal to +800 mV and zero, respectively. We must now calculate the collector voltage, VX . Writing a KVL from the 2-V power supply and across RC and Q1 , we obtain VCC = RC IC + VX .

(4.34)

VX = 1.424 V.

(4.35)

That is,

Since the collector voltage is more positive than the base voltage, this junction is reversebiased and the transistor operates in the active mode. (b) What happens to the circuit as RC increases? Since the voltage drop across the resistor, RC IC , increases while VCC is constant, the voltage at node X drops.

120

Chapter 4 Physics of Bipolar Transistors The device approaches the “edge” of the forward active region if the base-collector voltage falls to zero, i.e., as VX → +800 mV. Rewriting Eq. (4.33) yields: RC =

VCC − VX , IC

(4.36)

which, for VX = +800 mV, reduces to RC = 1041 .

(4.37)

Figure 4.14(b) plots VX as a function of RC . This example implies that there exists a maximum allowable value of the collector resistance, RC , in the circuit of Fig. 4.14(a). As we will see in Chapter 5, this limits the voltage gain that the circuit can provide. Exercise

In the above example, what is the minimum allowable value of VCC for transistor operation in the active mode? Assume RC = 500 .

The reader may wonder why the equivalent circuit of Fig. 4.13 is called the “large-signal model.” After all, the above example apparently contains no signals! This terminology emphasizes that the model can be used for arbitrarily large voltage and current changes in the transistor (so long as the device operates in the active mode). For example, if the base-emitter voltage varies from 800 mV to 300 mV, and hence the collector current by many orders of magnitude,4 the model still applies. This is in contrast to the small-signal model, studied in Section 4.4.4.

4.4.2 I/V Characteristics The large-signal model naturally leads to the I/V characteristics of the transistor. With three terminal currents and voltages, we may envision plotting different currents as a function of the potential difference between every two terminals—an elaborate task. However, as explained below, only a few of such characteristics prove useful. The first characteristic to study is, of course, the exponential relationship inherent in the device. Figure 4.15(a) plots IC versus VBE with the assumption that the collector voltage is constant and no lower than the base voltage. As shown in Fig. 4.11, IC is independent of VCE ; thus, different values of VCE do not alter the characteristic. Next, we examine IC for a given VBE but with VCE varying. Illustrated in Fig. 4.15(b), the characteristic is a horizontal line because IC is constant if the device remains in the active mode (VCE > VBE ). On the other hand, if different values are chosen for VBE , the characteristic moves up or down. The two plots of Fig. 4.15 constitute the principal characteristics of interest in most analysis and design tasks. Equations (4.24) and (4.25) suggest that the base and emitter currents follow the same behavior.

4

A 500-mV change in VBE leads to 500 mV/60 mV = 8.3 decades of change in IC .

4.4 Bipolar Transistor Models and Characteristics IC

IC Q1

V CE

IC

V CE Q1

V BE

V BE

121

IC I S exp I S exp

V BE2

V BE = V B2

VT V BE1

V BE = V B1

VT

V BE

V CE

(a)

(b)

Figure 4.15 Collector current as a function of (a) base-emitter voltage and (b) collectoremitter voltage.

Example 4.8

For a bipolar transistor, IS = 5 × 10−17 A and β = 100. Construct the IC -VBE , IC -VCE , IB -VBE , and IB -VCE characteristics.

Solution

We determine a few points along the IC -VBE characteristics, e.g., VBE1 = 700 mV ⇒ IC 1 = 24.6 μA

(4.38)

VBE2 = 750 mV ⇒ IC 2 = 169 μA

(4.39)

VBE3 = 800 mV ⇒ IC 3 = 1.153 mA.

(4.40)

The characteristic is depicted in Fig. 4.16 (a). IC

IC 1.153 mA

1.153 mA

V BE = 800 mV

μA

169

μA

V BE = 750 mV

24.6

μA

24.6

μA

V BE = 700 mV

700 750 800

169

V BE

V CE

(mV) (a)

(b)

IB

IB

μA

11.5

μA

V BE = 800 mV

0.169

μA

0.169

μA

V BE = 750 mV

0.025

μA

0.025

μA

V BE = 700 mV

700 750 800

11.5

V CE

V BE (mV)

(c)

(d)

(a) Collector current as a function of VBE , (b) collector current as a function of VCE , (c) base current as a function of VBE , (d) base current as a function of VCE .

Figure 4.16

122

Chapter 4 Physics of Bipolar Transistors Using the values obtained above, we can also plot the IC -VCE characteristic as shown in Fig. 4.16(b), concluding that the transistor operates as a constant current source of, e.g., 169 μA if its base-emitter voltage is held at 750 mV. We also remark that, for equal increments in VBE , IC jumps by increasingly greater steps: 24.6 μA to 169 μA to 1.153 mA. We return to this property in Section 4.4.3. For IB characteristics, we simply divide the IC values by 100 [Figs. 4.16(c) and (d)].

Exercise

What change in VBE doubles the base current?

The reader may wonder what exactly we learn from the I/V characteristics. After all, compared to Eqs. (4.23)–(4.25), the plots impart no additional information. However, as we will see throughout this book, the visualization of equations by means of such plots greatly enhances our understanding of the devices and the circuits employing them.

4.4.3 Concept of Transconductance Our study thus far shows that the bipolar transistor acts as a voltage-dependent current source (when operating in the forward active region). An important question that arises here is, how is the performance of such a device quantified? In other words, what is the measure of the “goodness” of a voltage-dependent current source? The example depicted in Fig. 4.1 suggests that the device becomes “stronger” as K increases because a given input voltage yields a larger output current. We must therefore concentrate on the voltage-to-current conversion property of the transistor, particularly as it relates to amplification of signals. More specifically, we ask, if a signal changes the base-emitter voltage of a transistor by a small amount (Fig. 4.17), how much change is produced in the collector current? Denoting the change in IC by IC , we recognize that the “strength” of the device can be represented by IC /VBE . For example, if a base-emitter voltage change of 1 mV results in a IC of 0.1 mA in one transistor and 0.5 mA in another, we can view the latter as a better voltage-dependent current source or “voltage-to-current converter.” The ratio IC /VBE approaches dIC /dVBE for very small changes and, in the limit, is called the “transconductance,” gm:∗ gm =

dIC . dVBE

(4.41)

IC

ΔV BE

Figure 4.17

∗

Test circuit for measurement of gm.

Note that VC E is constant here.

Q1

V CE

4.4 Bipolar Transistor Models and Characteristics

123

Note that this definition applies to any device that approximates a voltage-dependent current source (e.g., another type of transistor described in Chapter 6). For a bipolar transistor, Eq. (4.9) gives d VBE IS exp dVBE VT

(4.42)

=

1 VBE IS exp VT VT

(4.43)

=

IC . VT

(4.44)

gm =

The close resemblance between this result and the small-signal resistance of diodes [Eq. (3.58)] is no coincidence and will become clearer in the next chapter. Equation (4.44) reveals that, as IC increases, the transistor becomes a better amplifying device by producing larger collector current excursions in response to a given signal level applied between the base and the emitter. The transconductance may be expressed in −1 or “siemens,” S. For example, if IC = 1 mA, then with VT = 26 mV, we have gm = 0.0385 −1

(4.45)

= 0.0385 S

(4.46)

= 38.5 mS.

(4.47)

However, as we will see throughout this book, it is often helpful to view gm as the inverse of a resistance; e.g., for IC = 1 mA, we may write gm =

1 . 26

(4.48)

The concept of transconductance can be visualized with the aid of the transistor I/V characteristics. As shown in Fig. 4.18, gm = dIC /dVBE simply represents the slope of IC -VBE characteristic at a given collector current, IC 0 , and the corresponding base-emitter voltage, VBE0 . In other words, if VBE experiences a small perturbation ±V around VBE0 , then the collector current displays a change of ±gm V around IC 0 , where gm = IC 0 /VT . Thus, the

IC g m ΔV

I C0 V BE0

V BE

ΔV Figure 4.18

Illustration of transconductance.

124

Chapter 4 Physics of Bipolar Transistors value of IC 0 must be chosen according to the required gm and, ultimately, the required gain. We say the transistor is “biased” at a collector current of IC 0 , meaning the device carries a bias (or “quiescent”) current of IC 0 in the absence of signals.5

Example 4.9

Consider the circuit shown in Fig. 4.19(a). What happens to the transconductance of Q1 if the area of the device is increased by a factor of n? n I C0 I C0 V BE0

I C0 Q1

I C0

V CE

V CE V BE0

(a)

Figure 4.19

I C0

(b)

(a) One transistor and (b) n transistors providing transconductance.

Solution

Since IS ∝ AE , IS is multiplied by the same factor. Thus, IC = IS exp (VBE /VT ) also rises by a factor of n because VBE is constant. As a result, the transconductance increases by a factor of n. From another perspective, if n identical transistors, each carrying a collector current of IC 0 , are placed in parallel, then the composite device exhibits a transconductance equal to n times that of each [Fig. 4.19(b)]. On the other hand, if the total collector current remains unchanged, then so does the transconductance.

Exercise

Repeat the above example if VBE0 is reduced by VT ln n.

It is also possible to study the transconductance in the context of the IC -VCE characteristics of the transistor with VBE as a parameter. Illustrated in Fig. 4.20 for two different bias currents IC 1 and IC 2 , the plots reveal that a change of V in VBE results in a greater change in IC for operation around IC 2 than around IC 1 because gm2 > gm1 . The derivation of gm in Eqs. (4.42)–(4.44) suggests that the transconductance is fundamentally a function of the collector current rather than the base current. For example, if IC remains constant but β varies, then gm does not change but IB does. For this reason, the collector bias current plays a central role in the analysis and design, with the base current viewed as secondary, often undesirable effect. As shown in Fig. 4.10,the current produced by the transistor may flow through a resistor to generate a proportional voltage. We exploit this concept in Chapter 5 to design amplifiers.

4.4.4 Small-Signal Model Electronic circuits, e.g., amplifiers, may incorporate a large number of transistors, thus posing great difficulties in the analysis and design. Recall from Chapter 3 that diodes can 5

Unless otherwise stated, we use the term “bias current” to refer to the collector bias current.

4.4 Bipolar Transistor Models and Characteristics IC

g

m2

ΔV

V BE = V B2 + ΔV

I C2

V BE = V B2

I C1

V BE = V B1 + ΔV V BE = V B1 g

125

m1

ΔV V CE

Figure 4.20

Transconductance for different collector bias currents.

be reduced to linear devices through the use of the small-signal model. A similar benefit accrues if a small-signal model can be developed for transistors. The derivation of the small-signal model from the large-signal counterpart is relatively straightforward. We perturb the voltage difference between every two terminals (while the third terminal remains at a constant potential), determine the changes in the currents flowing through all terminals, and represent the results by proper circuit elements such as controlled current sources or resistors. Figure 4.21 depicts two conceptual examples where VBE or VCE is changed by V and the changes in IC , IB , and IE are examined. ΔI C ΔI B ΔV

Q1

ΔI C ΔI B

V CE

ΔI E

ΔV Q1

ΔI E

V BE (b)

(a)

Figure 4.21 Excitation of bipolar transistor with small changes in (a) base-emitter and (b) collector-emitter voltage.

Let us begin with a change in VBE while the collector voltage is constant (Fig. 4.22).We know from the definition of transconductance that IC = gm VBE ,

(4.49)

concluding that a voltage-controlled current source must be connected between the collector and the emitter with a value equal to gm V. For simplicity, we denote VBE by vπ and the change in the collector current by gmvπ . The change in VBE creates another change as well: IB = =

IC β

(4.50)

gm VBE . β

(4.51)

126

Chapter 4 Physics of Bipolar Transistors Δ I C = g m ΔV BE

ΔI B ΔV BE

I S exp

VBE

V CE

Q1

ΔV BE

ΔI C V BE + ΔV BE

V CE

VT

ΔI E

B

C

ΔV BE

g

C

B

ΔV BE m

E

Figure 4.22

B

g vπ m

vπ

C rπ

vπ

g vπ m

E

E

Development of small-signal model.

That is, if the base-emitter voltage changes by VBE , the current flowing between these two terminals changes by (gm/β)VBE . Since the voltage and current correspond to the same two terminals, they can be related by Ohm’s Law, i.e., by a resistor placed between the base and emitter having a value: rπ = =

VBE IB

(4.52)

β . gm

(4.53)

Thus, the forward-biased diode between the base and the emitter is modeled by a small-signal resistance equal to β/gm. This result is expected because the diode carries a bias current equal to IC /β and, from Eq. (3.58), exhibits a small-signal resistance of VT /(IC /β) = β(VT /IC ) = β/gm. We now turn our attention to the collector and apply a voltage change with respect to the emitter (Fig. 4.23). As illustrated in Fig. 4.11, for a constant VBE , the collector voltage has no effect on IC or IB because IC = IS exp (VBE /VT ) and IB = IC /β. Since VCE leads to no change in any of the terminal currents, the model developed in Fig. 4.22 need not be altered. How about a change in the collector-base voltage? As studied in Problem 4.15, such a change also results in a zero change in the terminal currents.

ΔI C ΔV CE

V BE

VBE

Q1 V BE

Figure 4.23

Response of bipolar transistor to small change in VCE .

I S exp

V BE VT

ΔV CE

4.4 Bipolar Transistor Models and Characteristics

127

The simple small-signal model developed in Fig. 4.22 serves as a powerful, versatile tool in the analysis and design of bipolar circuits. We should remark that both parameters of the model, gm and rπ , depend on the bias current of the device. With a high collector bias current, a greater gm is obtained, but the impedance between the base and emitter falls to lower values. Studied in Chapter 5, this trade-off proves undesirable in some cases.

Example 4.10

Consider the circuit shown in Fig. 4.24(a), where v1 represents the signal generated by a microphone, IS = 3 × 10−16 A, β = 100, andQ1 operates in the active mode. (a) If v1 = 0, determine the small-signal parameters of Q1 . (b) If the microphone generates a 1-mV signal, how much change is observed in the collector and base currents? IC

iB Q1

V CC = 1.8 V v1

v1

rπ

iC vπ

g vπ m

800 mV

(a)

Figure 4.24

(b)

(a) Transistor with bias and small-signal excitation, (b) small-signal equivalent

circuit. Solution

(a) Writing IC = IS exp (VBE /VT ), we obtain a collector bias current of 6.92 mA for VBE = 800 mV. Thus, IC VT

(4.54)

1 , 3.75

(4.55)

β gm

(4.56)

= 375 .

(4.57)

gm =

= and rπ =

(b) Drawing the small-signal equivalent of the circuit as shown in Fig. 4.24(b) and recognizing that vπ = v1 , we obtain the change in the collector current as: IC = gmv1

(4.58)

1 mV 3.75

(4.59)

= 0.267 mA.

(4.60)

=

128

Chapter 4 Physics of Bipolar Transistors The equivalent circuit also predicts the change in the base current as v1 IB = rπ

(4.61)

1 mV 375

(4.62)

= 2.67 μA,

(4.63)

=

which is, of course, equal to IC /β. Exercise

Repeat the above example if IS is halved.

The above example is not a useful circuit. The microphone signal produces a change in IC , but the result flows through the 1.8-V battery. In other words, the circuit generates no output. On the other hand, if the collector current flows through a resistor, a useful output is provided.

Example 4.11

The circuit of Fig. 4.24 (a) is modified as shown in Fig. 4.25, where resistor RC converts the collector current to a voltage. (a) Verify that the transistor operates in the active mode. (b) Determine the output signal level if the microphone produces a 1-mV signal. RC

100 Ω

V CC = 1.8 V

Q 1 Vout v1 800 mV

Figure 4.25 Solution

Simple stage with bias and small-signal excitation.

(a) The collector bias current of 6.92 mA flows through RC , leading to a potential drop of IC RC = 692 mV. The collector voltage, which is equal to Vout , is thus given by: Vout = VCC − RC IC

(4.64)

= 1.108 V.

(4.65)

Since the collector voltage (with respect to ground) is more positive than the base voltage, the device operates in the active mode. (b) As seen in the previous example, a 1-mV microphone signal leads to a 0.267-mA change in IC . Upon flowing through RC , this change yields a change of 0.267 mA × 100 = 26.7 mV in Vout . The circuit therefore amplifies the input by a factor of 26.7. Exercise

What value of RC results in a zero collector-base voltage?

4.4 Bipolar Transistor Models and Characteristics

129

The foregoing example demonstrates the amplification capability of the transistor. We will study and quantify the behavior of this and other amplifier topologies in the next chapter. Small-Signal Model of Supply Voltage We have seen that the use of the small-signal model of diodes and transistors can simplify the analysis considerably. In such an analysis, other components in the circuit must also be represented by a small-signal model. In particular, we must determine how the supply voltage, VCC , behaves with respect to small changes in the currents and voltages of the circuit. The key principle here is that the supply voltage (ideally) remains constant even though various voltages and currents within the circuit may change with time. Since the supply does not change and since the small-signal model of the circuit entails only changes in the quantities, we observe that VCC must be replaced with a zero voltage to signify the zero change. Thus, we simply “ground” the supply voltage in small-signal analysis. Similarly, any other constant voltage in the circuit is replaced with a ground connection. To emphasize that such grounding holds for only signals, we sometimes say a node is an “ac ground.” 4.4.5 Early Effect Our treatment of the bipolar transistor has thus far concentrated on the fundamental principles, ignoring second-order effects in the device and their representation in the largesignal and small-signal models. However, some circuits require attention to such effects if meaningful results are to be obtained. The following example illustrates this point. Example 4.12

Considering the circuit of Example 4.11, suppose we raise RC to 200 and VCC to 3.6 V. Verify that the device operates in the active mode and compute the voltage gain.

Solution

The voltage drop across RC now increases to 6.92 mA × 200 = 1.384 V, leading to a collector voltage of 3.6 V − 1.384 V = 2.216 V and guaranteeing operation in the active mode. Note that if VCC is not doubled, then Vout = 1.8 V − 1.384 V = 0.416 V and the transistor is not in the forward active region. Recall from part (b) of the above example that the change in the output voltage is equal to the change in the collector current multiplied by RC . Since RC is doubled, the voltage gain must also double, reaching a value of 53.4. This result is also obtained with the aid of the small-signal model. Illustrated in Fig. 4.26, the equivalent circuit yields vout = −gmvπ RC = −gmv1 RC and hence vout /v1 = −gmRC . With gm = (3.75 )−1 and RC = 200 , we have vout /v1 = −53.4.

RC

v1

Figure 4.26

Exercise

rπ

vπ

200 Ω

g vπ m

v out

Small-signal equivalent circuit of the stage shown in Fig. 4.25.

What happens if RC = 250 ?

130

Chapter 4 Physics of Bipolar Transistors This example points to an important trend: if RC increases, so does the voltage gain of the circuit. Does this mean that, if RC → ∞, then the gain also grows indefinitely? Does another mechanism in the circuit, perhaps in the transistor, limit the maximum gain that can be achieved? Indeed, the “Early effect” translates to a nonideality in the device that can limit the gain of amplifiers. To understand this effect, we return to the internal operation of the transistor and reexamine the claim shown in Fig. 4.11that “the collector current does not depend on the collector voltage.” Consider the device shown in Fig. 4.27(a), where the collector voltage is somewhat higher than the base voltage and the reverse bias across the junction creates a certain depletion region width. Now suppose VCE is raised to VCE2 [Fig. 4.27(b)], thus increasing the reverse bias and widening the depletion region in the collector and base areas. Since the base charge profile must still fall to zero at the edge of depletion region, x2 , the slope of the profile increases. Equivalently, the effective base width, WB , in Eq. (4.8) decreases, thereby increasing the collector current. Discovered by Early, this phenomenon poses interesting problems in amplifier design (Chapter 5).

V CE1 n p

e

x

n

+

n

x2 x1

V BE

V CE2

x '2 x1

V BE

(a)

Figure 4.27

p

e

x

n

+

(b)

(a) Bipolar device with base and collector bias voltages, (b) effect of higher collector

voltage.

How is the Early effect represented in the transistor model? We must first modify Eq. (4.9) to include this effect. It can be proved that the rise in the collector current with VCE can be approximately expressed by a multiplicative factor:

IC =

AE qDn ni2 VBE VCE exp , −1 1+ NE WB VT VA

VCE VBE 1+ . ≈ IS exp VT VA

(4.66)

(4.67)

where WB is assumed constant and the second factor, 1 + VCE /VA , models the Early effect. The quantity VA is called the “Early voltage.” It is instructive to examine the I/V characteristics of Fig. 4.15 in the presence of the Early effect. For a constant VCE , the dependence of IC upon VBE remains exponential but with a somewhat greater slope [Fig. 4.28(a)]. On the other hand, for a constant VBE , the IC − VCE characteristic displays a nonzero slope [Fig. 4.28(b)]. In fact, differentiation

4.4 Bipolar Transistor Models and Characteristics IC

With Early Effect

With Early Effect

IC

I S exp

Without Early Effect

V BE1

Without Early Effect

VT

V BE

V CE

(a)

Figure 4.28

131

(b)

Collector current as a function of (a) VBE and (b) VCE with and without

Early effect.

of Eq. (4.67) with respect to VCE yields δIC VBE 1 = IS exp δVCE VT VA ≈

(4.68)

IC , VA

(4.69)

where it is assumed VCE VA and hence IC ≈ IS exp (VBE /VT ). This is a reasonable approximation in most cases. The variation of IC with VCE in Fig. 4.28(b) reveals that the transistor in fact does not operate as an ideal current source, requiring modification of the perspective shown in Fig. 4.11(a). The transistor can still be viewed as a two-terminal device but with a current that varies to some extent with VCE (Fig. 4.29). X

X

V1

Figure 4.29

(

Q1

I S exp

)(

V1

VT

1+

VX VA

)

Realistic model of bipolar transistor as a current source.

Example 4.13

A bipolar transistor carries a collector current of 1 mA with VCE = 2 V. Determine the required base-emitter voltage if VA = ∞ or VA = 20 V. Assume IS = 2 × 10−16 A.

Solution

With VA = ∞, we have from Eq. (4.67) VBE = VT ln

IC IS

= 760.3 mV.

(4.70) (4.71)

132

Chapter 4 Physics of Bipolar Transistors If VA = 20 V, we rewrite Eq. (4.67) as ⎞

⎛ ⎜ IC VBE = VT ln⎜ ⎝ IS

⎟ 1 ⎟ VCE ⎠ 1+ VA

(4.72)

= 757.8 mV.

(4.73)

In fact, for VCE VA , we have (1 + VCE /VA )−1 ≈ 1 − VCE /VA

VBE

IC VCE ≈ VT ln + VT ln 1 − IS VA

(4.74)

VCE IC − VT , IS VA

(4.75)

≈ VT ln

where it is assumed ln(1 − ) ≈ − for 1. Exercise

Repeat the above example if two such transistors are placed in parallel.

Large-Signal and Small-Signal Models The presence of Early effect alters the transistor models developed in Sections 4.4.1 and 4.4.4. The large-signal model of Fig. 4.13 must now be modified to that in Fig. 4.30, where VCE VBE 1+ IC = IS exp VT VA IB =

(4.76)

1 VBE IS exp β VT

(4.77)

IE = IC + IB .

(4.78)

Note that IB is independent of VCE and still given by the base-emitter voltage. B

IC

IB

(

VBE

I S exp

C

)(

V1

VT

1+

V CE VA

)

IE E

Figure 4.30

Large-signal model of bipolar transistor including Early effect.

4.4 Bipolar Transistor Models and Characteristics

133

For the small-signal model, we note that the controlled current source remains unchanged and gm is expressed as gm =

dIC dVBE

(4.79)

1 VCE VBE = IS exp 1+ VT VT VA =

IC . VT

(4.80)

(4.81)

Similarly, rπ =

β gm

=β

VT . IC

(4.82)

(4.83)

Considering that the collector current does vary with VCE , let us now apply a voltage change at the collector and measure the resulting current change [Fig. 4.31(a)]: VCE + VCE VBE IC + IC = IS exp 1+ . VT VA

(4.84)

VBE VCE IC = IS exp , VT VA

(4.85)

It follows that

which is consistent with Eq. (4.69). Since the voltage and current change correspond to the same two terminals, they satisfy Ohm’s Law, yielding an equivalent resistor: rO =

VCE IC

=

VA VBE IS exp VT

≈

VA . IC

(4.86)

(4.87)

(4.88)

Depicted in Fig. 4.31(b), the small-signal model contains only one extra element, rO , to represent the Early effect. Called the “output resistance,” rO plays a critical role in highgain amplifiers (Chapter 5). Note that both rπ and rO are inversely proportionally to the bias current, IC .

134

Chapter 4 Physics of Bipolar Transistors ΔI C

B

ΔV

C rπ

Q1

g vπ m

vπ

rO

V BE E (a)

Figure 4.31

(b)

(a) Small change in VCE and (b) small-signal model including Early effect.

Example 4.14

A transistor is biased at a collector current of 1 mA. Determine the small-signal model if β = 100 and VA = 15 V.

Solution

We have gm = =

IC VT

(4.89)

1 , 26

(4.90)

and rπ =

β gm

(4.91)

= 2600 .

(4.92)

VA IC

(4.93)

= 15 k.

(4.94)

Also, rO =

Exercise

What early voltage is required if the output resistance must reach 25 k?

In the next chapter, we return to Example 4.12 and determine the gain of the amplifier in the presence of the Early effect. We will conclude that the gain is eventually limited by the transistor output resistance, rO . Figure 4.32 summarizes the concepts studied in this section. An important notion that has emerged from our study of the transistor is the concept of biasing. We must create proper dc voltages and currents at the device terminals to accomplish two goals: (1) guarantee operation in the active mode (VBE > 0, VCE ≥ 0); e.g., the load resistance tied to the collector faces an upper limit for a given supply voltage (Example 4.7); (2) establish a collector current that yields the required values for the smallsignal parameters gm, rO , and rπ . The analysis of amplifiers in the next chapter exercises these ideas extensively. Finally, we should remark that the small-signal model of Fig. 4.31(b) does not reflect the high-frequency limitations of the transistor. For example, the base-emitter and basecollector junctions exhibit a depletion-region capacitance that impacts the speed. These properties are studied in Chapter 11.

4.5 Operation of Bipolar Transistor in Saturation Mode Operation in Active Mode

I C = I S exp

e V BE

p

n

e

β

+

n

Small-Signal Model B

V BE VT I S exp

E

C

rπ

V BE

IC

V BE VT

+

IC C

exp

p

I/V Characteristrics

B

IS

V CE

V CE

Large-Signal Model

VBE

VT

V BE

+ h

I S exp

V BE

n

n

135

vπ

V BE1

g vπ m

E

VT V CE

Early Effect

n

V CE

p

V BE n

Modified Small-Signal Model

B

C rπ

vπ

g vπ m

rO

+

E

Figure 4.32

4.5

Summary of concepts studied thus far.

OPERATION OF BIPOLAR TRANSISTOR IN SATURATION MODE As mentioned in the previous section, it is desirable to operate bipolar devices in the forward active region, where they act as voltage-controlled current sources. In this section, we study the behavior of the device outside this region and the resulting difficulties. Let us set VBE to a typical value, e.g., 750 mV, and vary the collector voltage from a high level to a low level [Fig. 4.33(a)]. As VCE approaches VBE , and VBC goes from a negative value toward zero, the base-collector junction experiences less reverse bias. For VCE = VBE , the junction sustains a zero voltage difference, but its depletion region still absorbs most of the electrons injected by the emitter into the base. But what happens if VCE < VBE , i.e., VBC > 0 and the B-C junction is forward biased? We say the transistor enters the “saturation region.” Suppose VCE = 550 mV and hence VBC = +200 mV. We know from Chapter 2 that a typical diode sustaining 200 mV of forward bias carries an extremely small current.1 Thus, even in this case the 1 About nine orders of magnitude less than one sustaining 750 mV: (750 mV − 200 mV)/ (60 mV/dec) ≈ 9.2.

136

Chapter 4 Physics of Bipolar Transistors ΔI C

n V CE

Q1

e V BE

V BE

(a)

+ h

p

n

V CE

+

(b)

Figure 4.33 (a) Bipolar transistor with forward-biased base-collector junction, (b) flow of holes to collector.

transistor continues to operate as in the active mode, and we say the device is in “soft saturation.” If the collector voltage drops further, the B-C junction experiences greater forward bias, carrying a significant current [Fig. 4.33(b)]. Consequently, a large number of holes must be supplied to the base terminal—as if β is reduced. In other words, heavy saturation leads to a sharp rise in the base current and hence a rapid fall in β.

Example 4.15

A bipolar transistor is biased with VBE = 750 mV and has a nominal β of 100. How much B-C forward bias can the device tolerate if β must not degrade by more than 10%? For simplicity, assume base-collector and base-emitter junctions have identical structures and doping levels.

Solution

If the base-collector junction is forward-biased so much that it carries a current equal to one-tenth of the nominal base current, IB , then the β degrades by 10%. Since IB = IC /100, the B-C junction must carry no more than IC /1000. We therefore ask, what B-C voltage results in a current of IC /1000 if VBE = 750 mV gives a collector current of IC ? Assuming identical B-E and B-C junctions, we have VBE − VBC = VT ln

IC IC /1000 − VT ln IS IS

(4.95)

= VT ln 1000

(4.96)

≈ 180 mV.

(4.97)

That is, VBC = 570 mV. Exercise

Repeat the above example if VBE = 800 mV.

It is instructive to study the transistor large-signal model and I-V characteristics in the saturation region. We construct the model as shown in Fig. 4.34(a), including the base-collector diode. Note that the net collector current decreases as the device enters

4.5 Operation of Bipolar Transistor in Saturation Mode I S2 exp

137

V BE VT

D BC

D BC

B

C

VBE

D BE

I S1 exp

V BE VT

V BE

VBE

D BE

I S1 exp

V BE VT

E (a)

Figure 4.34

(b)

(a) Model of bipolar transistor including saturation effects, (b) case of open collector

terminal.

saturation because part of the controlled current IS1 exp (VBE /VT ) is provided by the B-C diode and need not flow from the collector terminal. In fact, as illustrated in Fig. 4.34(b), if the collector is left open, then DBC is forward-biased so much that its current becomes equal to the controlled current. The above observations lead to the IC -VCE characteristics depicted in Fig. 4.35, where IC begins to fall for VCE less than V1 , about a few hundred millivolts. The term “saturation” is used because increasing the base current in this region of operation leads to little change in the collector current.

Saturation Forward Active Region

IC

V1

Figure 4.35

V CE

Transistor I/V characteristics in different regions of operation.

In addition to a drop in β, the speed of bipolar transistors also degrades in saturation (Chapter 11). Thus, electronic circuits rarely allow operation of bipolar devices in this mode. As a rule of thumb, we permit soft saturation with VBC < 400 mV because the current in the B-C junction is negligible, provided that various tolerances in the component values do not drive the device into deep saturation. It is important to recognize that the transistor simply draws a current from any component tied to its collector, e.g., a resistor. Thus, it is the external component that defines the collector voltage and hence the region of operation.

138

Chapter 4 Physics of Bipolar Transistors

Example 4.16

For the circuit of Fig. 4.36, determine the relationship between RC and VCC that guarantees operation in soft saturation or active region.

V CC

RC IC V BE

Acceptable Region

V CC Q1

V BE 400 mV RC

(a)

Figure 4.36 Solution

(b)

(a) Simple stage, (b) acceptable range of VCC and RC .

In soft saturation, the collector current is still equal to IS exp (VBE /VT ). The collector voltage must not fall below the base voltage by more than 400 mV: VCC − RC IC ≥ VBE − 400 mV.

(4.98)

VCC ≥ IC RC + (VBE − 400 mV).

(4.99)

Thus, For a given value of RC , VCC must be sufficiently large so that VCC − IC RC still maintains a reasonable collector voltage. Exercise

Determine the maximum tolerable value of RC .

In the deep saturation region, the collector-emitter voltage approaches a constant value called VCE,sat (about 200 mV). Under this condition, the transistor bears no resemblance to a controlled current source and can be modeled as shown in Fig. 4.37.(The battery tied between C and E indicates that VCE is relatively constant in deep saturation.) B

C 800 mV

200 mV

E

Figure 4.37

4.6

Transistor model in deep saturation.

THE PNP TRANSISTOR We have thus far studied the structure and properties of the npn transistor, i.e., with the emitter and collector made of n-type materials and the base made of a p-type material. We may naturally wonder if the dopant polarities can be inverted in the three regions, forming a “pnp” device. More importantly, we may wonder why such a device would be useful.

4.6 The PNP Transistor

139

4.6.1 Structure and Operation Figure 4.38(a) shows the structure of a pnp transistor, emphasizing that the emitter is heavily doped. As with the npn counterpart, operation in the active region requires forwardbiasing the base-emitter junction and reverse-biasing the collector junction. Thus, VBE < 0 and VBC > 0. Under this condition, majority carriers in the emitter (holes) are injected into the base and swept away into the collector. Also, a linear profile of holes is formed in the base region to allow diffusion. A small number of base majority carriers (electrons) are injected into the emitter or recombined with the holes in the base region, thus creating the base current. Figure 4.38(b) illustrates the flow of the carriers. All of the operation principles and equations described for npn transistors apply to pnp devices as well.

x

p n

h

x2 x1

V BE p

p V CE V BE

+

V CE

e n + h e

p

+

Hole Density (a)

(b)

IE

V BE Q1 V BE (c)

V CE

IB

Q1

V CE

IC (d)

Figure 4.38 (a) Structure of pnp transistor, (b) current flow in pnp transistor, (c) proper biasing, (d) more intuitive view of (c).

Figure 4.38(c) depicts the symbol of the pnp transistor along with constant voltage sources that bias the device in the active region. In contrast to the biasing of the npn transistor in Fig. 4.6, here the base and collector voltages are lower than the emitter voltage. Following our convention of placing more positive nodes on the top of the page, we redraw the circuit as in Fig. 4.38(d) to emphasize VEB > 0 and VBC > 0 and to illustrate the actual direction of current flow into each terminal. 4.6.2 Large-Signal Model The current and voltage polarities in npn and pnp transistors can be confusing. We address this issue by making the following observations. (1) The (conventional) current always flows from a positive supply (i.e., top of the page) toward a lower potential (i.e., bottom of the page). Figure 4.39(a) shows two branches employing npn and pnp transistors, illustrating that the (conventional) current flows from collector to emitter in npn devices and from emitter to collector in pnp counterparts. Since the base current must be included in the emitter current, we note that IB1 and IC 1 add up to IE1 , whereas IE2 “loses” IB2 before emerging as IC 2 . (2) The distinction between active and saturation regions is based on the

140

Chapter 4 Physics of Bipolar Transistors Active Mode

Edge of Saturation

Saturation Mode

I E2 I C1 I B1

Q1

Q2

I B2

V CC

Active Mode

I C2

Edge of Saturation

Saturation Mode

I E1 0 (a)

(b)

Figure 4.39 (a) Voltage and current polarities in npn and pnp transistors, (b) illustration of active and saturation regions.

B-C junction bias. The different cases are summarized in Fig. 4.39(b), where the relative position of the base and collector nodes signifies their potential difference. We note that an npn transistor is in the active mode if the collector (voltage) is not lower than the base (voltage). For the pnp device, on the other hand, the collector must not be higher than the base. (3) The npn current equations (4.23)–(4.25) must be modified as follows for the pnp device: VEB VT

(4.100)

IB =

IS VEB exp β VT

(4.101)

IE =

β +1 VEB , IS exp β VT

(4.102)

IC = IS exp

where the current directions are defined in Fig. 4.40. The only difference between the npn and pnp equations relates to the base-emitter voltage that appears in the

E

IS

β

exp

V EB

IE

VT VEB

B

Figure 4.40

IB

Large-signal model of pnp transistor.

I S exp IC

V EB VT

C

4.6 The PNP Transistor

141

exponent, an expected result because VBE < 0 for pnp devices and must be changed to VEB to create a large exponential term. Also, the Early effect can be included as VEC VEB IC = IS exp 1+ . (4.103) VT VA Example 4.17

In the circuit shown in Fig. 4.41, determine the terminal currents of Q1 and verify operation in the forward active region. Assume IS = 2 × 10−16 A and β = 50, but VA = ∞.

Q1 1.2 V

Figure 4.41 Solution

X RC

V CC

2V

200 Ω

Simple stage using a pnp transistor.

We have VEB = 2 V − 1.2 V = 0.8 V and hence IC = IS exp

VEB VT

(4.104)

= 4.61 mA.

(4.105)

IB = 92.2 μA

(4.106)

IE = 4.70 mA.

(4.107)

It follows that

We must now compute the collector voltage and hence the bias across the B-C junction. Since RC carries IC , VX = RC IC = 0.922 V,

(4.108) (4.109)

which is lower than the base voltage. Invoking the illustration in Fig. 4.39(b), we conclude that Q1 operates in the active mode and the use of equations (4.100)–(4.102) is justified. Exercise

What is the maximum value of RC if the transistor must remain in soft saturation?

We should mention that some books assume all of the transistor terminal currents flow into the device, thus requiring that the right-hand side of Eqs. (4.100) and (4.101) be multiplied by a negative sign. We nonetheless continue with our notation as it reflects the actual direction of currents and proves more efficient in the analysis of circuits containing many npn and pnp transistors.

142

Chapter 4 Physics of Bipolar Transistors

Example 4.18

In the circuit of Fig. 4.42,Vin represents a signal generated by a microphone. Determine Vout for Vin = 0 and Vin = +5 mV if IS = 1.5 × 10−16 A.

Q1 V in

IC

1.7 V

Figure 4.42 Solution

RC

Vout

V CC

2.5 V

300 Ω

PNP stage with bias and small-signal voltages.

For Vin = 0, VEB = +800 mV and we have IC |Vin =0 = IS exp

VEB VT

= 3.46 mA,

(4.110) (4.111)

and hence Vout = 1.038 V.

(4.112)

If Vin increases to +5 mV, VEB = +795 mV and IC |Vin =+5 mV = 2.85 mA,

(4.113)

Vout = 0.856 V.

(4.114)

yielding

Note that as the base voltage rises, the collector voltage falls, a behavior similar to that of the npn counterparts in Fig. 4.25. Since a 5-mV change in Vin gives a 182-mV change in Vout , the voltage gain is equal to 36.4. These results are more readily obtained through the use of the small-signal model. Exercise

Determine Vout if Vin = −5 mV.

4.6.3 Small-Signal Model Since the small-signal model represents changes in the voltages and currents, we expect npn and pnp transistors to have similar models. Depicted in Fig. 4.43(a), the small-signal model of the pnp transistor is indeed identical to that of the npn device. Following the convention in Fig. 4.38(d), we sometimes draw the model as shown in Fig. 4.43(b). The reader may notice that the terminal currents in the small-signal model bear an opposite direction with respect to those in the large-signal model of Fig. 4.40. The small-signal model of pnp transistors may cause confusion, especially if drawn as in Fig. 4.43(b). In analogy with npn transistors, one may automatically assume that the

4.6 The PNP Transistor

B

ib

ic

rπ

g vπ m

vπ

E

ie

C

rO

rπ

g vπ m

vπ

rO

B

ie

C

ib

E

ic (b)

(a)

Figure 4.43

143

(a) Small-signal model of pnp transistor, (b) more intuitive view of (a).

“top” terminal is the collector and hence the model in Fig. 4.43(b) is not identical to that in Fig. 4.31(b). We caution the reader about this confusion. A few examples prove helpful here. Example 4.19

If the collector and base of a bipolar transistor are tied together, a two-terminal device results. Determine the small-signal impedance of the devices shown in Fig. 4.44(a). Assume VA = ∞. iX Q2

vX

Q1

rπ

(a)

vπ

g vπ m

(b)

Figure 4.44 Solution

We replace the bipolar transistor Q1 with its small-signal model and apply a small-signal voltage across the device [Fig. 4.44(b)]. Noting that rpi carries a current equal to vX /rπ , we write a KCL at the input node: vX + gmvπ = i X . rπ

(4.115)

vX 1 = iX gm + rπ−1

(4.116)

≈

1 gm

(4.117)

=

VT . IC

(4.118)

Since gmrπ = β 1, we have

Interestingly, with a bias current of IC , the device exhibits an impedance similar to that of a diode carrying the same bias current. We call this structure a “diode-connected transistor.” The same results apply to the pnp configuration in Fig. 4.44(a). Exercise

What is the impedance of a diode-connected device operating at a current of 1 mA?

144

Chapter 4 Physics of Bipolar Transistors

Example 4.20

Draw the small-signal equivalent circuits for the topologies shown in Figs. 4.45(a)–(c) and compare the results.

VCC

VCC

RC

VCC v in

Q1

Q1

v in Q 1 v out

RC

v out

v in

(a)

RC

(b)

v out

(c)

RC rπ

v in

vπ

g vπ m

rO

v out

v in

rπ

vπ

g vπ m

r O RC

v out

v in

rπ

vπ

g vπ m

r O RC

v out

v in

rπ

vπ

g vπ m

r O RC

v out

(d)

rπ

vπ

g vπ m

v in

rO RC

v out

(e)

v in

rπ

vπ

g vπ m

rO RC

v out

(f)

Figure 4.45 (a) Simple stage using an npn transistor, (b) simple stage using a pnp transistor, (c) another pnp stage, (d) small-signal equivalent of (a), (e) small-signal equivalent of (b), (f) small-signal equivalent of (f).

Solution

As illustrated in Figs. 4.45(d)–(f), we replace each transistor with its small-signal model and ground the supply voltage. It is seen that all three topologies reduce to the same equivalent circuit because VCC is grounded in the small-signal representation.

Exercise

Repeat the preceding example if a resistor is placed between the collector and base of each transistor.

Problems Example 4.21

145

Draw the small-signal equivalent circuit for the amplifier shown in Fig. 4.46(a). VCC R C1 RC Q1

rπ2

Q2

v in

v in R C2

rπ1

vπ 1

g

vπ 1

m1

g

m2

v π2

r O1 R C2

v out

(a)

Figure 4.46

vπ 2

r O2 v out

(b)

(a) Stage using npn and pnp devices, (b) small-signal equivalent of (a).

Solution

Figure 4.46(b) depicts the equivalent circuit. Note that rO1 , RC 1 , and rπ 2 appear in parallel. Such observations simplify the analysis (Chapter 5).

Exercise

Show that the circuit depicted in Fig. 4.47 has the same small-signal model as the above amplifier. VCC RD R C1

v out Q2

Q1 v in

Figure 4.47

Stage using two npn devices.

PROBLEMS In the following problems, unless otherwise stated, assume the bipolar transistors operate in the active mode. 4.1. Suppose the voltage-dependent current source of Fig. 4.1(a) is constructed with K = 20 mA/V. What value of load resistance in Fig. 4.1(b) is necessary to achieve a voltage gain of 15? 4.2. A resistance of RS is placed in series with the input voltage source in Fig. 4.2. Determine Vout /Vin . 4.3. Due to some fabrication errors, the crosssectional area of emitter has doubled. How does the collector current change?

4.4. In the circuit of Fig. 4.48, IS1 = IS2 = 5 × 10−5 A. (a) Calculate the value of I X if VB = 0.7 V. (b) Find the value of I S to get IY = 3.5 mA. IX Q1

Q2

IY Q3

VB

Figure 4.48

4.5. In the circuit of Fig 4.49, it is required that the collector current of Q2 is to be twice

146

Chapter 4 Physics of Bipolar Transistors that of Q1 if VBE1 − VBE2 = 0 . Determine the ratio of base widths of two transistors, if other device parameters are identical. I C1

I C2 Q1

4.9. Consider the circuit of Fig 4.53. Calculate the value of V CC that places Q1 at the edge of the active region. Assume IS = 5 × 10−16 A.

Q2

V BE1

500 Ω

RC

VCC = 2 V

V BE2

Q1

Figure 4.49

V B = 0.75 V

4.6. Consider the circuit of Fig. 4.50. (a) If VB = 0.6 V and I = 3.5 mA, determine I S1 and I S2 such that I S1 = 2I S2 . (b) Find the value of RC which places the transistors at the edge of the active mode. RC

IX Q1

V CC = 3 V

Q2

Figure 4.53

4.10. An integrated circuit requires two current sources: I1 = 1 mA and I2 = 1.5 mA. Assuming that only integer multiples of a unit bipolar transistor having IS = 3 × 10−16 A can be placed in parallel, and only a single voltage source, VB , is available (Fig. 4.54), construct the required circuit with minimum number of unit transistors.

VB

I1

I2

Figure 4.50

4.7. Consider the circuit of Fig. 4.51. Calculate V X if IS = 6 × 10−15 A. 1 kΩ

VB Unit Transistor

Figure 4.54

Q1 X 1 kΩ

1.5 V

V CC = 2 V

4.11. Consider the circuit of Fig 4.55, assuming β = 100 and IS = 6 × 10−16 A. If RB = 10 k, determine V B such that IC = 1 mA.

Figure 4.51

4.8. In the circuit of Fig 4.52 determine the value of RC and the voltage at V B , if IS = 5 × 10−16 A. RC

1 kΩ

Q1

VCC = 2 V

IC R1 VB

Q1 RE

1 kΩ

Figure 4.55

VB Figure 4.52

4.12. In the circuit of Fig 4.55, if VB = 2 V and RB = 10 k, calculate the collector current.

Problems 4.13. In the circuit depicted in Fig 4.56, if IS1 = 2IS2 = 5 × 10−16 A, β1 = β2 = 100 and R1 = 10 k, compute V B such that IX = 1 mA and IY = 2 mA.

the circuits shown in Fig. 4.58. Assume IS = 8 × 10−16 A, β = 100, and VA = ∞. 10 μ A

V CC = 2 V

V CC = 2 V

Q1

R1

IX

IY Q1

147

Q1

1 kΩ

Q2

1 kΩ

(a)

(b)

VB V CC = 2 V

1 mA

Q1

Figure 4.56

1 mA

V CC = 2 V

Q1

−16

4.14. In the circuit of Fig 4.56, if IS1 = 3 × 10 A and IS2 = 5 × 10−16 A, β1 = β2 = 100 and R1 = 5 k, VB = 800 mV, calculate I X and I Y . 4.15. The base-emitter junction of a transistor is driven by a constant voltage. Suppose a voltage source is applied between the base and collector. If the device operates in the forward active region, what changes will take place in I B and I C ?

(c)

(d)

Figure 4.58

4.20. A fictitious bipolar transistor exhibits an IC -VBE characteristic given by IC = IS exp

VBE , nV T

(4.119)

where n is a constant coefficient. Construct the small-signal model of the device if IC is still equal to βIB .

4.16. In a bipolar device V BE changes by ±10 mV. Calculate the change in gm , if the device is *4.21. A fictitious bipolar transistor exhibits the biased at IC = 2 mA. following relationship between its base and 4.17. A transistor gives a transconductance collector currents: of 1/13 with base-emitter voltage of IC = aI 2B , (4.120) 800 mV. Calculate the value of I S of the transistor. where a is a constant coefficient. Construct 4.18. Determine the operating point the small-signal model of Q1 for of the circuits shown in Fig. Assume IS = 8 × 10−16 A, β = 100, VA = ∞.

and each 4.57. and

4.19. Determine the operating point and the small-signal model of Q1 for each of

RC

50 Ω

Q1

V CC = 2.5 V

the small-signal model of the device if IC is still equal to IS exp (VBE /VT ). 4.22. The collector voltage of a bipolar transistor varies from 1 V to 4 V while the base-emitter voltage remains constant. What Early voltage is necessary to ensure that the collector current changes by less than 2%?

RC

1 kΩ

10 μ A

Q1

V CC = 2.5 V

RC

1 kΩ

Q1

0.8 V (a)

Figure 4.57

(b)

(c)

V CC = 2.5 V

148

Chapter 4 Physics of Bipolar Transistors

4.23. In the circuit of Fig 4.59, IS = 6 × 10−15 A. Determine the value of collector current and V X for (a) VA = ∞ and (b) VA = 4 V.

I1

V CC = 2 V Q1

VB RC

1 kΩ X Q1

VCC = 2.5 V

V B = 0.8 V Figure 4.59

4.24. In the circuit of Fig. 4.60, VCC changes from 2.5 to 3 V. Assuming IS = 1 × 10−17 A and VA = 5 V, determine the change in the collector current of Q1 .

RC

2 kΩ

V CC

Figure 4.62

(a) Assuming VA = ∞, determine VB such that IC = 1 mA. (b) If VA = 5 V, determine VB such that IC = 1 mA for a collector-emitter voltage of 1.5 V. 4.28. Consider the circuit shown in Fig. 4.63, where IS = 6 × 10−16 A and VA = ∞. (a) Determine VB such that Q1 operates at the edge of the active region. (b) If we allow soft saturation, e.g., a collector-base forward bias of 200 mV, by how much can VB increase?

Q1 0.8 V

RC

Figure 4.60

4.25. In the circuit of Fig. 4.61, n identical transistors are placed in parallel. If IS = 5 × 10−16 A and VA = 8 V for each device, construct the small-signal model of the equivalent transistor.

2 kΩ

V CC = 2.5 V

Q1 VB

Figure 4.63

4.29. For the circuit depicted in Fig. 4.64, calculate the value of collector-base bias, if IS = 7 × 10−16 A and VA = ∞.

V B = 0.8 V

Figure 4.61

4.26. A bipolar current source is to be designed for a specific output current. If VA = 2 V and output resistance is greater than 10 k, find the output current. *4.27. Consider the circuit shown in Fig. 4.62, where I1 is a 1-mA ideal current source and IS = 3 × 10−17 A.

RC

1 kΩ

V CC

Q1 Figure 4.64

4.30. Consider the circuit shown in Fig. 4.65, where IS = 5 × 10−16 A and VA = ∞. If VB is chosen to forward-bias the base-collector junction by 200 mV, what is the collector current?

Problems

149

23 kΩ Q1 VB

V CC = 2.5 V

Q1

RB

IC

1 kΩ

V CC

1.5 V

Figure 4.69 Figure 4.65

* 4.31. Assume IS = 2 × 10−17 A, VA = ∞, and β = 100 in Fig. 4.66. What is the maximum value of RC if the collector-base must experience a forward bias of less than 200 mV? 100 k Ω

RB

RC

4.35. Determine the collector current of Q1 in Fig. 4.70 if IS = 2 × 10−17 A and β = 100. 50 k Ω

Q1

RB 1.7 V

4.36. Determine the value of IS in Fig. 4.71 such that Q1 operates at the edge of the active mode.

Figure 4.66

Q1

4.32. In the circuit of Fig. 4.67, β = 100 and VA = ∞. Calculate the value of IS such that the base-collector junction is forwardbiased by 200 mV. 9 kΩ

Rp

1 kΩ

2V

Figure 4.70 V CC = 2.5 V

Q1

RC

V CC

IC

V B = 1.2 V

V CC

2V

2 kΩ

RC

Figure 4.71

4.37. What is the value of β that places Q1 at the edge of the active mode in Fig. 4.72? Assume IS = 8 × 10−16 A.

V CC = 2.5 V

100 k Ω

RB

Q1

Q1

V CC

1.5 V

1 kΩ

Figure 4.67

4.33. If IS1 = 3 IS2 = 6 × 10−16 A, calculate the value of V B in Fig. 4.68, required for getting IX = 10 mA.

Figure 4.72

4.38. Calculate the collector current of Q1 in Fig 4.73, if IS = 3 × 10−17 A. V CC

0.82 V

Q1 VB

Q2

V CC

2.5 V

Q1 2V

1.8 V

1 kΩ

IX Figure 4.73

Figure 4.68

*4.39. Determine the operating point small-signal model of Q1 for 4.34. In the circuit of Fig. 4.69, calculate the value the circuits shown in Fig. 4.74. of I C , if β = 100 and IS = 6 × 10−16 A. IS = 3 × 10−17 A, β = 100, and VA

and the each of Assume = ∞.

150

Chapter 4 Physics of Bipolar Transistors

Q1 1.7 V

Q1

V CC

2.5 V

1 kΩ

20 μ A

(a)

V CC

Q1 2.5 V

500 Ω

V CC

2.5 V

2 kΩ

(b)

(c)

Figure 4.74

4.40. In the circuit of Fig. 4.75, IS = 5 × 10−17 A. * 4.43. Suppose VA = 5 V in the circuit of Fig. 4.77. Calculate VX for (a) VA = ∞, and (b) VA = 6 V. Q1 Q1 1.7 V

X

1.7 V

V CC

X

2.5 V

V CC

2.5 V

3 kΩ

500 Ω

Figure 4.77 Figure 4.75

*4.41. Determine the operating point small-signal model of Q1 for the circuits shown in Fig. 4.76. IS = 3 × 10−17 A, β = 100, and VA 2 kΩ

V CC

and the each of Assume = ∞.

2.5 V

(a) What value of IS places Q1 at the edge of the active mode? (b) How does the result in (a) change if VA = ∞? *4.44. Consider the circuit depicted in Fig. 4.78, where IS = 6 × 10−16 A, VA = 5 V, and I1 = 2 mA.

Q1 2 μA

VB

(a)

Q1 X

V CC

2.5 V

I1

5 kΩ

V CC

2.5 V

Q1

Figure 4.78

(b)

0.5 mA

V CC

2.5 V

Q1

(c)

Figure 4.76

4.42. A pnp current source must provide an output current of 5 mA with an Early voltage of 2 V. What is the output impedance?

(a) What value of VB yields VX = 1 V? (b) If VB changes from the value found in (a) by 0.1 mV, what is the change in VX ? (c) Construct the small-signal model of the transistor. 4.45. In the circuit in Fig 4.79, β = 100, and VA = ∞. (a) Determine the value of collector-base forward bias if IS = 5 × 10−16 A and V BE of 0.8 V. (b) Calculate the transconductance of the device.

Spice Problems

Q1

RB

IS = 5 × 10−16 A,

Assume VA = ∞.

360 kΩ V CC

2.5 V

151

β = 100,

4.47. Consider the circuit of Fig 4.81 where IS1 = IS2 = 5 × 10−16 A, IC 2 = 0.5 mA, β1 = 100, β2 = 50, VA = ∞ , and RC = 500 . If Vin = 1.45 V, what is the value of VBE1 and VBE2 ?

4 kΩ Figure 4.79

**4.46. Determine the region of operation of Q1 ** 4.48. Repeat Problem 4.47 for the circuit illustrated in Fig. 4.82. in each of the circuits shown in Fig. 4.80. RE

RB

RE Q1

Q1

V CC

Q1

V CC

2.5 V

RC

300 Ω

2.5 V

RC

(a)

V CC

2.5 V

1 kΩ

(b)

(c)

RE 0.5 mA

Q1

V CC

2.5 V

V CC

2.5 V

Q1

RC

500 Ω (d)

(e)

Figure 4.80

Q1

V CC = 2.5 V

V in

V CC = 2.5 V

RC

Q2 RC Figure 4.81

Vout

Q1

Vout V in

Q2

Figure 4.82

SPICE PROBLEMS In the following problems, assume IS,npn = 5 × 10−16 A, βnpn = 100, VA,npn = 5 V, IS,pnp = 8 × 10−16 A, βpnp = 50, VA,pnp = 3.5 V.

4.1. Plot the input/output characteristic of the circuit shown in Fig. 4.83 for 0 < Vin < 2.5 V. What value of Vin places the transistor at the edge of saturation?

152

Chapter 4 Physics of Bipolar Transistors 1 kΩ

RC

V CC = 2.5 V

Vout

V CC = 2.5 V

V in

Q1

Q1

1 kΩ

V B = 0.9 V

Vout

V in

Figure 4.84 Figure 4.83

4.2. Repeat Problem 4.1 for the stage depicted in Fig. 4.84. At what value of Vin does Q1 carry a collector current of 1 mA?

4.3. Plot IC 1 and IC 2 as a function of Vin for the circuits shown in Fig. 4.85 for0 < Vin < 1.8 V. Explain the dramatic difference between the two.

I C2 I C1 V in

V CC = 2.5 V

V in

Q2

Q1 Q3

(a)

Figure 4.85

(b)

V CC = 2.5 V

Chapter

5

Bipolar Amplifiers

With the physics and operation of bipolar transistors described in Chapter 4, we now deal with amplifier circuits employing such devices. While the field of microelectronics involves much more than amplifiers, our study of cellphones and digital cameras in Chapter 1 indicates the extremely wide usage of amplification, motivating us to master the analysis and design of such building blocks. This chapter proceeds as follows.

General Concepts

Operating Point Analysis

Amplifier Topologies

• Simple Biasing

• Common–Emitter Stage

• Biasing

• Self-Biasing

• Common–Base Stage

• DC and Small–Signal Analysis

• Biasing of PNP Devices

• Emitter Follower

• Input and Output Impedances

➤ • Emitter Degeneration ➤

Building the foundation for the remainder of this book, this chapter is quite long. Most of the concepts introduced here are invoked again in Chapter 7 (MOS amplifiers). The reader is therefore encouraged to take frequent breaks and absorb the material in small doses.

5.1

GENERAL CONSIDERATIONS Recall from Chapter 4 that a voltage-controlled current source along with a load resistor can form an amplifier. In general, an amplifier produces an output (voltage or current) that is a magnified version of the input (voltage or current). Since most electronic circuits both sense and produce voltage quantities,1 our discussion primarily centers around “voltage amplifiers” and the concept of “voltage gain,” vout /vin . What other aspects of an amplifier’s performance are important? Three parameters that readily come to mind are (1) power dissipation (e.g., because it determines the battery lifetime in a cellphone or a digital camera); (2) speed (e.g., some amplifiers in a cellphone or analog-to-digital converters in a digital camera must operate at high frequencies);

1

Exceptions are described in Chapter 12.

153

154

Chapter 5 Bipolar Amplifiers (3) noise (e.g., the front-end amplifier in a cellphone or a digital camera processes small signals and must introduce negligible noise of its own).

5.1.1 Input and Output Impedances In addition to the above parameters, the input and output (I/O) impedances of an amplifier play a critical role in its capability to interface with preceding and following stages. To understand this concept, let us first determine the I/O impedances of an ideal voltage amplifier. At the input, the circuit must operate as a voltmeter, i.e., sense a voltage without disturbing (loading) the preceding stage. The ideal input impedance is therefore infinite. At the output, the circuit must behave as a voltage source, i.e., deliver a constant signal level to any load impedance. Thus, the ideal output impedance is equal to zero. In reality, the I/O impedances of a voltage amplifier may considerably depart from the ideal values, requiring attention to the interface with other stages. The following example illustrates the issue.

Example 5.1

An amplifier with a voltage gain of 10 senses a signal generated by a microphone and applies the amplified output to a speaker [Fig. 5.1(a)]. Assume the microphone can be modeled with a voltage source having a 10-mV peak-to-peak signal and a series resistance of 200 . Also assume the speaker can be represented by an 8- resistor.

Microphone Amplifier Speaker

A v = 10 200 Ω 10 mV

Rm

vm

8Ω

(a)

200 Ω vm

Rm

v1

R amp R in

(b)

v amp

RL

8 Ω v out

(c)

(a) Simple audio system, (b) signal loss due to amplifier input impedance, (c) signal loss due to amplifier output impedance.

Figure 5.1

5.1 General Considerations

155

(a) Determine the signal level sensed by the amplifier if the circuit has an input impedance of 2 k or 500 . (b) Determine the signal level delivered to the speaker if the circuit has an output impedance of 10 or 2 . Solution

(a) Figure 5.1(b) shows the interface between the microphone and the amplifier. The voltage sensed by the amplifier is therefore given by v1 =

Rin vm . Rin + Rm

(5.1)

For Rin = 2 k, v1 = 0.91vm,

(5.2)

only 9% less than the microphone signal level. On the other hand, for Rin = 500 , v1 = 0.71vm,

(5.3)

i.e., nearly 30% loss. It is therefore desirable to maximize the input impedance in this case. (b) Drawing the interface between the amplifier and the speaker as in Fig. 5.1(c), we have RL vout = vamp . (5.4) RL + Ramp For Ramp = 10 , vout = 0.44vamp ,

(5.5)

a substantial attenuation. For Ramp = 2 , vout = 0.8vamp .

(5.6)

Thus, the output impedance of the amplifier must be minimized. Exercise

If the signal delivered to the speaker is equal to 0.2vm, find the ratio of Rm and RL .

The importance of I/O impedances encourages us to carefully prescribe the method of measuring them. As with the impedance of two-terminal devices such as resistors and capacitors, the input (output) impedance is measured between the input (output) nodes of the circuit while all independent sources in the circuit are set to zero.2 Illustrated in Fig. 5.2, the method involves applying a voltage source to the two nodes (also called “ports”) of interest, measuring the resulting current, and defining vX /i X as the impedance. Also shown are arrows to denote “looking into” the input or output port and the corresponding impedance. The reader may wonder why the output port in Fig. 5.2(a) is left open whereas the input port in Fig. 5.2(b) is shorted. Since a voltage amplifier is driven by a voltage source during normal operation, and since all independent sources must be set to zero, the input 2

Recall that a zero voltage source is replaced by a short and a zero current source by an open.

156

Chapter 5 Bipolar Amplifiers Input Port

iX

Output Port iX

vx

vX

Short

R in

R out (a)

Figure 5.2

(b)

Measurement of (a) input and (b) output impedances.

port in Fig. 5.2(b) must be shorted to represent a zero voltage source. That is, the procedure for calculating the output impedance is identical to that used for obtaining the Thevenin impedance of a circuit (Chapter 1). In Fig. 5.2(a), on the other hand, the output remains open because it is not connected to any external sources. Determining the transfer of signals from one stage to the next, the I/O impedances are usually regarded as small-signal quantities—with the tacit assumption that the signal levels are indeed small. For example, the input impedance is obtained by applying a small change in the input voltage and measuring the resulting change in the input current. The small-signal models of semiconductor devices therefore prove crucial here.

Example 5.2

Assuming that the transistor operates in the forward active region, determine the input impedance of the circuit shown in Fig. 5.3(a).

VCC RC v in

Q1

(a)

Figure 5.3 Solution

RC

iX vX

rπ

vπ

g vπ m

rO

(b)

(a) Simple amplifier stage, (b) small-signal model.

Constructing the small-signal equivalent circuit depicted in Fig. 5.3(b), we note that the input impedance is simply given by vx = rπ . (5.7) ix Since rπ = β/gm = βVT /IC , we conclude that a higher β or lower IC yield a higher input impedance.

Exercise

What happens if RC is doubled?

5.1 General Considerations

157

Short R in

R out

(a) Figure 5.4

(b)

Concept of impedance seen at a node.

To simplify the notations and diagrams, we often refer to the impedance seen at a node rather than between two nodes (i.e., at a port). As illustrated in Fig. 5.4, such a convention simply assumes that the other node is the ground, i.e., the test voltage source is applied between the node of interest and ground.

Example 5.3

Calculate the impedance seen looking into the collector of Q 1 in Fig. 5.5(a).

v in

rπ

Q 1 R out

(a) Figure 5.5

g vπ m

vπ

rO

R out

(b)

(a) Impedance seen at collector, (b) small-signal model.

Solution

Setting the input voltage to zero and using the small-signal model in Fig. 5.5(b), we note that vπ = 0, gmvπ = 0, and hence Rout = rO .

Exercise

What happens if a resistance of value R1 is placed in series with the base?

Example 5.4

Calculate the impedance seen at the emitter of Q 1 in Fig. 5.6(a). Neglect the Early effect for simplicity. VCC v in

rπ

Q1

g vπ m

vπ

vπ rπ

iX

R out

(a)

Figure 5.6

vX

(b)

(a) Impedance seen at emitter, (b) small-signal model.

158

Chapter 5 Bipolar Amplifiers

Solution

Setting the input voltage to zero and replacing VCC with ac ground, we arrive at the small-signal circuit shown in Fig. 5.6(b). Interestingly, vπ = −vX and gmvπ +

vπ = −i X . rπ

(5.8)

That is, vX = iX

1 gm +

1 rπ

.

(5.9)

Since rπ = β/gm 1/gm, we have Rout ≈ 1/gm. Exercise

What happens if a resistance of value R1 is placed in series with the collector?

The above three examples provide three important rules that will be used throughout this book (Fig. 5.7): Looking into the base, we see rπ if the emitter is (ac) grounded. Looking into the collector, we see rO if the emitter is (ac) grounded. Looking into the emitter, we see 1/gm if the base is (ac) grounded and the Early effect is neglected. It is imperative that the reader master these rules and be able to apply them in more complex circuits.3 rO

VA = rπ

Figure 5.7

ac

ac

ac

ac

1 gm

Summary of impedances seen at terminals of a transistor.

5.1.2 Biasing Recall from Chapter 4 that a bipolar transistor operates as an amplifying device if it is biased in the active mode; that is, in the absence of signals, the environment surrounding the device must ensure that the base-emitter and base-collector junctions are forward- and reverse-biased, respectively. Moreover, as explained in Section 4.4, amplification properties of the transistor such as gm, rπ , and rO depend on the quiescent (bias) collector current. Thus, the surrounding circuitry must also set (define) the device bias currents properly. 5.1.3 DC and Small-Signal Analysis The foregoing observations lead to a procedure for the analysis of amplifiers (and many other circuits). First, we compute the operating (quiescent) conditions (terminal voltages and currents) of each transistor in the absence of signals. Called the “dc analysis” or “bias 3 While beyond the scope of this book, it can be shown that the impedance seen at the emitter is approximately equal to 1/gm only if the collector is tied to a relatively low impedance.

5.1 General Considerations V BE

159

Bias (dc) Value

t IC

Bias (dc) Value

t

Figure 5.8

Bias and signal levels for a bipolar transistor.

analysis,” this step determines both the region of operation (active or saturation) and the small-signal parameters of each device. Second, we perform “small-signal analysis,” i.e., study the response of the circuit to small signals and compute quantities such as the voltage gain and I/O impedances. As an example, Fig. 5.8 illustrates the bias and signal components of a voltage and a current. It is important to bear in mind that small-signal analysis deals with only (small) changes in voltages and currents in a circuit around their quiescent values. Thus, as mentioned in Section 4.4.4, all constant sources, i.e., voltage and current sources that do not vary with time, must be set to zero for small-signal analysis. For example, the supply voltage is constant and, while establishing proper bias points, plays no role in the response to small signals. We therefore ground all constant voltage sources4 and open all constant current sources while constructing the small-signal equivalent circuit. From another point of view, the two steps described above follow the superposition principle: first, we determine the effect of constant voltages and currents while signal sources are set to zero, and second, we analyze the response to signal sources while constant sources are set to zero. Figure 5.9 summarizes these concepts. DC Analysis

Small-Signal Analysis

VCC R C1 V CB

I C1

I C2

v in

v out

Open

V BE

Figure 5.9

Short

Steps in a general circuit analysis.

We should remark that the design of amplifiers follows a similar procedure. First, the circuitry around the transistor is designed to establish proper bias conditions and hence the necessary small-signal parameters. Second, the small-signal behavior of the circuit is studied to verify the required performance. Some iteration between the two steps may often be necessary so as to converge toward the desired behavior. How do we differentiate between small-signal and large-signal operations? In other words, under what conditions can we represent the devices with their small-signal models? 4

We say all constant voltage sources are replaced by an “ac ground.”

160

Chapter 5 Bipolar Amplifiers If the signal perturbs the bias point of the device only negligibly, we say the circuit operates in the small-signal regime. In Fig. 5.8, for example, the change in IC due to the signal must remain small. This criterion is justified because the amplifying properties of the transistor such as gm and rπ are considered constant in small-signal analysis even though they in fact vary as the signal perturbs IC . That is, a linear representation of the transistor holds only if the small-signal parameters themselves vary negligibly. The definition of “negligibly” depends somewhat on the circuit and the application, but as a rule of thumb, we consider 10% variation in the collector current as the upper bound for small-signal operation. In drawing circuit diagrams hereafter, we will employ some simplified notations and symbols. Illustrated in Fig. 5.10 is an example where the battery serving as the supply voltage is replaced with a horizontal bar labeled VCC .5 Also, the input voltage source is simplified to one node called Vin , with the understanding that the other node is ground. VCC RC

RC

VCC

Q1 V in

Figure 5.10

Vout V in

Vout

Q1

Notation for supply voltage.

In this chapter, we begin with the DC analysis and design of bipolar stages, developing skills to determine or create bias conditions. This phase of our study requires no knowledge of signals and hence the input and output ports of the circuit. Next, we introduce various amplifier topologies and examine their small-signal behavior.

5.2

OPERATING POINT ANALYSIS AND DESIGN It is instructive to begin our treatment of operating points with an example.

Example 5.5

A student familiar with bipolar devices constructs the circuit shown in Fig. 5.11 and attempts to amplify the signal produced by a microphone. If IS = 6 × 10−16 A and the peak value of the microphone signal is 20 mV, determine the peak value of the output signal. VCC RC

1 kΩ

Vout Q1 Vin

Figure 5.11

5

Amplifier driven directly by a microphone.

The subscript CC indicates supply voltage feeding the collector.

5.2 Operating Point Analysis and Design Solution

161

Unfortunately, the student has forgotten to bias the transistor. (The microphone does not produce a dc output.) If Vin (= VBE ) reaches 20 mV, then IC = IS exp

VBE VT

= 1.29 × 10−15 A.

(5.10) (5.11)

This change in the collector current yields a change in the output voltage equal to RC IC = 1.29 × 10−12 V.

(5.12)

The circuit generates virtually no output because the bias current (in the absence of the microphone signal) is zero and so is the transconductance. Exercise

Repeat the above example if a constant voltage of 0.65 V is placed in series with the microphone.

As mentioned in Section 5.1.2, biasing seeks to fulfill two objectives: ensure operation in the forward active region, and set the collector current to the value required in the application. Let us return to the above example for a moment.

Example 5.6

Having realized the bias problem, the student in Example 5.5 modifies the circuit as shown in Fig. 5.12, connecting the base to VCC to allow dc biasing for the base-emitter junction. Explain why the student needs to learn more about biasing.

VCC = 2.5 V RC

1 kΩ

Vout Q1

Figure 5.12

Amplifier with base tied to VCC .

Solution

The fundamental issue here is that the signal generated by the microphone is shorted to VCC . Acting as an ideal voltage source, VCC maintains the base voltage at a constant value, prohibiting any change introduced by the microphone. Since VBE remains constant, so does Vout , leading to no amplification. Another important issue relates to the value of VBE : with VBE = VCC = 2.5 V, enormous currents flow into the transistor.

Exercise

Does the circuit operate better if a resistor is placed in series with the emitter of Q 1 ?

162

Chapter 5 Bipolar Amplifiers VCC RB

RC Y X

Q1

IB

Figure 5.13

IC

Use of base resistance for base current path.

5.2.1 Simple Biasing Now consider the topology shown in Fig. 5.13, where the base is tied to VCC through a relatively large resistor, RB , so as to forward-bias the base-emitter junction. Our objective is to determine the terminal voltages and currents of Q 1 and obtain the conditions that ensure biasing in the active mode. How do we analyze this circuit? One can replace Q 1 with its large-signal model and apply KVL and KCL, but the resulting nonlinear equation(s) yield little intuition. Instead, we recall that the baseemitter voltage in most cases falls in the range of 700 to 800 mV and can be considered relatively constant. Since the voltage drop across RB is equal to RB IB , we have RB IB + VBE = VCC

(5.13)

and hence IB =

VCC − VBE . RB

(5.14)

VCC − VBE , RB

(5.15)

With the base current known, we write IC = β

note that the voltage drop across RC is equal to RC IC , and hence obtain VCE as VCE = VCC − RC IC = VCC − β

VCC − VBE RC . RB

(5.16) (5.17)

Calculation of VCE is necessary as it reveals whether the device operates in the active mode or not. For example, to avoid saturation completely, we require the collector voltage to remain above the base voltage: VCC − β

VCC − VBE RC > VBE . RB

(5.18)

The circuit parameters can therefore be chosen so as to guarantee this condition. In summary, using the sequence IB → IC → VCE , we have computed the important terminal currents and voltages of Q 1 . While not particularly interesting here, the emitter current is simply equal to IC + IB . The reader may wonder about the error in the above calculations due to the assumption of a constant VBE in the range of 700 to 800 mV. An example clarifies this issue.

5.2 Operating Point Analysis and Design Example 5.7

163

For the circuit shown in Fig. 5.14, determine the collector bias current. Assume β = 100 and IS = 10−17 A. Verify that Q 1 operates in the forward active region.

Solution

VCC = 2.5 V 100 k Ω

1 kΩ

RC

RB

Y X IB

Figure 5.14

IC Q1

Simple biased stage.

Since IS is relatively small, we surmise that the base-emitter voltage required to carry typical current level is relatively large. Thus, we use VBE = 800 mV as an initial guess and write Eq. (5.14) as IB =

VCC − VBE RB

≈ 17 μA.

(5.19) (5.20)

It follows that IC = 1.7 mA.

(5.21)

With this result for IC , we calculate a new value for VBE : VBE = VT ln

IC IS

= 852 mV,

(5.22) (5.23)

and iterate to obtain more accurate results. That is, IB =

VCC − VBE RB

(5.24)

= 16.5 μA

(5.25)

IC = 1.65 mA.

(5.26)

and hence Since the values given by (5.21) and (5.26) are quite close, we consider IC = 1.65 mA accurate enough and iterate no more. Writing (5.16), we have VCE = VCC − RC IC

(5.27)

= 0.85 V,

(5.28)

a value nearly equal to VBE . The transistor therefore operates near the edge of active and saturation modes. Exercise

What value of RB provides a reverse bias of 200 mV across the base-collector junction?

164

Chapter 5 Bipolar Amplifiers The biasing scheme of Fig. 5.13 merits a few remarks. First, the effect of VBE “uncertainty” becomes more pronounced at low values of VCC because VCC − VBE determines the base current. Thus, in low-voltage design—an increasingly common paradigm in modern electronic systems—the bias is more sensitive to VBE variations among transistors or with temperature. Second, we recognize from Eq. (5.15) that IC heavily depends on β, a parameter that may change considerably. In the above example, if β increases from 100 to 120, then IC rises to 1.98 mA and VCE falls to 0.52, driving the transistor toward heavy saturation. For these reasons, the topology of Fig. 5.13 is rarely used in practice. 5.2.2 Resistive Divider Biasing In order to suppress the dependence of IC upon β, we return to the fundamental relationship IC = IS exp(VBE /VT ) and postulate that IC must be set by applying a well-defined VBE . Figure 5.15 depicts an example, where R1 and R2 act as a voltage divider, providing a base-emitter voltage equal to R2 VCC , R1 + R 2

VX = if the base current is negligible. Thus,

IC = IS exp

R2 VCC , · R1 + R2 VT

(5.29)

(5.30)

a quantity independent of β. Nonetheless, the design must ensure that the base current remains negligible. VCC R1

RC Y X

IC Q1

R2

Figure 5.15

Example 5.8

Use of resistive divider to define VBE .

Determine the collector current of Q 1 in Fig. 5.16 if IS = 10−17 A and β = 100. Verify that the base current is negligible and the transistor operates in the active mode. VCC = 2.5 V 17 k Ω

RC

R1

Y X 8 kΩ

Figure 5.16

Example of biased stage.

R2

5 kΩ

IC Q1

5.2 Operating Point Analysis and Design Solution

165

Neglecting the base current of Q 1 , we have VX =

R2 VCC R1 + R 2

(5.31)

= 800 mV.

(5.32)

It follows that IC = IS exp

VBE VT

(5.33)

= 231 μA

(5.34)

IB = 2.31 μA.

(5.35)

and

Is the base current negligible? With which quantity should this value be compared? Provided by the resistive divider, IB must be negligible with respect to the current flowing through R1 and R2 : ?

IB This condition indeed 100 μA ≈ 43IB . We also note that

holds

in

VCC . R1 + R 2

this

example

(5.36) because

VCC /(R1 + R2 ) =

VCE = 1.345 V,

(5.37)

and hence Q 1 operates in the active region. Exercise

What is the maximum value of RC if Q 1 must remain in soft saturation?

The analysis approach taken in the above example assumes a negligible base current, requiring verification at the end. But what if the end result indicates that IB is not negligible? We now analyze the circuit without this assumption. Let us replace the voltage divider with a Thevenin equivalent (Fig. 5.17), noting that VThev is equal to the open-circuit output voltage (VX when the amplifier is disconnected): VThev =

R2 VCC . R1 + R 2

(5.38)

Moreover, RThev is given by the output resistance of the network if VCC is set to zero: RThev = R1 ||R2 .

(5.39)

VX = VThev − IB RThev

(5.40)

The simplified circuit yields:

and IC = IS exp

VThev − IB RThev . VT

(5.41)

This result along with IC = βIB forms the system of equations leading to the values of IC and IB . As in the previous examples, iterations prove useful here, but the exponential

166

Chapter 5 Bipolar Amplifiers VCC

VCC

R1

RC

RC

R2

IC X

VCC

R1

R Thev X

Q1 V Thev

R2

IB

IC Q1

R1 VCC

Figure 5.17

R2

VThev

Use of Thevenin equivalent to calculate bias.

dependence in Eq. (5.41) gives rise to wide fluctuations in the intermediate solutions. For this reason, we rewrite Eq. (5.41) as 1 IC · , (5.42) IB = VThev − VT ln IS RThev and begin with a guess for VBE = VT ln(IC /IS ). The iteration then follows the sequence VBE → IB → IC → VBE → · · ·. Example 5.9

Calculate the collector current of Q 1 in Fig. 5.18(a). Assume β = 100 and IS = 10−17 A.

Solution

Constructing the equivalent circuit shown in Fig. 5.18(b), we note that VThev =

R2 VCC R1 + R 2

(5.43)

= 800 mV

(5.44)

RThev = R1 ||R2

(5.45)

and

= 54.4 k.

(5.46)

VCC = 2.5 V 170 k Ω

R1

RC Y

X 80 k Ω

R2

IB

VCC

5 kΩ

RC

IC

R Thev X

Q1 V Thev

IB

IC Q1

Figure 5.18 (a) Stage with resistive divider bias, (b) stage with Thevenin equivalent for the resistive divider and VCC .

5.2 Operating Point Analysis and Design

167

We begin the iteration with an initial guess VBE = 750 mV (because we know that the voltage drop across RThev makes VBE less than VThev ), thereby arriving at the base current: IB =

VThev − VBE RThev

(5.47)

= 0.919 μA.

(5.48)

IC IS

(5.49)

Thus, IC = βIB = 91.9 μA and VBE = VT ln

= 776 mV.

(5.50)

It follows that IB = 0.441 μA and hence IC = 44.1 μA, still a large fluctuation with respect to the first value from above. Continuing the iteration, we obtain VBE = 757 mV, IB = 0.79 μA and IC = 79.0 μA. After many iterations, VBE ≈ 766 mV and IC = 63 μA. Exercise

How much can R2 be increased if Q 1 must remain in soft saturation?

While proper choice of R1 and R2 in the topology of Fig. 5.15 makes the bias relatively insensitive to β, the exponential dependence of IC upon the voltage generated by the resistive divider still leads to substantial bias variations. For example, if R2 is 1% higher than its nominal value, so is VX , thus multiplying the collector current by exp(0.01VBE /VT ) ≈ 1.36 (for VBE = 800 mV). In other words, a 1% error in one resistor value introduces a 36% error in the collector current. The circuit is therefore still of little practical value. 5.2.3 Biasing with Emitter Degeneration A biasing configuration that alleviates the problem of sensitivity to β and VBE is shown in Fig. 5.19. Here, resistor RE appears in series with the emitter, thereby lowering the sensitivity to VBE . From an intuitive viewpoint, this occurs because RE exhibits a linear (rather than exponential) I-V relationship. Thus, an error in VX due to inaccuracies in R1 , R2 , or VCC is partly “absorbed” by RE , introducing a smaller error in VBE and hence IC . Called “emitter degeneration,” the addition of RE in series with the emitter alters many attributes of the circuit, as described later in this chapter. VCC R1

RC Y X

R2

IC Q1

P

IE RE

Figure 5.19

Addition of degeneration resistor to stabilize bias point.

168

Chapter 5 Bipolar Amplifiers To understand the above property, let us determine the bias currents of the transistor. Neglecting the base current, we have VX = VCC R2 /(R1 + R2 ). Also, VP = VX − VBE , yielding IE = =

VP RE

(5.51)

R2 1 VCC − VBE RE R1 + R 2

(5.52)

≈ IC ,

(5.53)

if β 1. How can this result be made less sensitive to VX or VBE variations? If the voltage drop across RE , i.e., the difference between VCC R2 /(R1 + R2 ) and VBE , is large enough to absorb and swamp such variations, then IE and IC remain relatively constant. An example illustrates this point.

Example 5.10

Calculate the bias currents in the circuit of Fig. 5.20 and verify that Q 1 operates in the forward active region. Assume β = 100 and IS = 5 × 10−17 A. How much does the collector current change if R2 is 1% higher than its nominal value? VCC = 2.5 V 16 k Ω

1 kΩ

RC

R1

Y X 9 kΩ

Q1 P

R2

RE

Figure 5.20 Solution

100 Ω

Example of biased stage.

We neglect the base current and write VX = VCC

R2 R1 + R 2

= 900 mV.

(5.54) (5.55)

Using VBE = 800 mV as an initial guess, we have VP = VX − VBE = 100 mV,

(5.56) (5.57)

and hence IE ≈ IC ≈ 1 mA.

(5.58)

5.2 Operating Point Analysis and Design

169

With this result, we must reexamine the assumption of VBE = 800 mV. Since VBE = VT ln

IC IS

= 796 mV,

(5.59) (5.60)

we conclude that the initial guess is reasonable. Furthermore, Eq. (5.57) suggests that a 4-mV error in VBE leads to a 4% error in VP and hence IE , indicating a good approximation. Let us now determine if Q 1 operates in the active mode. The collector voltage is given by VY = VCC − IC RC = 1.5 V.

(5.61) (5.62)

With the base voltage at 0.9 V, the device is indeed in the active region. Is the assumption of negligible base current valid? With IC ≈ 1 mA, IB ≈ 10 μA whereas the current flowing through R1 and R2 is equal to 100 μA. The assumption is therefore reasonable. For greater accuracy, an iterative procedure similar to that in Example 5.9 can be followed. If R2 is 1.6% higher than its nominal value, then Eq. (5.54) indicates that VX rises to approximately 909 mV. We may assume that the 9-mV change directly appears across RE , raising the emitter current by 9 mV/100 = 90 μA. From Eq. (5.56), we note that this assumption is equivalent to considering VBE constant, which is reasonable because the emitter and collector currents have changed by only 9%. Exercise

What value of R2 places Q 1 at the edge of saturation?

The bias topology of Fig. 5.19 is used extensively in discrete circuits and occasionally in integrated circuits. Illustrated in Fig. 5.21, two rules are typically followed: (1) I1 IB to lower sensitivity to β, and (2) VRE must be large enough (100 mV to several hundred millivolts) to suppress the effect of uncertainties in VX and VBE . VCC R1 Y

I1 I 1 >> I B R2

X IB RE

Figure 5.21

R C Small Enough to Avoid Saturation IC Q1 VRE >> Variations in VX and VBE

Summary of robust bias conditions.

Design Procedure It is possible to prescribe a design procedure for the bias topology of Fig. 5.21 that serves most applications: (1) decide on a collector bias current that yields proper small-signal parameters such as gm and rπ ; (2) based on the expected variations of

170

Chapter 5 Bipolar Amplifiers R1 , R2 , and VBE , choose a value for VRE ≈ IC RE , e.g., 200 mV; (3) calculate VX = VBE + IC RE with VBE = VT ln(IC /IS ); (4) choose R1 and R2 so as to provide the necessary value of VX and establish I1 IB . Determined by small-signal gain requirements, the value of RC is bounded by a maximum that places Q 1 at the edge of saturation. The following example illustrates these concepts.

Example 5.11

Solution

Design the circuit of Fig. 5.21 so as to provide a transconductance of 1/(52 ) for Q 1 . Assume VCC = 2.5 V, β = 100, and IS = 5 × 10−17 A. What is the maximum tolerable value of RC ? A gm of (52 )−1 translates to a collector current of 0.5 mA and a VBE of 778 mV. Assuming RE IC = 200 mV, we obtain RE = 400 . To establish VX = VBE + RE IC = 978 mV, we must have R2 VCC = VBE + RE IC , R1 + R 2

(5.63)

where the base current is neglected. For the base current IB = 5 μA to be negligible, VCC IB , R1 + R 2

(5.64)

e.g., by a factor of 10. Thus, R1 + R2 = 50 k, which in conjunction with Eq. (5.63) yields R1 = 30.45 k

(5.65)

R2 = 19.55 k.

(5.66)

How large can RC be? Since the collector voltage is equal to VCC − RC IC , we pose the following constraint to ensure active mode operation: VCC − RC IC >VX ;

(5.67)

RC IC < 1.522 V.

(5.68)

RC < 3.044 k.

(5.69)

that is,

Consequently,

If RC exceeds this value, the collector voltage falls below the base voltage. As mentioned in Chapter 4, the transistor can tolerate soft saturation, i.e., up to about 400 mV of base-collector forward bias. Thus, in low-voltage applications, we may allow VY ≈ VX − 400 mV and hence a greater value for RC . Exercise

Repeat the above example if the power budget is only 1 mW and the transconductance of Q 1 is not given.

5.2 Operating Point Analysis and Design

171

The two rules depicted in Fig. 5.21 to lower sensitivities do impose some trade-offs. Specifically, an overly conservative design faces the following issues: (1) if we wish I1 to be much much greater than IB , then R1 + R2 and hence R1 and R2 are quite small, leading to a low input impedance; (2) if we choose a very large VRE , then VX ( = VBE + VRE ) must be high, thereby limiting the minimum value of the collector voltage to avoid saturation. Let us return to the above example and study these issues.

Example 5.12

Repeat Example 5.11 but assuming VRE = 500 mV and I1 ≥ 100IB .

Solution

The collector current and base-emitter voltage remain unchanged. The value of RE is now given by 500 mV/0.5 mA = 1 k. Also, VX = VBE + RE IC = 1.278 V and Eq. (5.63) still holds. We rewrite Eq. (5.64) as VCC ≥ 100IB , R1 + R 2

(5.70)

obtaining R1 + R2 = 5 k. It follows that R1 = 1.45 k

(5.71)

R2 = 3.55 k.

(5.72)

Since the base voltage has risen to 1.278 V, the collector voltage must exceed this value to avoid saturation, leading to VCC − VX IC

(5.73)

< 1.044 k.

(5.74)

RC <

As seen in Section 5.3.1, the reduction in RC translates to a lower voltage gain. Also, the much smaller values of R1 and R2 here than in Example 5.11 introduce a low input impedance, loading the preceding stage. We compute the exact input impedance of this circuit in Section 5.3.1. Exercise

Repeat the above example if VRE is limited to 100 mV.

5.2.4 Self-Biased Stage Another biasing scheme commonly used in discrete and integrated circuits is shown in Fig. 5.22. Called “self-biased” because the base current and voltage are provided from the collector, this stage exhibits many interesting and useful attributes. Let us begin the analysis of the circuit with the observation that the base voltage is always lower than the collector voltage: VX = VY − IB RB . A result of self-biasing, this important property guarantees that Q 1 operates in the active mode regardless of device and circuit parameters. For example, if RC increases indefinitely, Q 1 remains in the active region, a critical advantage over the circuit of Fig. 5.21.

172

Chapter 5 Bipolar Amplifiers VCC RC

RB

Y IC

IB

Q1

X

Figure 5.22

Self-biased stage.

We now determine the collector bias current by assuming IB IC ; i.e., RC carries a current equal to IC , thereby yielding VY = VCC − RC IC .

(5.75)

Also, VY = RB IB + VBE =

RB IC + VBE . β

(5.76) (5.77)

Equating the right-hand sides of Eqs. (5.75) and (5.77) gives IC =

VCC − VBE . RB RC + β

(5.78)

As usual, we begin with an initial guess for VBE , compute IC , and utilize VBE = VT ln(IC /IS ) to improve the accuracy of our calculations.

Example 5.13

Determine the collector current and voltage ofQ 1 in Fig. 5.22 if RC = 1 k, RB = 10 k, VCC = 2.5 V, IS = 5 × 10−17 A, and β = 100. Repeat the calculations for RC = 2 k.

Solution

Assuming VBE = 0.8 V, we have from Eq. (5.78): IC = 1.545 mA,

(5.79)

and hence VBE = VT ln(IC /IS ) = 807.6 mV, concluding that the initial guess for VBE and the value of IC given by it are reasonably accurate. We also note that RB IB = 154.5 mV and VY = RB IB + VBE ≈ 0.955 V. If RC = 2 k, then with VBE = 0.8 V, Eq. (5.78) gives IC = 0.810 mA.

(5.80)

To check the validity of the initial guess, we write VBE = VT ln(IC /IS ) = 791 mV. Compared with VCC − VBE in the numerator of Eq. (5.78), the 9-mV error is negligible and the value of IC in Eq. (5.80) is acceptable. Since RB IB = 81 mV, VY ≈ 0.881 V. Exercise

What happens if the base resistance is doubled?

Equation (5.78) and the preceding example suggest two important guidelines for the design of the self-biased stage: (1) VCC − VBE must be much greater than the uncertainties

5.2 Operating Point Analysis and Design

173

in the value of VBE ; (2) RC must be much greater than RB /β to lower sensitivity to β. In fact, if RC RB /β, then IC ≈

VCC − VBE , RC

(5.81)

and VY = VCC − IC RC ≈ VBE . This result serves as a quick estimate of the transistor bias conditions. Design Procedure Equation (5.78) together with the condition RC RB /β provides the basic expressions for the design of the circuit. With the required value of IC known from small-signal considerations, we choose RC = 10RB /β and rewrite Eq. (5.78) as IC =

VCC − VBE , 1.1RC

(5.82)

RC =

VCC − VBE 1.1IC

(5.83)

RB =

βRC . 10

(5.84)

where VBE = VT ln(IC /IS ). That is,

The choice of RB also depends on small-signal requirements and may deviate from this value, but it must remain substantially lower than βRC . Example 5.14

Design the self-biased stage of Fig. 5.22 for gm = 1/(13 ) and VCC = 1.8 V. Assume IS = 5 × 10−16 A and β = 100.

Solution

Since gm = IC /VT = 1/(13 ), we have IC = 2 mA, VBE = 754 mV, and RC ≈

VCC − VBE 1.1IC

(5.85)

≈ 475 .

(5.86)

βRC 10

(5.87)

= 4.75 k.

(5.88)

Also, RB =

Note that RB IB = 95 mV, yielding a collector voltage of 754 mV + 95 mV = 849 mV. Exercise

Repeat the above design with a supply voltage of 2.5 V.

174

Chapter 5 Bipolar Amplifiers R1

RC

I1 RB

RC

R1

R2

RC

Q1 RE

VRE

Q1 Q1

Sensitive to β

Figure 5.23

R2

RB

RC Q1

Sensitive to Resistor Errors

Always in Active Mode

Summary of biasing techniques.

Figure 5.23 summarizes the biasing principles studied in this section. 5.2.5 Biasing of PNP Transistors The dc bias topologies studied thus far incorporate npn transistors. Circuits using pnp devices follow the same analysis and design procedures while requiring attention to voltage and current polarities. We illustrate these points with the aid of some examples.

Example 5.15

Calculate the collector and voltage of Q 1 in the circuit of Fig. 5.24 and determine the maximum allowable value of RC for operation in the active mode. IB

VCC

VEB X

RB

Q1 Y

IC RC

Figure 5.24

Solution

Simple biasing of pnp stage.

The topology is the same as that in Fig. 5.13 and we have IB RB + VEB = VCC .

(5.89)

That is, IB =

VCC − VEB RB

(5.90)

VCC − VEB . RB

(5.91)

and IC = β The circuit suffers from sensitivity to β.

5.2 Operating Point Analysis and Design

175

If RC is increased, VY rises, thus approaching VX (= VCC − VEB ) and bringing Q 1 closer to saturation. The transistor enters saturation at VY = VX , i.e., IC RC,max = VCC − VEB

(5.92)

and hence VCC − VEB IC RB = . β

RC,max =

(5.93) (5.94)

From another perspective, since VX = IB RB and VY = IC RC , we have IB RB = IC RC,max as the condition for edge of saturation, obtaining RB = βRC,max . Exercise

For a given RC , what value of RB places the device at the edge of saturation?

Example 5.16

Determine the collector current and voltage of Q 1 in the circuit of Fig. 5.25(a). VCC R2 I1

I B VEB X

R1

Y

VCC IB

R Thev

Q1

X V Thev

IC RC

Q1 Y

IC RC

(a)

Figure 5.25

VEB

(b)

(a) PNP stage with resistive divider biasing, (b) Thevenin equivalent of divider

and VCC . Solution

As a general case, we assume IB is significant and construct the Thevenin equivalent of the voltage divider as depicted in Fig. 5.25(b): VThev =

R1 VCC R1 + R 2

RThev = R1 ||R2 .

(5.95) (5.96)

Adding the voltage drop across RThev and VEB to VThev yields VThev + IB RThev + VEB = VCC ;

(5.97)

that is, VCC − VThev − VEB RThev R2 VCC − VEB R + R2 . = 1 RThev

IB =

(5.98)

(5.99)

176

Chapter 5 Bipolar Amplifiers It follows that R2 VCC − VEB R1 + R 2 . IC = β RThev

(5.100)

As in Example 5.9, some iteration between IC and VEB may be necessary. Equation (5.100) indicates that if IB is significant, then the transistor bias heavily depends on β. On the other hand, if IB I1 , we equate the voltage drop across R2 to VEB , thereby obtaining the collector current: R2 VCC = VEB R1 + R 2

(5.101)

IC = IS exp

R2 VCC . R1 + R2 VT

(5.102)

Note that this result is identical to Eq. (5.30). Exercise

What is the maximum value of RC if Q 1 must remain in soft saturation?

Example 5.17

Assuming a negligible base current, calculate the collector current and voltage of Q 1 in the circuit of Fig. 5.26. What is the maximum allowable value of RC for Q 1 to operate in the forward active region? VCC R2 I1

RE I B VEB X

R1

Y

VRE

Q1 IC RC

Figure 5.26

Solution

PNP stage with degeneration resistor.

With IB I1 , we have VX = VCC R1 /(R1 + R2 ). Adding to VX the emitter-base voltage and the drop across RE , we obtain VX + VEB + RE IE = VCC

(5.103)

R2 1 IE = VCC − VEB . RE R 1 + R 2

(5.104)

and hence

Using IC ≈ IE , we can compute a new value for VEB and iterate if necessary. Also, with IB = IC /β, we can verify the assumption IB I1 .

5.2 Operating Point Analysis and Design

177

In arriving at Eq. (5.104), we have written a KVL from VCC to ground, Eq. (5.103). But a more straightforward approach is to recognize that the voltage drop across R2 is equal to VEB + IE RE , i.e., VCC

R2 = VEB + IE RE , R1 + R 2

(5.105)

which yields the same result as in Eq. (5.104). The maximum allowable value of RC is obtained by equating the base and collector voltages: VCC

R1 = RC,max IC R1 + R 2 RC,max R2 ≈ VCC − VEB . RE R1 + R 2

(5.106) (5.107)

It follows that RC,max = RE VCC

R1 · R1 + R 2

1 . R2 VCC − VEB R1 + R 2

(5.108)

Exercise

Repeat the above example if R2 = ∞.

Example 5.18

Determine the collector current and voltage of Q 1 in the self-biased circuit of Fig. 5.27.

X

Q1 IB RB

Figure 5.27

Solution

VCC

VEB Y

IC RC

Self-biased pnp stage.

We must write a KVL from VCC through the emitter-base junction of Q 1 , RB , and RC to ground. Since β 1 and hence IC IB , RC carries a current approximately equal to IC , creating VY = RC IC . Moreover, VX = RB IB + VY = RB IB + RC IC , yielding VCC = VEB + VX = VEB + RB IB + IC RC RB = VEB + + RC IC . β

(5.109) (5.110) (5.111)

178

Chapter 5 Bipolar Amplifiers Thus, IC =

VCC − VEB , RB + RC β

(5.112)

a result similar to Eq. (5.78). As usual, we begin with a guess for VEB , compute IC , and determine a new value for VEB , etc. Note that, since the base is higher than the collector voltage, Q 1 always remains in the active mode. Exercise

5.3

How far is Q 1 from saturation?

BIPOLAR AMPLIFIER TOPOLOGIES Following our detailed study of biasing, we can now delve into different amplifier topologies and examine their small-signal properties.6 Since the bipolar transistor contains three terminals, we may surmise that three possibilities exist for applying the input signal to the device, as conceptually illustrated in Figs. 5.28(a)–(c). Similarly, the output signal can be sensed from any of the terminals (with respect to ground) [Figs. 5.28(d)–(f)], leading to nine possible combinations of input and output networks and hence nine amplifier topologies. v in v in

v in (a)

(b)

(c)

v out v out v out (d)

Figure 5.28

(e)

(f)

Possible input and output connections to a bipolar transistor.

However, as seen in Chapter 4, bipolar transistors operating in the active mode respond to base-emitter voltage variations by varying their collector current. This property rules out the input connection shown in Fig. 5.28(c) because here Vin does not affect the base or emitter voltages. Also, the topology in Fig. 5.28(f) proves of no value as Vout is not a function of the collector current. The number of possibilities therefore falls to four. But we note that the input and output connections in Figs. 5.28(b) and (e) remain incompatible because Vout would be sensed at the input node (the emitter) and the circuit would provide no function. 6 While beyond the scope of this book, the large-signal behavior of amplifiers also becomes important in many applications.

5.3 Bipolar Amplifier Topologies

179

The foregoing observations reveal three possible amplifier topologies. We study each carefully, seeking to compute its gain and input and output impedances. In all cases, the bipolar transistors operate in the active mode. The reader is encouraged to review Examples (5.2)–(5.4) and the three resulting rules illustrated in Fig. 5.7 before proceeding further. 5.3.1 Common-Emitter Topology Our initial thoughts in Section 4.1 pointed to the circuit of Fig. 4.1(b) and hence the topology of Fig. 4.25 as an amplifier. If the input signal is applied to the base [Fig. 5.28(a)] and the output signal is sensed at the collector [Fig. 5.28(d)], the circuit is called a “commonemitter” (CE) stage (Fig. 5.29). We have encountered and analyzed this circuit in different contexts without giving it a name. The term “common-emitter” is used because the emitter terminal is grounded and hence appears in common to the input and output ports. Nevertheless, we identify the stage based on the input and output connections (to the base and from the collector, respectively) so as to avoid confusion in more complex topologies.

VCC RC Vout

V in

Q 1 Output Sensed at Collector

Input Applied to Base

Figure 5.29

Common-emitter stage.

We deal with the CE amplifier in two phases: (a) analysis of the CE core to understand its fundamental properties, and (b) analysis of the CE stage including the bias circuitry as a more realistic case. Analysis of CE Core Recall from the definition of transconductance in Section 4.4.3 that a small increment of V applied to the base of Q 1 in Fig. 5.29 increases the collector current by gmV and hence the voltage drop across RC by gmVRC . In order to examine the amplifying properties of the CE stage, we construct the small-signal equivalent of the circuit, shown in Fig. 5.30. As explained in Chapter 4, the supply voltage node, VCC , acts as an ac ground because its value remains constant with time. We neglect the Early effect for now.

v in

v out rπ

Figure 5.30

vπ

Small-signal model of CE stage.

g vπ m

–

v out RC

RC

180

Chapter 5 Bipolar Amplifiers Let us first compute the small-signal voltage gain Av = vout /vin . Beginning from the output port and writing a KCL at the collector node, we have vout = gmvπ , RC

(5.113)

Av = −gmRC .

(5.114)

− and vπ = vin . It follows that

Equation (5.114) embodies two interesting and important properties of the CE stage. First, the small-signal gain is negative because raising the base voltage and hence the collector current in Fig. 5.29 lowers Vout . Second, Av is proportional to gm (i.e., the collector bias current) and the collector resistor, RC . Interestingly, the voltage gain of the stage is limited by the supply voltage. A higher collector bias current or a larger RC demands a greater voltage drop across RC , but this drop cannot exceed VCC . In fact, denoting the dc drop across RC with VRC and writing gm = IC /VT , we express Eq. (5.113) as |Av | =

IC RC VT

(5.115)

=

VRC . VT

(5.116)

Since VRC < VCC , |Av | <

VCC . VT

(5.117)

Furthermore, the transistor itself requires a minimum collector-emitter voltage of about VBE to remain in the active region, lowering the limit to |Av | <

VCC − VBE . VT

(5.118)

Example 5.19

Design a CE core with VCC = 1.8 V and a power budget, P, of 1 mW while achieving maximum voltage gain.

Solution

Since P = IC · VCC = 1 mW, we have IC = 0.556 mA. The value of RC that places Q 1 at the edge of saturation is given by VCC − RC IC = VBE ,

(5.119)

which, along with VBE ≈ 800 mV, yields RC ≤

VCC − VBE IC

≤ 1.8 k.

(5.120) (5.121)

5.3 Bipolar Amplifier Topologies

181

The voltage gain is therefore equal to Av = −gmRC

(5.122)

= −38.5.

(5.123)

Under this condition, an input signal drives the transistor into saturation. As illustrated in Fig. 5.31(a), a 2-mVpp input results in a 77-mVpp output, forward-biasing the basecollector junction for half of each cycle. Nevertheless, so long as Q 1 remains in soft saturation (VBC > 400 mV), the circuit amplifies properly. A more aggressive design may allow Q 1 to operate in soft saturation, e.g., VCE ≈ 400 mV and hence RC ≤

VCC − 400 mV IC

(5.124)

≤ 2.52 k.

(5.125)

In this case, the maximum voltage gain is given by Av = −53.9.

(5.126)

Of course, the circuit can now tolerate only very small voltage swings at the output. For example, a 2-mVpp input signal gives rise to a 107.8-mVpp output, driving Q 1 into heavy saturation [Fig. 5.31(b)]. We say the circuit suffers from a trade-off between voltage gain and voltage “headroom.”

77 mV pp

VCC RC 2 mVpp

800 mV

800 mV

Q1 t t

(a)

VCC

107.8 mVpp

RC 2 mVpp 800 mV

Q1

400 mV

t t (b)

Figure 5.31 Exercise

CE stage (a) with some signal levels, (b) in saturation.

Repeat the above example if VCC = 2.5 V and compare the results.

182

Chapter 5 Bipolar Amplifiers iX vX

iX rπ

vπ

RC

g vπ m

rπ

vπ

(a)

Figure 5.32

g vπ m

RC

vX

(b)

(a) Input and (b) output impedance calculation of CE stage.

Let us now calculate the I/O impedances of the CE stage. Using the equivalent circuit depicted in Fig. 5.32(a), we write vX iX

(5.127)

= rπ .

(5.128)

Rin =

Thus, the input impedance is simply equal to β/gm = βVT /IC and decreases as the collector bias increases. The output impedance is obtained from Fig. 5.32(b), where the input voltage source is set to zero (replaced with a short). Since vπ = 0, the dependent current source also vanishes, leaving RC as the only component seen by vX . In other words, Rout =

vX iX

(5.129)

= RC .

(5.130)

The output impedance therefore trades with the voltage gain, −gmRC . Figure 5.33 summarizes the trade-offs in the performance of the CE topology along with the parameters that create such trade-offs. For example, for a given value of output impedance, RC is fixed and the voltage gain can be increased by increasing IC , thereby lowering both the voltage headroom and the input impedance. Voltage Headroom (Swings)

g

m

Input Impedance

β

gm Figure 5.33

CE stage trade-offs.

Voltage Gain

RC Output Impedance RC

5.3 Bipolar Amplifier Topologies

183

Example 5.20

A CE stage must achieve an input impedance of Rin and an output impedance of Rout . What is the voltage gain of the circuit?

Solution

Since Rin = rπ = β/gm and Rout = RC , we have Av = −gmRC = −β

(5.131)

Rout . Rin

(5.132)

Interestingly, if the I/O impedances are specified, then the voltage gain is automatically set. We will develop other circuits in this book that avoid this “coupling” of design specifications. Exercise

What happens to this result if the supply voltage is halved?

Inclusion of Early Effect Equation (5.114) suggests that the voltage gain of the CE stage can be increased indefinitely if RC → ∞ while gm remains constant. Mentioned in Section 4.4.5, this trend appears valid if VCC is also raised to ensure the transistor remains in the active mode. From an intuitive point of view, a given change in the input voltage and hence the collector current gives rise to an increasingly larger output swing as RC increases. In reality, however, the Early effect limits the voltage gain even if RC approaches infinity. Since achieving a high gain proves critical in circuits such as operational amplifiers, we must reexamine the above derivations in the presence of the Early effect. Figure 5.34 depicts the small-signal equivalent circuit of the CE stage including the transistor output resistance. Note that rO appears in parallel with RC , allowing us to rewrite Eq. (5.114) as Av = −gm(RC ||rO ).

(5.133)

We also recognize that the input impedance remains equal to rπ whereas the output impedance falls to Rout = RC ||rO .

(5.134)

v in

v out rπ

Figure 5.34

vπ

CE stage including Early effect.

g vπ m

rO

RC

184

Chapter 5 Bipolar Amplifiers

Example 5.21

The circuit of Fig. 5.29 is biased with a collector current of 1 mA and RC = 1 k. If β = 100 and VA = 10 V, determine the small-signal voltage gain and the I/O impedances.

Solution

We have gm =

IC VT

(5.135)

= (26 )−1

(5.136)

and rO =

VA IC

(5.137)

= 10 k.

(5.138)

Av = −gm(RC ||rO )

(5.139)

Thus,

≈ 35.

(5.140)

(As a comparison, if VA = ∞, then Av ≈ 38.) For the I/O impedances, we write Rin = rπ

(5.141)

β gm

(5.142)

= 2.6 k

(5.143)

Rout = RC ||rO

(5.144)

=

and

= 0.91 k. Exercise

(5.145)

Calculate the gain if VA = 5 V. Let us determine the gain of a CE stage as RC → ∞. Equation (5.132) gives Av = −gmrO .

(5.146)

Called the “intrinsic gain” of the transistor to emphasize that no external device loads the circuit, gmrO represents the maximum voltage gain provided by a single transistor, playing a fundamental role in high-gain amplifiers. We now substitute gm = IC /VT and rO = VA /IC in Eq. (5.133), thereby arriving at |Av | =

VA . VT

(5.147)

5.3 Bipolar Amplifier Topologies

185

Interestingly, the intrinsic gain of a bipolar transistor is independent of the bias current. In modern integrated bipolar transistors, VA falls in the vicinity of 5 V, yielding a gain of nearly 200.7 In this book, we assume gmrO 1 (and hence rO 1/gm) for all transistors. Another parameter of the CE stage that may prove relevant in some applications is the “current gain,” defined as AI =

i out , i in

(5.148)

where i out denotes the current delivered to the load and i in the current flowing to the input. We rarely deal with this parameter for voltage amplifiers, but note that AI = β for the stage shown in Fig. 5.29 because the entire collector current is delivered to RC . CE Stage With Emitter Degeneration In many applications, the CE core of Fig. 5.29 is modified as shown in Fig. 5.35(a), where a resistor RE appears in series with the emitter. Called “emitter degeneration,” this technique improves the “linearity” of the circuit and provides many other interesting properties that are studied in more advanced courses.

VCC

VCC

RC

RC Vout

V in

Q1 RE

Vout

ΔV

Q1 RE

(a)

Figure 5.35

(b)

(a) CE stage with degeneration, (b) effect of input voltage change.

As with the CE core, we intend to determine the voltage gain and I/O impedances of the circuit, assuming Q 1 is biased properly. Before delving into a detailed analysis, it is instructive to make some qualitative observations. Suppose the input signal raises the base voltage by V [Fig. 5.35(b)]. If RE were zero, then the base-emitter voltage would also increase by V, producing a collector current change of gm V. But with RE = 0, some fraction of V appears across RE , thus leaving a voltage change across the BE junction that is less than V. Consequently, the collector current change is also less than gm V. We therefore expect that the voltage gain of the degenerated stage is lower than that of the CE core with no degeneration. While undesirable, the reduction in gain is incurred to improve other aspects of the performance. How about the input impedance? Since the collector current change is less than gm V, the base current also changes by less than gm V/β, yielding an input impedance greater than β/gm = rπ . Thus, emitter degeneration increases the input impedance of the CE stage, a desirable property. A common mistake is to conclude that Rin = rπ + RE , but as explained below, Rin = rπ + (β + 1)RE . 7

But other second-order effects limit the actual gain to about 50.

186

Chapter 5 Bipolar Amplifiers v out v in

rπ

g vπ m

vπ

RC

RE

Figure 5.36

Small-signal model of CE stage with emitter degeneration.

We now quantify the foregoing observations by analyzing the small-signal behavior of the circuit. Depicted in Fig. 5.36 is the small-signal equivalent circuit, where VCC is replaced with an ac ground and the Early effect is neglected. Note that vπ appears across rπ and not from the base to ground. To determine vout /vin , we first write a KCL at the output node, vout , RC

(5.149)

vout . gmRC

(5.150)

gmvπ = − obtaining vπ = −

We also recognize that two currents flow through RE : one originating from rπ equal to vπ /rπ and another equal to gmvπ . Thus, the voltage drop across RE is given by vπ vRE = + gmvπ RE . (5.151) rπ Since the voltage drop across rπ and RE must add up to vin , we have vin = vπ + vRE vπ = vπ + + gmvπ RE rπ 1 = vπ 1 + + gm RE . rπ

(5.152) (5.153) (5.154)

Substituting for vπ from Eq. (5.150) and rearranging the terms, we arrive at vout =− vin

gmRC . 1 1+ + gm RE rπ

(5.155)

As predicted earlier, the magnitude of the voltage gain is lower than gmRC for RE = 0. With β 1, we can assume gm 1/rπ and hence Av = −

gmRC . 1 + gmRE

(5.156)

Thus, the gain falls by a factor of 1 + gmRE . To arrive at an interesting interpretation of Eq. (5.156), we divide the numerator and denominator by gm, Av = −

RC . 1 + RE gm

(5.157)

5.3 Bipolar Amplifier Topologies

187

It is helpful to memorize this result as “the gain of the degenerated CE stage is equal to the total load resistance seen at the collector (to ground) divided by 1/gm plus the total resistance placed in series with the emitter.” (In verbal descriptions, we often ignore the negative sign in the gain, with the understanding that it must be included.) This and similar interpretations throughout this book greatly simplify the analysis of amplifiers—often obviating the need for drawing small-signal circuits.

Example 5.22

Determine the voltage gain of the stage shown in Fig. 5.37(a).

VCC

VCC

RC

RC v out

v in

v out

VCC v in

Q1

Q1

Q2 RE

rπ2

RE rπ2 (a)

Figure 5.37 Solution

(b)

(a) CE stage example, (b) simplified circuit.

We identify the circuit as a CE stage because the input is applied to the base of Q 1 and the output is sensed at its collector. This transistor is degenerated by two devices: RE and the base-emitter junction of Q 2 . The latter exhibits an impedance of rπ 2 (as illustrated in Fig. 5.7), leading to the simplified model depicted in Fig. 5.37(b). The total resistance placed in series with the emitter is therefore equal to RE ||rπ 2 , yielding Av = −

RC 1 + RE ||rπ 2 gm1

.

(5.158)

Without the above observations, we would need to draw the small-signal model of both Q 1 and Q 2 and solve a system of several equations. Exercise

Repeat the above example if a resistor is placed in series with the emitter of Q 2 .

Example 5.23

Calculate the voltage gain of the circuit in Fig. 5.38(a).

Solution

The topology is a CE stage degenerated by RE , but the load resistance between the collector of Q 1 and ac ground consists of RC and the base-emitter junction of Q 2 . Modeling the latter by rπ 2 , we reduce the circuit to that shown in Fig. 5.38(b), where the total load resistance seen at the collector of Q 1 is equal to RC ||rπ 2 . The

188

Chapter 5 Bipolar Amplifiers voltage gain is thus given by Av = −

RC ||rπ 2 . 1 + RE gm1

(5.159)

VCC

VCC

RC

RC v out

v in

v out

VCC v in

Q1

rπ2

Q1

Q2 RE

RE

(a)

Figure 5.38

Exercise

(b)

(a) CE stage example, (b) simplified circuit.

Repeat the above example if a resistor is placed in series with the emitter of Q 2 .

To compute the input impedance of the degenerated CE stage, we redraw the smallsignal model as in Fig. 5.39(a) and calculate vX /i X . Since vπ = rπ i X , the current flowing through RE is equal to i X + gmrπ i X = (1 + β)i X , creating a voltage drop of RE (1 + β)i X . Summing vπ and vRE and equating the result to vX , we have vX = rπ i X + RE (1 + β)i X ,

(5.160)

and hence Rin =

vX iX

(5.161)

= rπ + (β + 1)RE .

(5.162)

As predicted by our qualitative reasoning, emitter degeneration increases the input impedance [Fig. 5.39(b)]. Why is Rin not simply equal to rπ + RE ? This would hold only if rπ and RE were exactly in series, i.e., if the two carried equal currents, but in the circuit of Fig. 5.39(a), the collector current, gmvπ , also flows into node P.

iX vX

rπ

g vπ m

vπ v RE

P RE (a)

Figure 5.39

iX

v out RC

rπ

vX R in

( β + 1) R E (b)

(a) Input impedance of degenerated CE stage, (b) equivalent circuit.

5.3 Bipolar Amplifier Topologies

189

iX rπ

v RE

Figure 5.40

RC

g vπ m

vπ

vX

P RE

Output impedance of degenerated stage.

Does the factor β + 1 bear any intuitive meaning? We observe that the flow of both base and collector currents through RE results in a large voltage drop, (β + 1)i X RE , even though the current drawn from vX is merely i X . In other words, the test voltage source, vX , supplies a current of only i X while producing a voltage drop of (β + 1)i X RE across RE —as if i X flows through a resistor equal to (β + 1)RE . The above observation is articulated as follows: any impedance tied between the emitter and ground is multiplied by β + 1 when “seen from the base.” The expression “seen from the base” means the impedance measured between the base and ground. We also calculate the output impedance of the stage with the aid of the equivalent shown in Fig. 5.40, where the input voltage is set to zero. Equation (5.153) applies to this circuit as well: vin = 0 = vπ +

vπ + gmvπ RE , rπ

(5.163)

yielding vπ = 0 and hence gmvπ = 0. Thus, all of i X flows through RC , and vX iX

(5.164)

= RC ,

(5.165)

Rout =

revealing that emitter degeneration does not alter the output impedance if the Early effect is neglected.

Example 5.24

A CE stage is biased at a collector current of 1 mA. If the circuit provides a voltage gain of 20 with no emitter degeneration and 10 with degeneration, determine RC , RE , and the I/O impedances. Assume β = 100.

Solution

For Av = 20 in the absence of degeneration, we require gmRC = 20,

(5.166)

which, together with gm = IC /VT = (26 )−1 , yields RC = 520 .

(5.167)

Since degeneration lowers the gain by a factor of two, 1 + gmRE = 2,

(5.168)

190

Chapter 5 Bipolar Amplifiers i.e., 1 gm

(5.169)

= 26 .

(5.170)

RE =

The input impedance is given by Rin = rπ + (β + 1)RE =

β + (β + 1)RE gm

≈ 2rπ

(5.171) (5.172) (5.173)

because β 1 and RE = 1/gm in this example. Thus, Rin = 5200 . Finally, Rout = RC

(5.174)

= 520 .

(5.175)

Exercise

What bias current would result in a gain of 5 with such emitter and collector resistor values?

Example 5.25

Compute the voltage gain and I/O impedances of the circuit depicted in Fig. 5.41. Assume a very large value for C1 . VCC RC Vout V in

Q1 RE

Constant

Figure 5.41

C1

CE stage example.

Solution

If C1 is very large, it acts as a short circuit for the signal frequencies of interest. Also, the constant current source is replaced with an open circuit in the small-signal equivalent circuit. Thus, the stage reduces to that in Fig. 5.35(a) and Eqs. (5.157), (5.162), (5.165) apply.

Exercise

Repeat the above example if we tie another capacitor from the base to ground.

The degenerated CE stage can be analyzed from a different perspective to provide more insight. Let us place the transistor and the emitter resistor in a black box having

5.3 Bipolar Amplifier Topologies i out v in

i out

v in rπ

Q1

g vπ m

vπ

RE

RE

(a)

Figure 5.42

191

(b)

(a) Degenerated bipolar transistor viewed as a black box, (b) small-signal equivalent.

still three terminals [Fig. 5.42(a)]. For small-signal operation, we can view the box as a new transistor (or “active” device) and model its behavior by new values of transconductance and impedances. Denoted by Gm to avoid confusion with gm of Q 1 , the equivalent transconductance is obtained from Fig. 5.42(b). Since Eq. (5.154) still holds, we have i out = gmvπ = gm

(5.176)

1+

vin , + gm)RE

(5.177)

(rπ−1

and hence Gm = ≈

i out vin

(5.178)

gm . 1 + gmRE

(5.179)

For example, the voltage gain of the stage with a load resistance of RD is given by −GmRD . An interesting property of the degenerated CE stage is that its voltage gain becomes relatively independent of the transistor transconductance and hence bias current if gmRE 1. From Eq. (5.157), we note that Av → −RC /RE under this condition. This trend in fact represents the “linearizing” effect of emitter degeneration. As a more general case, we now consider a degenerated CE stage containing a resistance in series with the base [Fig. 5.43(a)]. As seen below, RB only degrades the

VCC RC v in

v out

RB A

Q1

RE

(a)

Figure 5.43

v in

RB

A

rπ ( β + 1) R E (b)

(a) CE stage with base resistance, (b) equivalent circuit.

192

Chapter 5 Bipolar Amplifiers performance of the circuit, but often proves inevitable. For example, RB may represent the output resistance of a microphone connected to the input of the amplifier. To analyze the small-signal behavior of this stage, we can adopt one of two approaches: (a) draw the small-signal model of the entire circuit and solve the resulting equations, or (b) recognize that the signal at node A is simply an attenuated version of vin and write vA vout vout = · . vin vin vA

(5.180)

Here, vA /vin denotes the effect of voltage division between RB and the impedance seen at the base of Q 1 , and vout /vA represents the voltage gain from the base of Q 1 to the output, as already obtained in Eqs. (5.155) and (5.157). We leave the former approach for Problem 5.37 and continue with the latter here. Let us first compute vA /vin with the aid of Eq. (5.162) and the model depicted in Fig. 5.39(b), as illustrated in Fig. 5.43(b). The resulting voltage divider yields rπ + (β + 1)RE vA = . vin rπ + (β + 1)RE + RB

(5.181)

Combining Eqs. (5.155) and (5.157), we arrive at the overall gain as rπ + (β + 1)RE vout = · vin rπ + (β + 1)RE + RB

−gmRC 1 1+ + gm RE rπ

(5.182)

=

−gmrπ RC rπ + (β + 1)RE · rπ + (β + 1)RE + RB rπ + (1 + β)RE

(5.183)

=

−βRC . rπ + (β + 1)RE + RB

(5.184)

To obtain a more intuitive expression, we divide the numerator and the denominator by β: Av ≈

−RC 1 RB + RE + gm β +1

.

(5.185)

Compared to Eq. (5.157), this result contains only one additional term in the denominator equal to the base resistance divided by β + 1. The above results reveal that resistances in series with the emitter and the base have similar effects on the voltage gain, but RB is scaled down by β + 1. The significance of this observation becomes clear later. For the stage of Fig. 5.43(a), we can define two different input impedances, one seen at the base of Q 1 and another at the left terminal of RB (Fig. 5.44). The former is equal to Rin1 = rπ + (β + 1)RE

(5.186)

Rin2 = RB + rπ + (β + 1)RE .

(5.187)

and the latter,

5.3 Bipolar Amplifier Topologies

193

VCC RC RB

R in2

Figure 5.44

R in1

v out Q1 RE

Input impedances seen at different nodes.

In practice, Rin1 proves more relevant and useful. We also note that the output impedance of the circuit remains equal to Rout = RC

(5.188)

even with RB = 0.

Example 5.26

Solution

A microphone having an output resistance of 1 k generates a peak signal level of 2 mV. Design a CE stage with a bias current of 1 mA that amplifies this signal to 40 mV. Assume RE = 4/gm and β = 100. The following quantities are obtained: RB = 1 k, gm = (26 )−1 , |Av | = 20, and RE = 104 . From Eq. (5.185), 1 RB RC = |Av | + RE + (5.189) gm β +1 ≈ 2.8 k.

(5.190)

Exercise

Repeat the above example if the microphone output resistance is doubled.

Example 5.27

Determine the voltage gain and I/O impedances of the circuit shown in Fig. 5.45(a). Assume a very large value for C 1 and neglect the Early effect. VCC RC v in

RB

RC

v out Q1

R1 R2

v in

RB

v out Q1

C1 R2

I1 (a)

Figure 5.45

(a) CE stage example, (b) simplified circuit.

(b)

R1

194

Chapter 5 Bipolar Amplifiers

Solution

Replacing C 1 with a short circuit, I1 with an open circuit, and VCC with ac ground, we arrive at the simplified model in Fig. 5.45(b), where R1 and RC appear in parallel and R2 acts as an emitter degeneration resistor. Equations (5.185)–(5.188) are therefore written respectively as Av =

−(RC ||R1 ) 1 RB + R2 + gm β +1

(5.191)

Rin = RB + rπ + (β + 1)R2

(5.192)

Rout = RC ||R1 . Exercise

(5.193)

What happens if a very large capacitor is tied from the emitter of Q 1 to ground?

Effect of Transistor Output Resistance The analysis of the degenerated CE stage has thus far neglected the Early effect. We nonetheless explore one aspect of the circuit, namely, the output resistance, as it provides the foundation for many other topologies studied later. Our objective is to determine the output impedance seen looking into the collector of a degenerated transistor [Fig. 5.46(a)]. Recall from Fig. 5.7 that Rout = rO if RE = 0. Also, Rout = ∞ if VA = ∞ (why?). To include the Early effect, we draw the smallsignal equivalent circuit as in Fig. 5.46(b), grounding the input terminal. A common mistake here is to write Rout = rO + RE . Since gmvπ flows from the output node into P, resistors rO and RE are not in series. We readily note that RE and rπ appear in parallel, and the current flowing through RE ||rπ is equal to i X . Thus, vπ = −i X (RE ||rπ ),

(5.194)

R out V in

Q1 RE

(a)

Figure 5.46

iX rπ

g vπ m

vπ P RE

rO

vX

iX

(b)

(a) Output impedance of degenerated stage, (b) equivalent circuit.

where the negative sign arises because the positive side of vπ is at ground. We also recognize that rO carries a current of i X − gmvπ and hence sustains a voltage of (i X − gmvπ )rO . Adding

5.3 Bipolar Amplifier Topologies

195

this voltage to that across RE (= −vπ ) and equating the result to vX , we obtain vX = (i X − gmvπ )rO − vπ

(5.195)

= [i X + gmi X (RE ||rπ )]rO + i X (RE ||rπ ).

(5.196)

Rout = [1 + gm(RE ||rπ )]rO + RE ||rπ

(5.197)

It follows that

= rO + (gmrO + 1)(RE ||rπ ).

(5.198)

Recall from Eq. (5.146) that the intrinsic gain of the transistor, gmrO 1, and hence Rout ≈ rO + gmrO (RE ||rπ ) ≈ rO [1 + gm(RE ||rπ )].

(5.199) (5.200)

Interestingly, emitter degeneration raises the output impedance from rO to the above value, i.e., by a factor of 1 + gm(RE ||rπ ). The reader may wonder if the increase in the output resistance is desirable or undesirable. The “boosting” of output resistance as a result of degeneration proves extremely useful in circuit design, producing amplifiers with a higher gain as well as creating more ideal current sources. These concepts are studied in Chapter 9. It is instructive to examine Eq. (5.200) for two special cases RE rπ and RE rπ . For RE rπ , we have RE ||rπ → rπ and Rout ≈ rO (1 + gmrπ ) ≈ βrO ,

(5.201) (5.202)

because β 1. Thus, the maximum resistance seen at the collector of a bipolar transistor is equal to βrO —if the degeneration impedance becomes much larger than rπ . For RE rπ , we have RE ||rπ → RE and Rout ≈ (1 + gmRE )rO .

(5.203)

Thus, the output resistance is boosted by a factor of 1 + gmRE . In the analysis of circuits, we sometimes draw the transistor output resistance explicitly to emphasize its significance (Fig. 5.47). This representation, of course, assumes Q 1 itself does not contain another rO .

R out Q1 V in

rO RE

Figure 5.47

Stage with explicit depiction of rO .

196

Chapter 5 Bipolar Amplifiers

Example 5.28

We wish to design a current source having a value of 1 mA and an output resistance of 20 k. The available bipolar transistor exhibits β = 100 and VA = 10 V. Determine the minimum required value of emitter degeneration resistance.

Solution

Since rO = VA /IC = 10 k, degeneration must raise the output resistance by a factor of two. We postulate that the condition RE rπ holds and write 1 + gmRE = 2.

(5.204)

1 gm

(5.205)

= 26 .

(5.206)

That is, RE =

Note that indeed rπ = β/gm RE . Exercise

What is the output impedance if RE is doubled?

Example 5.29

Calculate the output resistance of the circuit shown in Fig. 5.48(a) if C 1 is very large. R out

Vb

Q1

R out R1 R2

Q1

R out1 R1

Q1

C1 R2

R2

I1 (a)

Figure 5.48 Solution

(b)

(c)

(a) CE stage example, (b) simplified circuit, (c) resistance seen at the collector.

Replacing Vb and C 1 with an ac ground and I1 with an open circuit, we arrive at the simplified model in Fig. 5.48(b). Since R1 appears in parallel with the resistance seen looking into the collector of Q 1 , we ignore R1 for the moment, reducing the circuit to that in Fig. 5.48(c). In analogy with Fig. 5.40, we rewrite Eq. (5.200) as Rout1 = [1 + gm(R2 ||rπ )]rO .

(5.207)

Returning to Fig. 5.48(b), we have Rout = Rout1 ||R1 = [1 + gm(R2 ||rπ )]rO ||R1 . Exercise

(5.208) (5.209)

What is the output resistance if a very large capacitor is tied between the emitter of Q 1 and ground?

5.3 Bipolar Amplifier Topologies

197

The procedure of progressively simplifying a circuit until it resembles a known topology proves extremely critical in our work. Called “analysis by inspection,” this method obviates the need for complex small-signal models and lengthy calculations. The reader is encouraged to attempt the above example using the small-signal model of the overall circuit to appreciate the efficiency and insight provided by our intuitive approach.

Example 5.30

Determine the output resistance of the stage shown in Fig. 5.49(a).

R out Q1

V b2

R out Q1 r O2

Q2

V b1 (a)

Figure 5.49 Solution

(b)

(a) CE stage example, (b) simplified circuit.

Recall from Fig. 5.7 that the impedance seen at the collector is equal to rO if the base and emitter are (ac) grounded. Thus, Q 2 can be replaced with rO2 [Fig. 5.49(b)]. From another perspective, Q 2 is reduced to rO2 because its base-emitter voltage is fixed by Vb1 , yielding a zero gm2 vπ 2 . Now, rO2 plays the role of emitter degeneration resistance for Q 1 . In analogy with Fig. 5.40(a), we rewrite Eq. (5.200) as Rout = [1 + gm1 (rO2 ||rπ 1 )]rO1 .

(5.210)

Called a “cascode” circuit, this topology is studied and utilized extensively in Chapter 9. Exercise

Repeat the above example for a “stack” of three transistors.

CE Stage with Biasing Having learned the small-signal properties of the commonemitter amplifier and its variants, we now study a more general case wherein the circuit contains a bias network as well. We begin with simple biasing schemes described in Section 5.2 and progressively add complexity (and more robust performance) to the circuit. Let us begin with an example.

198

Chapter 5 Bipolar Amplifiers

Example 5.31

A student familiar with the CE stage and basic biasing constructs the circuit shown in Fig. 5.50 to amplify the signal produced by a microphone. Unfortunately, Q 1 carries no current, failing to amplify. Explain the cause of this problem. VCC = 2.5 V 100 k Ω

RC

RB

Vout

X

Figure 5.50 Solution

1 kΩ

Q1

Microphone amplifier.

Many microphones exhibit a small low-frequency resistance (e.g., <100 ). If used in this circuit, such a microphone creates a low resistance from the base of Q 1 to ground, forming a voltage divider with RB and providing a very low base voltage. For example, a microphone resistance of 100 yields VX =

100 × 2.5 V 100 k + 100

≈ 2.5 mV.

(5.211) (5.212)

Thus, the microphone low-frequency resistance disrupts the bias of the amplifier. Exercise

Does the circuit operate better if RB is halved?

How should the circuit of Fig. 5.50 be fixed? Since only the signal generated by the microphone is of interest, a series capacitor can be inserted as depicted in Fig. 5.51 so as to isolate the dc biasing of the amplifier from the microphone. That is, the bias point of Q 1 remains independent of the resistance of the microphone because C 1 carries no bias current. The value of C 1 is chosen so that it provides a relatively low impedance (almost a short circuit) for the frequencies of interest. We sayC 1 is a “coupling” capacitor and the input of this stage is “ac-coupled” or “capacitively coupled.” Many circuits employ capacitors to isolate the bias conditions from “undesirable” effects. More examples clarify this point later. VCC = 2.5 V 100 k Ω

RC

RB X

C1

Figure 5.51

1 kΩ

Vout Q1

Capacitive coupling at the input of microphone amplifier.

The foregoing observation suggests that the methodology illustrated in Fig. 5.9 must include an additional rule: replace all capacitors with an open circuit for dc analysis and a short circuit for small-signal analysis. Let us begin with the stage depicted in Fig. 5.52(a). For bias calculations, the signal source is set to zero and C 1 is opened, leading to Fig. 5.52(b). From Section 5.2.1,

5.3 Bipolar Amplifier Topologies VCC

VCC

RC

RB X C1

Y

Vout

X

Q1

(a)

Y Q1

RC

(c)

RC

Q1

RB R in2

Q1 RB

v in

(b)

Q1

v out

X

RC

RB

199

RC R out

RB R in1 (d)

(e)

Figure 5.52 (a) Capacitive coupling at the input of a CE stage, (b) simplified stage for bias calculation, (c) simplified stage for small-signal calculation, (d) simplified circuit for input impedance calculation, (e) simplified circuit for output impedance calculation.

we have IC = β

VCC − VBE , RB

VY = VCC − βRC

VCC − VBE . RB

(5.213) (5.214)

To avoid saturation, VY ≥ VBE . With the bias current known, the small-signal parameters gm, rπ , and rO can be calculated. We now turn our attention to small-signal analysis, considering the simplified circuit of Fig. 5.52(c). Here, C 1 is replaced with a short and VCC with ac ground, but Q 1 is maintained as a symbol. We attempt to solve the circuit by inspection: if unsuccessful, we will resort to using a small-signal model for Q 1 and writing KVLs and KCLs. The circuit of Fig. 5.52(c) resembles the CE core illustrated in Fig. 5.29, except for RB . Interestingly, RB has no effect on the voltage at node X so long as vin remains an ideal voltage source; i.e., vX = vin regardless of the value of RB . Since the voltage gain from the base to the collector is given by vout /vX = −gmRC , we have vout = −gmRC . vin

(5.215)

vout = −gm(RC ||rO ). vin

(5.216)

If VA < ∞, then

However, the input impedance is affected by RB [Fig. 5.52(d)]. Recall from Fig. 5.7 that the impedance seen looking into the base, Rin1 , is equal to rπ if the emitter is grounded. Here, RB simply appears in parallel with Rin1 , yielding Rin2 = rπ ||RB .

(5.217)

Thus, the bias resistor lowers the input impedance. Nevertheless, this effect is usually negligible.

200

Chapter 5 Bipolar Amplifiers To determine the output impedance, we set the input source to zero [Fig. 5.52(e)]. Comparing this circuit with that in Fig. 5.32(b), we recognize that Rout remains unchanged: Rout = RC ||rO .

(5.218)

because both terminals of RB are shorted to ground. In summary, the bias resistor, RB , negligibly impacts the performance of the stage shown in Fig. 5.52(a).

Example 5.32

Having learned about ac coupling, the student in Example 5.31 modifies the design to that shown in Fig. 5.53 and attempts to drive a speaker. Unfortunately, the circuit still fails. Explain why. VCC = 2.5 V 100 k Ω

RC

RB X

C1

Figure 5.53

1 kΩ

Q1

Amplifier with direct connection of speaker.

Solution

Typical speakers incorporate a solenoid (inductor) to actuate a membrane. The solenoid exhibits a very low dc resistance, e.g., less than 1 . Thus, the speaker in Fig. 5.53 shorts the collector to ground, driving Q 1 into deep saturation.

Exercise

Does the circuit operate better if the speaker is tied between the output node and VCC ?

Example 5.33

The student applies ac coupling to the output as well [Fig. 5.54(a)] and measures the quiescent points to ensure proper biasing. The collector bias voltage is 1.5 V, indicating that Q 1 operates in the active region. However, the student still observes no gain in the circuit. (a) If IS = 5 × 10−17 A and VA = ∞, compute the β of the transistor. (b) Explain why the circuit provides no gain.

VCC = 2.5 V 100 k Ω

RC

RB X

1 kΩ

Q1

C1 (a)

C2

v out

v in

100 k Ω

Q1

RC

1 k Ω R sp

RB

(b)

Figure 5.54 (a) Amplifier with capacitive coupling at the input and output, (b) simplified small-signal model.

8Ω

5.3 Bipolar Amplifier Topologies Solution

201

(a) A collector voltage of 1.5 V translates to a voltage drop of 1 V across RC and hence a collector current of 1 mA. Thus, VBE = VT ln

IC IS

(5.219)

= 796 mV.

(5.220)

It follows that IB =

VCC − VBE RB

(5.221)

= 17 μA,

(5.222)

and β = IC /IB = 58.8. (b) Speakers typically exhibit a low impedance in the audio frequency range, e.g., 8 . Drawing the ac equivalent as in Fig. 5.54(b), we note that the total resistance seen at the collector node is equal to 1 k||8 , yielding a gain of |Av | = gm(RC ||RS ) = 0.31. Exercise

(5.223)

Repeat the above example for RC = 500 .

The design in Fig. 5.54(a) exemplifies an improper interface between an amplifier and a load: the output impedance is so much higher than the load impedance that the connection of the load to the amplifier drops the gain drastically. How can we remedy the problem of loading here? Since the voltage gain is proportional to gm, we can bias Q 1 at a much higher current to raise the gain. Alternatively, we can interpose a “buffer” stage between the CE amplifier and the speaker (Section 5.3.3). Let us now consider the biasing scheme shown in Fig. 5.15 and repeated in Fig. 5.55(a). To determine the bias conditions, we set the signal source to zero and open the capacitor(s). Equations (5.38)–(5.41) can then be used. For small-signal analysis, the simplified circuit in Fig. 5.55(b) reveals a resemblance to that in Fig. 5.52(b), except that both R1 and R2

VCC R1

v in

C1

Q1 R2 (a)

Figure 5.55

v out

RC Q1 v in

R1

R2

(b)

(a) Biased stage with capacitive coupling, (b) simplified circuit.

RC

202

Chapter 5 Bipolar Amplifiers VCC R1

v in

C1

v out

RC Q1

Q1 R2

R1

v in

RE

R2

(a)

Figure 5.56

RC

RE

(b)

(a) Degenerated stage with capacitive coupling, (b) simplified circuit.

appear in parallel with the input. Thus, the voltage gain is still equal to −gm(RC ||rO ) and the input impedance is given by Rin = rπ ||R1 ||R2 .

(5.224)

The output resistance is equal to RC ||rO . We next study the more robust biasing scheme of Fig. 5.19, repeated in Fig. 5.56(a) along with an input coupling capacitor. The bias point is determined by opening C 1 and following Eqs. (5.52) and (5.53). With the collector current known, the smallsignal parameters of Q 1 can be computed. We also construct the simplified ac circuit shown in Fig. 5.56(b), noting that the voltage gain is not affected by R1 and R2 and remains equal to Av =

−RC , 1 + RE gm

(5.225)

where Early effect is neglected. On the other hand, the input impedance is lowered to: Rin = [rπ + (β + 1)RE ]||R1 ||R2 ,

(5.226)

whereas the output impedance remains equal to RC if VA = ∞. As explained in Section 5.2.3, the use of emitter degeneration can effectively stabilize the bias point despite variations in β and IS . However, as evident from Eq. (5.225), degeneration also lowers the gain. Is it possible to apply degeneration to biasing but not to the signal? Illustrated in Fig. 5.57 is such a topology, where C 2 is large enough to act as a short circuit for signal frequencies of interest. We can

VCC R1

v in

C1

RC Q1

R2 RE

Figure 5.57

Use of capacitor to eliminate degeneration.

C2

5.3 Bipolar Amplifier Topologies

203

therefore write Av = −gmRC

(5.227)

Rin = rπ ||R1 ||R2

(5.228)

and

Rout = RC .

(5.229)

Example 5.34

Design the stage of Fig. 5.57 to satisfy the following conditions: IC = 1 mA, voltage drop across RE = 400 mV, voltage gain = 20 in the audio frequency range (20 Hz to 20 kHz), input impedance > 2 k. Assume β = 100, IS = 5 × 10−16 , and VCC = 2.5 V.

Solution

With IC = 1 mA ≈ IE , the value of RE is equal to 400 . For the voltage gain to remain unaffected by degeneration, the maximum impedance of C 1 must be much smaller than 1/gm = 26 .8 Occurring at 20 Hz, the maximum impedance must remain below roughly 0.1 × (1/gm) = 2.6 : 1 1 1 ≤ · for ω = 2π × 20 Hz. C 2ω 10 gm

(5.230)

C 2 ≥ 30,607 μF.

(5.231)

Thus,

(This value is unrealistically large, requiring modification of the design.) We also have |Av | = gmRC = 20,

(5.232)

RC = 520 .

(5.233)

obtaining Since the voltage across RE is equal to 400 mV and VBE = VT ln(IC /IS ) = 736 mV, we have VX = 1.14 V. Also, with a base current of 10 μA, the current flowing through R1 and R2 must exceed 100 μA to lower sensitivity to β: VCC > 10IB R1 + R 2

(5.234)

R1 + R2 < 25 k.

(5.235)

and hence Under this condition, VX ≈

R2 VCC = 1.14 V, R1 + R 2

(5.236)

yielding

8

R2 = 11.4 k

(5.237)

R1 = 13.6 k.

(5.238)

A common mistake here is to make the impedance of C 1 much less than RE .

204

Chapter 5 Bipolar Amplifiers We must now check to verify that this choice of R1 and R2 satisfies the condition Rin > 2 k. That is, Rin = rπ ||R1 ||R2 = 1.83 k.

(5.239) (5.240)

Unfortunately, R1 and R2 lower the input impedance excessively. To remedy the problem, we can allow a smaller current through R1 and R2 than 10IB , at the cost of creating more sensitivity to β. For example, if this current is set to 5IB = 50 μA and we still neglect IB in the calculation of VX , VCC > 5IB R1 + R 2

(5.241)

R1 + R2 < 50 k.

(5.242)

R2 = 22.8 k

(5.243)

R1 = 27.2 k,

(5.244)

Rin = 2.15 k.

(5.245)

and

Consequently,

giving

Exercise

Redesign the above stage for a gain of 10 and compare the results.

We conclude our study of the CE stage with a brief look at the more general case depicted in Fig. 5.58(a), where the input signal source exhibits a finite resistance and the output is tied to a load RL . The biasing remains identical to that of Fig. 5.56(a), but RS and RL lower the voltage gain vout /vin . The simplified ac circuit of Fig. 5.58(b) reveals Vin is attenuated by the voltage division between RS and the impedance seen at node X, R1 ||R2 ||[rπ + (β + 1)RE ], i.e., vX R1 ||R2 ||[rπ + (β + 1)RE ] = . vin R1 ||R2 ||[rπ + (β + 1)RE ] + RS

(5.246)

The voltage gain from vin to the output is given by vout vX vout = · vin vin vX =−

R1 ||R2 ||[rπ + (β + 1)RE ] RC ||RL . R1 ||R2 ||[rπ + (β + 1)RE ] + RS 1 + RE gm

As expected, lower values of R1 and R2 reduce the gain.

(5.247)

(5.248)

5.3 Bipolar Amplifier Topologies

205

VCC RS v in

C1

R1

RC

C2

Q1 R2

v out

RS

v out RL

X

Q1

R1 R2

v in

RC

RL

RE

RE (b)

(a)

v out

RS

X

R1 R2

v in

Q1

RC

RL

RE

(b)

Figure 5.58

(a) General CE stage, (b) simplified circuit, (c) Thevenin model of input network.

The above computation views the input network as a voltage divider. Alternatively, we can utilize a Thevenin equivalent to include the effect of RS , R1 , and R2 on the voltage gain. Illustrated in Fig. 5.58(c), the idea is to replace vin , RS and R1 ||R2 with vThev and RThev : vThev =

R1 ||R2 vin R1 ||R2 + RS

RThev = RS ||R1 ||R2 .

(5.249)

(5.250)

The resulting circuit resembles that in Fig. 5.43(a) and follows Eq. (5.185): Av = −

R1 ||R2 RC ||RL · , RThev R1 ||R2 + RS 1 + RE + gm β +1

(5.251)

where the second fraction on the right accounts for the voltage attenuation given by Eq. (5.249). The reader is encouraged to prove that Eqs. (5.248) and (5.251) are identical. The two approaches described above exemplify analysis techniques used to solve circuits and gain insight. Neither requires drawing the small-signal model of the transistor because the reduced circuits can be “mapped” into known topologies. Figure 5.59 summarizes the concepts studied in this section. 5.3.2 Common-Base Topology Following our extensive study of the CE stage, we now turn our attention to the “commonbase” (CB) topology. Nearly all of the concepts described for the CE configuration apply here as well. We therefore follow the same train of thought, but at a slightly faster pace. Given the amplification capabilities of the CE stage, the reader may wonder why we study other amplifier topologies. As we will see, other configurations provide different circuit properties that are preferable to those of the CE stage in some applications. The reader is encouraged to review Examples 5.2–5.4, their resulting rules illustrated in Fig. 5.7, and the possible topologies in Fig. 5.28 before proceeding further.

206

Chapter 5 Bipolar Amplifiers Headroom

RC

RC Gain

Av = –g m R C

rO R out

R in

R out

R1 C1

A v = –g m ( R C r O )

RC Q1 R1

RE

RC

R2

R2 RE

Figure 5.59

A v, R in

C2

Summary of concepts studied thus far.

Figure 5.60 shows the CB stage. The input is applied to the emitter and the output is sensed at the collector. Biased at a proper voltage, the base acts as ac ground and hence as a node “common” to the input and output ports. As with the CE stage, we first study the core and subsequently add the biasing elements. VCC RC Vout Q1

Output Sensed at Collector

Vb

v in Input Applied to Emitter

Figure 5.60

Common-base stage.

Analysis of CB Core How does the CB stage of Fig. 5.61(a) respond to an input signal?9 If Vin goes up by a small amount V, the base-emitter voltage of Q 1 decreases by the same amount because the base voltage is fixed. Consequently, the collector current falls by gm V, allowing Vout to rise by gm VRC . We therefore surmise that the small-signal voltage gain is equal to Av = gmRC .

(5.252)

Interestingly, this expression is identical to the gain of the CE topology. Unlike the CE stage, however, this circuit exhibits a positive gain because an increase in Vin leads to an increase in Vout . Let us confirm these results with the aid of the small-signal equivalent depicted in Fig. 5.61(b), where the Early effect is neglected. Beginning with the output node, we 9

Note that the topologies of Figs. 5.60 and 5.61(a) are identical even though Q 1 is drawn differently.

5.3 Bipolar Amplifier Topologies

207

VCC RC Vout

v out

g ΔV R C m

rπ

Q1

Vb

g vπ m

vπ

RC

v in

ΔV

V in (a)

Figure 5.61

(b)

(a) Response of CB stage to small input change, (b) small-signal model.

equate the current flowing through RC to gmvπ : −

vout = gmvπ , RC

(5.253)

obtaining vπ = −vout /(gmRC ). Considering the input node next, we recognize that vπ = −vin . It follows that vout = gmRC . vin

(5.254)

As with the CE stage, the CB topology suffers from trade-offs among the gain, the voltage headroom, and the I/O impedances. We first examine the circuit’s headroom limitations. How should the base voltage, Vb, in Fig. 5.61(a) be chosen? Recall that the operation in the active region requires VBE > 0 and VBC ≤ 0 (for npn devices). Thus, Vb must remain higher than the input by about 800 mV, and the output must remain higher than or equal to Vb. For example, if the dc level of the input is zero (Fig. 5.62), then the output must not fall below approximately 800 mV, i.e., the voltage drop across RC cannot exceed VCC − VBE . Similar to the CE stage limitation, this condition translates to Av =

=

IC · RC VT

(5.255)

VCC − VBE . VT

(5.256)

VCC RC

VCC – V BE ~0V

~800 mV 800 mV 0

Figure 5.62

t

V in

Voltage headroom in CB stage.

Vb

208

Chapter 5 Bipolar Amplifiers

Example 5.35

The voltage produced by an electronic thermometer is equal to 600 mV at room temperature. Design a CB stage to sense the thermometer voltage and amplify the change with maximum gain. Assume VCC = 1.8 V, IC = 0.2 mA, IS = 5 × 10−17 A, and β = 100.

Solution

Illustrated in Fig. 5.63(a), the circuit must operate properly with an input level of 600 mV. Thus, Vb = VBE + 600 mV = VT ln(IC /IS ) + 600 mV = 1.354 V. To avoid saturation, the collector voltage must not fall below the base voltage, thereby allowing a maximum voltage drop across RC equal to 1.8 V − 1.354 V = 0.446 V. Thus RC = 2.23 k. We can then write Av = gmRC

(5.257)

IC RC VT

(5.258)

= 17.2.

(5.259)

=

The reader is encouraged to repeat the problem with IC = 0.4 mA to verify that the maximum gain remains relatively independent of the bias current.10 VCC

VCC

RC

RC

R1

Vout Vb

Q1 V in

Vout Q1 V in

600 mV

Thermometer

R2

600 mV

(b)

(a)

Figure 5.63

IB

I1

(a) CB stage sensing an input, (b) bias network for base.

We must now generate Vb. A simple approach is to employ a resistive divider as depicted in Fig. 5.63(b). To lower sensitivity to β, we choose I1 ≈ 10IB ≈ 20 μA ≈ VCC /(R1 + R2 ). Thus, R1 + R2 = 90 k. Also, Vb ≈

R2 VCC R1 + R 2

(5.260)

and hence

Exercise

R2 = 67.7 k

(5.261)

R1 = 22.3 k.

(5.262)

Repeat the above example if the thermometer voltage is 300 mV. 10 This example serves only as an illustration of the CB stage. A CE stage may prove more suited to sensing a thermometer voltage.

5.3 Bipolar Amplifier Topologies

209

Let us now compute the I/O impedances of the CB topology so as to understand its capabilities in interfacing with preceding and following stages. The rules illustrated in Fig. 5.7 prove extremely useful here, obviating the need for small-signal equivalent circuits. Shown in Fig. 5.64(a), the simplified ac circuit reveals that Rin is simply the impedance seen looking into the emitter with the base at ac ground. From the rules in Fig. 5.7, we have Rin =

1 gm

(5.263)

if VA = ∞. The input impedance of the CB stage is therefore relatively low, e.g., 26 for IC = 1 mA (in sharp contrast to the corresponding value for a CE stage, β/gm).

VCC

VCC

RC

RC

Q1

IX

Q1

Vb

ac

VX

R in (a)

Figure 5.64

ΔV (b)

(a) Input impedance of CB stage, (b) response to a small change in input.

The input impedance of the CB stage can also be determined intuitively [Fig. 5.64(b)]. Suppose a voltage source VX tied to the emitter of Q 1 changes by a small amount V. The base-emitter voltage therefore changes by the same amount, leading to a change in the collector current equal to gmV. Since the collector current flows through the input source, the current supplied by VX also changes by gmV. Consequently, Rin = VX /IX = 1/gm. Does an amplifier with a low input impedance find any practical use? Yes, indeed. For example, many stand-alone high-frequency amplifiers are designed with an input resistance of 50 to provide “impedance matching” between modules in a cascade and the transmission lines (traces on a printed-circuit board) connecting the modules (Fig. 5.65).11 The output impedance of the CB stage is computed with the aid of Fig. 5.66, where the input voltage source is set to zero. We note that Rout = Rout1 ||RC , where Rout1 is the impedance seen at the collector with the emitter grounded. From the rules of Fig. 5.7, we have Rout1 = rO and hence Rout = rO ||RC

(5.264)

Rout = RC if VA = ∞.

(5.265)

or

11 If the input impedance of each stage is not matched to the characteristic impedance of the preceding transmission line, then “reflections” occur, corrupting the signal or at least creating dependence on the length of the lines.

210

Chapter 5 Bipolar Amplifiers

Figure 5.65

50-Ω Transmission Line

50-Ω Transmission Line

50 Ω

50 Ω

System using transmission lines.

Q1

RC

rO

R out1

R out

ac

Figure 5.66

Output impedance of CB stage.

Example 5.36

A common-base amplifier is designed for an input impedance of Rin and an output impedance of Rout . Neglecting the Early effect, determine the voltage gain of the circuit.

Solution

Since Rin = 1/gm and Rout = RC , we have Av =

Exercise

Rout . Rin

(5.266)

Compare this value with that obtained for the CE stage.

From Eqs. (5.256) and (5.266), we conclude that the CB stage exhibits a set of trade-offs similar to those depicted in Fig. 5.33 for the CE amplifier. It is instructive to study the behavior of the CB topology in the presence of a finite source resistance. Shown in Fig. 5.67, such a circuit suffers from signal attenuation from the input to node X, thereby providing a smaller voltage gain. More specifically, since the impedance seen looking into the emitter of Q 1 (with the base grounded) is

VCC RC v out RS v in

Figure 5.67

Q1 X

1 gm

CB stage with source resistance.

RS v in

X 1 gm

5.3 Bipolar Amplifier Topologies

211

equal to 1/gm (for VA = ∞), we have 1 gm

vX =

RS + =

1 gm

vin

(5.267)

1 vin . 1 + gmRS

(5.268)

We also recall from Eq. (5.254) that the gain from the emitter to the output is given by vout = gmRC . vX

(5.269)

It follows that gmRC vout = vin 1 + gmRS =

(5.270)

RC , 1 + RS gm

(5.271)

a result identical to that of the CE stage (except for a negative sign) if RS is viewed as an emitter degeneration resistor.

Example 5.37

A common-base stage is designed to amplify an RF signal received by a 50- antenna. Determine the required bias current if the input impedance of the amplifier must “match” the impedance of the antenna. What is the voltage gain if the CB stage also drives a 50- load? Assume VA = ∞.

Solution

Figure 5.68 depicts the amplifier12 and the equivalent circuit with the antenna modeled by a voltage source, vin , and a resistance, RS = 50 . For impedance matching,

VCC

VCC

RC

RC v out

Antenna

Q1

VB

v out Antenna

RS

Q1

VB

v in

Figure 5.68 12

(a) CB stage sensing a signal received by an antenna, (b) equivalent circuit.

The dots denote the need for biasing circuitry, as described later in this section.

212

Chapter 5 Bipolar Amplifiers it is necessary that the input impedance of the CB core, 1/gm, be equal to RS , and hence IC = gmVT

(5.272)

= 0.52 mA.

(5.273)

If RC itself is replaced by a 50- load, then Eq. (5.271) reveals that Av =

=

RC 1 + RS gm

(5.274)

1 . 2

(5.275)

The circuit is therefore not suited to driving a 50- load directly. Exercise

What is the voltage gain if a 50- resistor is also tied from the emitter of Q 1 to ground?

Another interesting point of contrast between the CE and CB stages relates to their current gains. The CB stage displays a current gain of unity because the current flowing into the emitter simply emerges from the collector (if the base current is neglected). On the other hand, as mentioned in Section 5.3.1, AI = β for the CE stage. In fact, in the preceding example, i in = vin /(RS + 1/gm), which upon flowing through RC , yields vout = RC vin /(RS + 1/gm). It is thus not surprising that the voltage gain does not exceed 0.5 if RC ≤ RS . As with the CE stage, we may desire to analyze the CB topology in the general case: with emitter degeneration, VA < ∞, and a resistance in series with the base [Fig. 5.69(a)]. Outlined in Problem 5.52, this analysis is somewhat beyond the scope of this book. Nevertheless, it is instructive to consider a special case where RB = 0 but VA < ∞, and we wish to compute the output impedance. As illustrated in Fig. 5.69(b), Rout is equal to RC in parallel with the impedance seen looking into the collector, Rout1 . But Rout1 is identical to the output resistance of an emitter-degenerated common emitter stage, i.e., Fig. 5.46, and hence given by Eq. (5.197): Rout1 = [1 + gm(RE ||rπ )]rO + (RE ||rπ ).

(5.276)

VCC RC v out RE

rO Q1

RB

VB

RE

rO

RC R out1

Q1

v in (a)

Figure 5.69

(b)

(a) General CB stage, (b) output impedance seen at different nodes.

R out2

5.3 Bipolar Amplifier Topologies VCC RC

VCC RC

v out

Q1 v in

VCC RC Vb

Q1

RE

RE

VCC RC

v out

Q1

Q1

R out

R out v in

RE

RE

(a)

Figure 5.70

213

(b)

(a) CE stage and (b) CB stage simplified for output impedance calculation.

It follows that Rout = RC ||{[1 + gm(RE ||rπ )]rO + (RE ||rπ )}.

(5.277)

The reader may have recognized that the output impedance of the CB stage is equal to that of the CE stage. Is this true in general? Recall that the output impedance is determined by setting the input source to zero. In other words, when calculating Rout , we have no knowledge of the input terminal of the circuit, as illustrated in Fig. 5.70 for CE and CB stages. It is therefore no coincidence that the output impedances are identical if the same assumptions are made for both circuits (e.g., identical values of VA and emitter degeneration).

Example 5.38

Old wisdom says “the output impedance of the CB stage is substantially higher than that of the CE stage.” This claim is justified by the tests illustrated in Fig. 5.71. If a constant current is injected into the base while the collector voltage is varied, IC exhibits a slope equal to rO−1 [Fig. 5.71(a)]. On the other hand, if a constant current is drawn from the emitter, IC displays much less dependence on the collector voltage. Explain why these tests do not represent practical situations.

IC VCC

IC

IC

VB

IB Q1

V1

V1

Q1

IC

IE V1

V1

(a)

(b)

Open

rπ

g vπ m

vπ

rO

rπ

vπ

g vπ m

R out

rO R out

Open (c)

(d)

Figure 5.71 (a) Resistance seens at collector with emitter grounded, (b) resistance seen at collector with an ideal current source in emitter, (c) small-signal model of (a), (d) smallsignal model of (b).

214

Chapter 5 Bipolar Amplifiers

Solution

The principal issue in these tests relates to the use of current sources to drive each stage. From a small-signal point of view, the two circuits reduce to those depicted in Figs. 5.71(c) and (d), with current sources IB and IE replaced with open circuits because they are constant. In Fig. 5.71(c), the current through rπ is zero, yielding gmvπ = 0 and hence Rout = rO . On the other hand, Fig. 5.71(d) resembles an emitter-degenerated stage (Fig. 5.46) with an infinite emitter resistance, exhibiting an output resistance of Rout = [1 + gm(RE ||rπ )]rO + (RE ||rπ )

(5.278)

= (1 + gmrπ )rO + rπ

(5.279)

≈ βrO + rπ ,

(5.280)

which is, of course, much greater than rO . In practice, however, each stage may be driven by a voltage source having a finite impedance, making the above comparison irrelevant. Exercise

Repeat the above example if a resistor of value R1 is inserted in series with the emitter. Another special case of the topology shown in Fig. 5.69(a) occurs if VA = ∞ but RB > 0. Since this case does not reduce to any of the configurations studied earlier, we employ the small-signal model shown in Fig. 5.72 to study its behavior. As usual, we write gmvπ = −vout /RC and hence vπ = −vout /(gmRC ). The current flowing through rπ (and RB ) is then equal to vπ /rπ = −vout /(gmrπ RC ) = −vout /(βRC ). Multiplying this current by RB + rπ , we obtain the voltage at node P: vP = −

=

−vout (RB + rπ ) βRC

(5.281)

vout (RB + rπ ). βRC

(5.282)

We also write a KCL at P: vπ vP − vin + gmvπ = ; rπ RE

RB

v out

rπ

g vπ m

vπ P

v in

Figure 5.72

(5.283)

RE

CB stage with base resistance.

RC

5.3 Bipolar Amplifier Topologies

215

that is,

vout (RB + rπ ) − vin −vout 1 βRC + gm = . rπ gmRC RE

(5.284)

It follows that vout βRC = . vin (β + 1)RE + RB + rπ

(5.285)

Dividing the numerator and denominator by β + 1, we have vout ≈ vin

RC . RB 1 RE + + β + 1 gm

(5.286)

As expected, the gain is positive. Furthermore, this expression is identical to that in Eq. (5.185) for the CE stage. Figure 5.73 illustrates the results, revealing that, except for a negative sign, the two stages exhibit equal gains. Note that RB degrades the gain and is not added to the circuit deliberately. As explained later in this section, RB may arise from the biasing network.

VCC

VCC

RC

RC v out

RB

RB

Q1

v in

v out Q1 RE

RE v in

Figure 5.73

Comparison of CE and CB stages with base resistance.

Let us now determine the input impedance of the CB stage in the presence of a resistance in series with the base, still assuming VA = ∞. From the small-signal equivalent circuit shown in Fig. 5.74, we recognize that rπ and RB form a voltage divider, RB

v out

rπ

vX

Figure 5.74

vπ

g vπ m

RC

iX

Input impedance of CB stage with base resistance.

216

Chapter 5 Bipolar Amplifiers thereby producing13 vπ = −

rπ vX . r π + RB

(5.287)

Moreover, KCL at the input node gives vπ + gmvπ = −i X . rπ Thus,

(5.288)

1 −rπ + gm vX = −i X rπ r π + RB

(5.289)

and r π + RB vX = iX β +1 ≈

(5.290)

RB 1 . + gm β + 1

(5.291)

Note that Rin = 1/gm if RB = 0, an expected result from the rules illustrated in Fig. 5.7. Interestingly, the base resistance is divided by β + 1 when “seen” from the emitter. This is in contrast to the case of emitter degeneration, where the emitter resistance is multiplied by β + 1 when seen from the base. Figure 5.75 summarizes the two cases. Note that these results remain independent of RC if VA = ∞. RB

VA =

Q1 r π + (β + 1) R E

RB 1 + gm β + 1

Figure 5.75

Example 5.39

VA =

Q1

RE

Impedance seen at the emitter or base of a transistor.

Determine the impedance seen at the emitter of Q 2 in Fig. 5.76(a) if the two transistors are identical and VA = ∞. VCC RB

RC Q1

v out

VCC RB 1 + g m1 β + 1

Q2 R eq

v out Q2

RX

(a)

Figure 5.76

RC

RX (b)

(a) Example of CB stage, (b) simplified circuit.

Alternatively, the current through rπ + RB is equal to vX /(rπ + RB ), yielding a voltage of −rπ vX /(rπ + RB ) across rπ .

13

5.3 Bipolar Amplifier Topologies Solution

217

The circuit employs Q 2 as a common-base device, but with its base tied to a finite series resistance equal to that seen at the emitter ofQ 1 . Thus, we must first obtain the equivalent resistance Req , which from Eq. (5.291) is simply equal to Req =

1 RB + . gm1 β +1

(5.292)

Reducing the circuit to that shown in Fig. 5.76(b), we have RX =

Req 1 + gm2 β +1

(5.293)

1 1 RB 1 = + + . gm2 β + 1 gm1 β +1 Exercise

(5.294)

What happens if a resistor of value R1 is placed in series with the collector of Q 1 ?

CB Stage with Biasing Having learned the small-signal properties of the CB core, we now extend our analysis to the circuit including biasing. An example proves instructive at this point.

Example 5.40

The student in Example 5.31 decides to incorporate ac coupling at the input of a CB stage to ensure the bias is not affected by the signal source, drawing the design as shown in Fig. 5.77. Explain why this circuit does not work.

VCC RC Vout Q1 V in

Figure 5.77

C1

Vb

CB stage lacking bias current.

Solution

Unfortunately, the design provides no dc path for the emitter current of Q 1 , forcing a zero bias current and hence a zero transconductance. The situation is similar to the CE counterpart in Example 5.5, where no base current can be supported.

Exercise

In what region does Q 1 operate if Vb = VCC ?

218

Chapter 5 Bipolar Amplifiers

Example 5.41

Somewhat embarrassed, the student quickly connects the emitter to ground so that VBE = Vb and a reasonable collector current can be established (Fig. 5.78). Explain why “haste makes waste.” VCC RC Vout Q1

Figure 5.78

Vb

C1

V in

CB stage with emitter shorted to ground.

Solution

As in Example 5.6, the student has shorted the signal to ac ground. That is, the emitter voltage is equal to zero regardless of the value of vin , yielding vout = 0.

Exercise

Does the circuit operate better if Vb is raised?

The above examples imply that the emitter can remain neither open nor shorted to ground, thereby requiring some bias element. Shown in Fig. 5.79(a) is an example in which RE provides a path for the bias current at the cost of lowering the input impedance. We recognize that Rin now consists of two parallel components: (1) 1/gm, seen looking “up” into the emitter (with the base at ac ground) and (2) RE , seen looking “down.” Thus, Rin =

1 ||RE . gm

(5.295)

As with the input biasing network in the CE stage (Fig. 5.58), the reduction in Rin manifests itself if the source voltage exhibits a finite output resistance. Depicted in Fig. 5.79(b), such a circuit attenuates the signal, lowering the overall voltage gain.

VCC

VCC

RC

RC v out

1 gm

v in

C1

v out

Q1

Q1 Vb

RE

RE

v in

R S C1

RE R in

(a)

Figure 5.79

Vb

X

(b)

(a) CB stage with biasing, (b) inclusion of source resistance.

5.3 Bipolar Amplifier Topologies

219

Following the analysis illustrated in Fig. 5.67, we can write vX Rin = vin Rin + RS

=

=

(5.296)

1 ||RE gm

(5.297)

1 ||RE + RS gm 1 . 1 + (1 + gmRE )RS

(5.298)

Since vout /vX = gmRC , vout 1 = · gmRC . vin 1 + (1 + gmRE )RS

(5.299)

As usual, we have preferred solution by inspection over drawing the small-signal equivalent. The reader may see a contradiction in our thoughts: on the one hand, we view the low input impedance of the CB stage as a useful property; on the other hand, we consider the reduction of the input impedance due to RE undesirable. To resolve this apparent contradiction, we must distinguish between the two components 1/gm and RE , noting that the latter shunts the input source current to ground, thus “wasting” the signal. As shown in Fig. 5.80, i in splits two ways, with only i 2 reaching RC and contributing to the output signal. If RE decreases while 1/gm remains constant, then i 2 also falls.14 Thus, reduction of Rin due to RE is undesirable. By contrast, if 1/gm decreases while RE remains constant, then i 2 rises. For RE to affect the input impedance negligibly, we must have RE

1 gm

(5.300)

VCC RC v out i in

v in

Figure 5.80

R S C1

Q1 i2 i1

Vb RE

Small-signal input current components in a CB stage.

and hence IC RE VT . That is, the dc voltage drop across RE muts be much greater than VT . 14

In the extreme case, RE = 0 (Example 5.41) and i 2 = 0.

(5.301)

220

Chapter 5 Bipolar Amplifiers How is the base voltage, Vb, generated? We can employ a resistive divider similar to that used in the CE stage. Shown in Fig. 5.81(a), such a topology must ensure I1 IB to minimize sensitivity to β, yielding Vb ≈

R2 VCC . R1 + R 2

(5.302)

However, recall from Eq. (5.286) that a resistance in series with the base reduces the voltage gain of the CB stage. Substituting a Thevenin equivalent for R1 and R2 as depicted in Fig. 5.81(b), we recognize that a resistance of RThev = R1 ||R2 now appears in series with the base. For this reason, a “bypass capacitor” is often tied from the base to ground, acting as a short circuit at frequencies of interest [Fig. 5.81(c)].

VCC RC

R1 IB

Q1

VCC

I1

VCC

RC

Vb

RC R Thev

Q1

Q1 V Thev

R2

C1 R E

RE (a)

R1

R2 RE

(b)

CB

(c)

Figure 5.81 (a) CB stage with base bias network, (b) use of Thevenin equivalent, (c) effect of bypass capacitor.

Example 5.42

Design a CB stage (Fig. 5.82) for a voltage gain of 10 and an input impedance of 50 . Assume IS = 5 × 10−16 A, VA = ∞, β = 100, and VCC = 2.5 V. VCC RC R1

V out V in

C1

RE I C

Figure 5.82 Solution

Vb

Q1 R2 RE

CB

Example of CB stage with biasing.

We begin by selecting RE 1/gm, e.g., RE = 500 , to minimize the undesirable effect of RE . Thus, Rin ≈

1 = 50 gm

(5.303)

and hence IC = 0.52 mA.

(5.304)

5.3 Bipolar Amplifier Topologies

221

If the base is bypassed to ground Av = gmRC ,

(5.305)

RC = 500 .

(5.306)

yielding

We now determine the base bias resistors. Since the voltage drop across RE is equal to 500 × 0.52 mA = 260 mV and VBE = VT ln(IC /IS ) = 899 mV, we have Vb = IE RE + VBE = 1.16 V.

(5.307) (5.308)

Selecting the current through R1 and R2 to be 10IB = 52 μA, we write Vb ≈

R2 VCC . R1 + R 2

VCC = 52 μA. R1 + R 2

(5.309) (5.310)

It follows that R1 = 25.8 k

(5.311)

R2 = 22.3 k.

(5.312)

The last step in the design is to compute the required values ofC 1 andCB according to the signal frequency. For example, if the amplifier is used at the receiver front end of a 900MHz cellphone, the impedances ofC 1 andCB must be sufficiently small at this frequency. Appearing in series with the emitter of Q 1 , C 1 plays a role similar to RS in Fig. 5.67 and Eq. (5.271). Thus, its impedance, |C 1 ω|−1 , must remain much less than 1/gm = 50 . In high-performance applications such as cellphones, we may choose |C 1 ω|−1 = (1/gm)/20 to ensure negligible gain degradation. Consequently, for ω = 2π × (900 MHz): C1 =

20gm ω

= 71 pF.

(5.313) (5.314)

Since the impedance of CB appears in series with the base and plays a role similar to the term RB /(β + 1) in Eq. (5.286), we require that 1 1 1 1 (5.315) = β + 1 CB ω 20 gm and hence CB = 0.7 pF.

(5.316)

(A common mistake is to make the impedance of CB negligible with respect to R1 ||R2 rather than with respect to 1/gm.) Exercise

Design the above circuit for an input impedance of 100 .

222

Chapter 5 Bipolar Amplifiers 5.3.3 Emitter Follower Another important circuit topology is the emitter follower (also called the “commoncollector” stage). The reader is encouraged to review Examples 5.2–5.3, rules illustrated in Fig. 5.7, and the possible topologies in Fig. 5.28 before proceeding further. For the sake of brevity, we may also use the term “follower” to refer to emitter followers in this chapter. Shown in Fig. 5.83, the emitter follower senses the input at the base of the transistor and produces the output at the emitter. The collector is tied to VCC and hence ac ground. We first study the core and subsequently add the biasing elements. VCC V in Input Applied to Base

Figure 5.83

Output Sensed at Emitter

Q1

Vout RE

Emitter follower.

Emitter Follower Core How does the follower in Fig. 5.84(a) respond to a change in Vin ? If Vin rises by a small amount Vin , the base-emitter voltage ofQ 1 tends to increase, raising the collector and emitter currents. The higher emitter current translates to a greater drop across RE and hence a higher Vout . From another perspective, if we assume, for example, Vout is constant, then VBE must rise and so must IE , requiring that Vout go up. Since Vout changes in the same direction as Vin , we expect the voltage gain to be positive. Note that Vout is always lower than Vin by an amount equal to VBE , and the circuit is said to provide “level shift.” VCC V in

V in1 + ΔV in

Q1

V in1 Vout

RE

(a)

Figure 5.84

V BE1

V out1 + ΔV out

V BE2

V out1 (b)

(a) Emitter follower sensing an input change, (b) response of the circuit.

Another interesting and important observation here is that the change in Vout cannot be larger than the change in Vin . Suppose Vin increases from Vin1 to Vin1 + Vin and Vout from Vout1 to Vout1 + Vout [Fig. 5.84(b)]. If the output changes by a greater amount than the input, Vout > Vin , then VBE2 must be less than VBE1 . But this means the emitter current also decreases and so does IE RE = Vout , contradicting the assumption that Vout has increased. Thus, Vout < Vin , implying that the follower exhibits a voltage gain less than unity.15 15

In an extreme case described in Example 5.43, the gain becomes equal to unity.

5.3 Bipolar Amplifier Topologies

rπ

v in

223

g vπ m

vπ

v out RE

Figure 5.85

Small-signal model of emitter follower.

The reader may wonder if an amplifier with a subunity gain has any practical value. As explained later, the input and output impedances of the emitter follower make it a particularly useful circuit for some applications. Let us now derive the small-signal properties of the follower, first assuming VA = ∞. Shown in Fig. 5.85, the equivalent circuit yields vout vπ + gmvπ = rπ RE

(5.317)

vout rπ · . β + 1 RE

(5.318)

and hence vπ = We also have vin = vπ + vout .

(5.319)

Substituting for vπ from (5.318), we obtain vout = vin

≈

1 1+

rπ 1 · β + 1 RE

RE RE +

1 gm

.

(5.320)

(5.321)

The voltage gain is therefore positive and less than unity. Example 5.43

In integrated circuits, the follower is typically realized as shown in Fig. 5.86. Determine the voltage gain if the current source is ideal and VA = ∞.

VCC V in

Q1 Vout I1

Figure 5.86

Follower with current source.

224

Chapter 5 Bipolar Amplifiers

Solution

Since the emitter resistor is replaced with an ideal current source, the value of RE in Eq. (5.321) must tend to infinity, yielding Av = 1.

(5.322)

This result can also be derived intuitively. A constant current source flowing through Q 1 requires that VBE = VT ln(IC /IS ) remain constant. Writing Vout = Vin − VBE , we recognize that Vout exactly follows Vin if VBE is constant. Exercise

Repeat the above example if a resistor of value R1 is placed in series with the collector. Equation (5.321) suggests that the emitter follower acts as a voltage divider, a perspective that can be reinforced by an alternative analysis. Suppose, as shown in Fig. 5.87(a), we wish to model vin and Q 1 by a Thevenin equivalent. The Thevenin voltage is given by the open-circuit output voltage produced by Q 1 [Fig. 5.87(b)], as if Q 1 operates with RE = ∞ (Example 5.43). Thus, vThev = vin . The Thevenin resistance is obtained by setting the input to zero [Fig. 5.87(c)] and is equal to 1/gm. The circuit of Fig. 5.87(a) therefore reduces to that shown in Fig. 5.87(d), confirming operation as a voltage divider. VCC

VCC

Q1

Q1

v in

v out

v in

v out = v in

RE (a)

(b)

VCC

R Thev =

Q1

R Thev

v out RE

v Thev = v in

(c)

1 gm

(d)

Figure 5.87 (a) Emitter follower stage, (b) Thevenin voltage, (c) Thevenin resistance, (d) simplified circuit.

Example 5.44

Determine the voltage gain of a follower driven by a finite source impedance of RS [Fig. 5.88(a)] if VA = ∞.

Solution

We model vin , RS , and Q 1 by a Thevenin equivalent. The reader can show that the opencircuit voltage is equal to vin . Furthermore, the Thevenin resistance [Fig. 5.88(b)] is given by Eq. (5.291) as RS /(β + 1) + 1/gm. Figure 5.88(c) depicts the equivalent circuit, revealing that vout = vin

RE . RS 1 RE + + β + 1 gm

(5.323)

5.3 Bipolar Amplifier Topologies

RS

VCC

RS

Q1

v in

225

VCC Q1

v out RE R Thev (b)

(a)

RS 1 + gm β + 1

v out RE

v Thev = v in

(c)

Figure 5.88 (a) Follower with source impedance, (b) Thevenin resistance seen at emitter, (c) simplified circuit.

This result can also be obtained by solving the small-signal equivalent circuit of the follower. Exercise

What happens if RE = ∞?

In order to appreciate the usefulness of emitter followers, let us compute their input and output impedances. In the equivalent circuit of Fig. 5.89(a), we have i X rπ = vπ . Also, the current i X and gmvπ flow through RE , producing a voltage drop equal to (i X + gmvπ )RE . Adding the voltages across rπ and RE and equating the result to vX , we have vX = vπ + (i X + gmvπ )RE = i X rπ + (i X + gmi X rπ )RE ,

(5.324) (5.325)

and hence vX = rπ + (1 + β)RE . iX

(5.326)

This expression is identical to that in Eq. (5.162) derived for a degenerated CE stage. This is, of course, no coincidence. Since the input impedance of the CE topology is independent of the collector resistor (for VA = ∞), its value remains unchanged if RC = 0, which is the case for an emitter follower [Fig. 5.89(b)]. The key observation here is that the follower “transforms” the load resistor, RE , to a much larger value, thereby serving as an efficient “buffer.” This concept can be illustrated by an example.

226

Chapter 5 Bipolar Amplifiers VCC

iX rπ

vX

g vπ m

vπ

Q1 R in

RE

Q1 R in

RE

(a)

Figure 5.89

Example 5.45

VCC 0

RC

RE

(b)

(a) Input impedance of emitter follower, (b) equivalence of CE and follower stages.

A CE stage exhibits a voltage gain of 20 and an output resistance of 1 k. Determine the voltage gain of the CE amplifier if (a) The stage drives an 8- speaker directly. (b) An emitter follower biased at a current of 5 mA is interposed between the CE stage and the speaker. Assume β = 100, VA = ∞, and the follower is biased with an ideal current source.

Solution

(a) As depicted in Fig. 5.90(a), the equivalent resistance seen at the collector is now given by the parallel combination of RC and the speaker impedance, Rsp , reducing the gain from 20 to 20 × (RC ||8 )/RC = 0.159. The voltage gain therefore degrades drastically.

1 kΩ

VCC

1 kΩ

RC

VCC RC

R sp Q1 v in

Q2

C1

Q1 v in

(a)

Figure 5.90

R sp R in1

I1

C1

(b)

(a) CE stage and (b) two-stage circuit driving a speaker.

(b) From the arrangement in Fig. 5.90(b), we note that Rin1 = rπ 2 + (β + 1)Rsp = 1328 .

(5.327) (5.328)

Thus, the voltage gain of the CE stage drops from 20 to 20 × (RC ||Rin1 )/ RC = 11.4, a substantial improvement over case (a). Exercise

Repeat the above example if the emitter follower is biased at a current of 10 mA.

We now calculate the output impedance of the follower, assuming the circuit is driven by a source impedance RS [Fig. 5.91(a)]. Interestingly, we need not resort to a small-signal model here as Rout can be obtained by inspection. As illustrated in Fig. 5.91(b), the output

5.3 Bipolar Amplifier Topologies VCC

RS

VCC

RS

Q1

227

Q1 RS 1 + gm β + 1

RE R out

RE RE

(a)

Figure 5.91

(b)

(a) Output impedance of a follower, (b) components of output resistance.

resistance can be viewed as the parallel combination of two components: one seen looking “up” into the emitter and another looking “down” into RE . From Fig. 5.88, the former is equal to RS /(β + 1) + 1/gm, and hence RS 1 Rout = ||RE . (5.329) + β + 1 gm This result can also be derived from the Thevenin equivalent shown in Fig. 5.88(c) by setting vin to zero. Equation (5.329) reveals another important attribute of the follower: the circuit transforms the source impedance, RS , to a much lower value, thereby providing higher “driving” capability. We say the follower operates as a good “voltage buffer” because it displays a high input impedance (like a voltmeter) and a low output impedance (like a voltage source). Effect of Transistor Output Resistance Our analysis of the follower has thus far neglected the Early effect. Fortunately, the results obtained above can be readily modified to reflect this nonideality. Figure 5.92 illustrates a key point that facilitates the analysis: in small-signal operation, rO appears in parallel with RE . We can therefore rewrite Eqs. (5.323), (5.326) and (5.329) as Av =

RE ||rO RS 1 RE ||rO + + β + 1 gm

(5.330)

Rin = rπ + (β + 1)(RE ||rO ) Rout =

(5.331)

1 RS ||RE ||rO . + β + 1 gm

(5.332)

VCC RS v in

Q1

RS

rO v in

RE

Figure 5.92

Follower including transistor output resistance.

Q1 RE

rO

228

Chapter 5 Bipolar Amplifiers

Example 5.46

Determine the small-signal properties of an emitter follower using an ideal current source (as in Example 5.43) but with a finite source impedance RS .

Solution

Since RE = ∞, we have

rO 1 RS + rO + β + 1 gm

Av =

(5.333)

Rin = rπ + (β + 1)rO RS 1 Rout = ||rO . + β + 1 gm

Also, gmrO 1, and hence

Av ≈

(5.334) (5.335)

rO

(5.336)

RS β +1 Rin ≈ (β + 1)rO . rO +

(5.337)

We note that Av approaches unity if RS (β + 1)rO , a condition typically valid. Exercise

How are the results modified if RE < ∞? The buffering capability of followers is sometimes attributed to their “current gain.” Since a base current i B results in an emitter current of (β + 1)i B , we can say that for a current i L delivered to the load, the follower draws only i L /(β + 1) from the source voltage (Fig. 5.93). Thus, vX sees the load impedance multiplied by (β + 1). iL

β+1 vX

VCC Q1

iL Load

Figure 5.93

Current amplification in a follower.

Emitter Follower with Biasing The biasing of emitter followers entails defining both the base voltage and the collector (emitter) current. Figure 5.94(a) depicts an example similar to the scheme illustrated in Fig. 5.19 for the CE stage. As usual, the current flowing through R1 and R2 is chosen to be much greater than the base current. VCC

VCC

R1 v in

C1

RB X

Q1 Vout

R2

v in

C1

IB

Figure 5.94

Vout

Y

RE

(a)

Q1

X

RE

(b)

Biasing a follower by means of (a) resistive divider, (b) single base resistor.

5.3 Bipolar Amplifier Topologies

229

It is interesting to note that, unlike the CE topology, the emitter follower can operate with a base voltage near VCC . This is because the collector is tied to VCC , allowing the same voltage for the base without driving Q 1 into saturation. For this reason, followers are often biased as shown in Fig. 5.94(b), where RB IB is chosen much less than the voltage drop across RE , thus lowering the sensitivity to β. The following example illustrates this point. Example 5.47

The follower of Fig. 5.94(b) employs RB = 10 k and RE = 1 k. Calculate the bias current and voltages if IS = 5 × 10−16 A, β = 100, and VCC = 2.5 V. What happens if β drops to 50?

Solution

To determine the bias current, we follow the iterative procedure described in Section 5.2.3. Writing a KVL through RB , the base-emitter junction, and RE gives RB IC + VBE + RE IC = VCC , β

(5.338)

which, with VBE ≈ 800 mV, leads to IC = 1.545 mA.

(5.339)

It follows that VBE = VT ln(IC /IS ) = 748 mV. Using this value in Eq. (5.338), we have IC = 1.593 mA,

(5.340)

a value close to that in Eq. (5.339) and hence relatively accurate. Under this condition, IB RB = 159 mV whereas RE IC = 1.593 V. Since IB RB RE IC , we expect that variation of β and hence IB RB negligibly affects the voltage drop across RE and hence the emitter and collector currents. As a rough estimate, for β = 50, IB RB is doubled (≈ 318 mV), reducing the drop across RE by 159 mV. That is, IE = (1.593 V − 0.159 V)/1 k = 1.434 mA, implying that a twofold change in β leads to a 10% change in the collector current. The reader is encouraged to repeat the above iterations with β = 50 and determine the exact current. Exercise

If RB is doubled, is the circuit more or less sensitive to the variation in β?

As manifested by Eq. (5.338), the topologies of Fig. 5.94 suffer from supplydependent biasing. In integrated circuits, this issue is resolved by replacing the emitter resistor with a constant current source (Fig. 5.95). Now, since IEE is constant, so are VBE and RB IB . Thus, if VCC rises, so do VX and VY , but the bias current remains constant. VCC RB v in

Figure 5.95

C1

Q1 C2

RL

Capacitive coupling at input and output of a follower.

230

Chapter 5 Bipolar Amplifiers

PROBLEMS 5.1. An antenna modeled as a Thevenin equivalent having a voltage 15 cos 2π × 103 t and output resistance of 50 . Determine the average power delivered to a load resistance of 15 .

D1

5.2. Determine the small-signal input resistance of the circuits shown in Fig. 5.96. Assume all diodes are forward-biased. (Recall from Chapter 3 that each diode behaves as a linear resistance if the voltage and current changes are small.)

D1 R1

R in

D2

R1

R in

D2

R1

R in D1

(a)

(b)

(c)

Figure 5.96

5.3. Compute the input resistance of the circuits depicted in Fig. 5.97. Assume VA =∞. 5.4. Compute the output resistance of the circuits depicted in Fig. 5.98.

VCC

5.5. Determine the input impedance of the circuits depicted in Fig. 5.99. Assume VA = ∞.

VCC

VCC

R1

Q1 Q1

R in

VCC

R2

R in

R1

Rin

Q2

Rin

R1

Q1 R2

Q2

R1

(a)

(b)

(c)

(d)

Figure 5.97

Rout

VB

R1 RE

Rout

RB Rout

VB

RE RE

(a) Figure 5.98

(b)

(c)

Problems VCC

VCC

231

VCC

Ideal

Q1

Q1 R in

Q1

R1

R in

VB

R in

Q2

R1 (a)

VB

R1 (b)

(c)

VCC

VCC

Q2

Q2 R in

Q1

Q1

R in (d)

Figure 5.99

5.6. Compute the output impedance of the circuits shown in Fig. 5.100. R out

VCC Q1

Q2

R out

(a)

5.7. Compute the bias point of the circuits depicted in Fig. 5.101. Assume β = 100, IS = 6 × 10−16 A, and VA = ∞. 5.8. Construct the small-signal equivalent of each of the circuits in Problem 5.7.

Q1

RC

(e)

*5.9. Calculate the bias point of the circuits shown in Fig. 5.102. Assume β = 100, IS = 5 × 10−16 A, and VA = ∞.

VB (b)

Figure 5.100 V CC = 2.5 V 100 k Ω

500 Ω

V CC = 2.5 V 100 k Ω

1 kΩ

Q1

V CC = 2.5 V 100 k Ω

Q1

Q1 0.5 V

Q2 (a)

Figure 5.101

(b)

V CC = 2.5 V 34 k Ω

3 kΩ

Q1

16 k Ω

(c)

V CC = 2.5 V 9 kΩ

500 Ω

Q1

16 k Ω

Q2

Figure 5.102

(a)

1 kΩ

(b)

V CC = 2.5 V 12 k Ω

1 kΩ

Q1

13 k Ω 0.5 V

(c)

232

Chapter 5 Bipolar Amplifiers

5.10. In the circuit of Fig. 5.103, β = 100, VA = ∞. (a) If the collector current of Q1 is equal to 1 mA, calculate the value of I S . (b) If Q1 is biased at the edge of saturation, calculate the value of I S . VCC = 2.5 V 40 kΩ

1 kΩ

30 kΩ

500 Ω

VCC = 2 V

1 kΩ

24 kΩ

16 kΩ Figure 5.106

5.14. The circuit of Fig. 5.107 is designed for a collector current of 0.5 mA. Assume β = 100, IS = 5 × 10−15 A and VA = ∞. Determine the required value of RE . VCC = 3 V

20 k Ω

R1 RC

10 k Ω

R2

3 kΩ

Figure 5.103

5.11. Consider the circuit of Fig. 5.104, where β = 100, IS = 5 × 10−15 A and VA = ∞. Calculate the value of IC and VC E .

RE

Figure 5.107

VCC = 2.5 V 42 kΩ

1 kΩ

18 kΩ

500 Ω

5.15. In the circuit of Fig. 5.108, determine the value of R1 that guarantees operation of Q1 in the active mode. Assume β = 100, IS = 10−16 A and VA = ∞. VCC = 2.5 V

30 k Ω

2 kΩ

Figure 5.104

5.12. For the circuit of Fig. 5.105 where β = 100, IS = 5 × 10−15 A and VA = ∞, what is the minimum value of RB that guarantees the operation of Q1 in the active mode? 2.5 V 2 kΩ

R2 Figure 5.108

5.16. In the circuit of Fig. 5.109, β1 = β2 = 100, IS1 = IS2 = 4 × 10−15 A and VA = ∞. Determine the operating point of the transistor and voltage gain.

RB

1.5 V

VCC = 2.5 V

10 k Ω

R1

100 Ω Q1

Figure 5.105

15 k Ω

5.13. For the CE stage depicted in Fig. 5.106, determine the gain, input, and output impedance.

Q1

R2

Figure 5.109

Q2

Problems VCC = 2.5 V

5.17. Consider the circuit of Fig. 5.110, where IS1 = 2IS2 = 3IS3 = 5 × 10−15 A, β1 = β2 = β3 = 100, and VA = ∞. Determine collector currents of Q 1 , Q 2 and Q 3 .

1 kΩ

RB

500 Ω

Rp

VCC = 2.5 V

13 k Ω

233

Q1

1 kΩ Q1

Figure 5.113

Q2

12 k Ω Q3

5.21. Consider the circuit shown in Fig. 5.114, where IS = 6 × 10−16 A, β = 100, and VA = ∞. Calculate the operating point of Q 1 . V CC = 2.5 V 500 Ω

20 k Ω

Figure 5.110

5.18. The circuit of Fig. 5.111 must be biased with a collector current of 0.5 mA. Compute the required value of RB if β = 100, IS = 5 × 10−15 A and VA = ∞.

Q1 400 Ω

Figure 5.114

VCC = 2.5 V RB

1 kΩ

5.22. In the circuit of Fig. 5.115, β = 100, IS = 5 × 10−15 A and of VA = ∞. Determine the operating point of Q1 . VCC = 3 V

10 k Ω

Figure 5.111

1 kΩ VX

5.19. In the circuit of Fig. 5.112, if β = 100, IS = 5 × 10−15 A, determine VX and IC .

500 Ω

VCC = 2.5 V

10 k Ω

300 Ω

Figure 5.112

5.20. Due to a manufacturing error, a parasitic resistor, RP , has appeared in series with the collector of Q 1 in Fig. 5.113. What is the minimum allowable value of RB if the base-collector forward bias must not exceed 200 mV? Assume IS = 3 × 10−16 A, β = 100, and VA = ∞.

Figure 5.115

5.23. In the circuit of Fig. 5.116, IS1 = IS2 = 4 × 10−16 A, β1 = β2 = 100 and VA = ∞. Calculate VB such thatQ 1 carries a collector current of 1 mA. VCC = 3 V

300 Ω Q1 VB

Q2

500 Ω Figure 5.116

234

Chapter 5 Bipolar Amplifiers

5.24. Determine the bias point of circuit shown in Fig. 5.117 given IS = 9 × 10−16 A, β = 100 and VA = ∞.

VCC = 2.5 V

5 kΩ

Q1

VCC = 3 V

RB

1 kΩ

1 kΩ 40 k Ω

Figure 5.120

200 Ω

5.28. If β = 100 and VA = ∞, what value of I S yields a collector current of 1 mA in Fig. 5.121?

Figure 5.117

5.25. Calculate the bias point of the circuits shown in Fig. 5.118. Assume βnpn = 2βpnp = 100, IS = 9 × 10−16 A, and VA = ∞. 32 k Ω

VCC = 2.5 V

1 kΩ

VCC = 2.5 V Q1

Q1 18 k Ω

VCC = 3 V

25 k Ω 32 k Ω

Q2

100 Ω

1 kΩ

1 kΩ

Figure 5.121 18 k Ω

*5.29. The topology depicted in Fig. 5.122(a) is called a “VBE multiplier.” (The npn counterpart has a similar topology.) Construct(a) (b) ing the circuit shown in Fig. 5.122(b), Figure 5.118 determine the collector-emitter voltage of Q 1 if the base current is negligible. (The npn 5.26. Calculate the value of RE in Fig. 5.119 such counterpart can also be used.) that Q 1 sustains a reverse bias of 300 mV across its base-collector junction. Assume β = 50, IS = 8 × 10−16 A, and VA = ∞. VCC What happens if the value of RE is halved? VCC = 2.5 V 10 k Ω

RE Q1

10 k Ω

R1

R1 Q1

R2

Q1 R2

5 kΩ

Figure 5.119

R3 (a)

(b)

Figure 5.122

5.27. We have chosen RB in Fig. 5.120 to place Q 1 at the edge of saturation. But the actual value of this resistor can vary by ±5%. Determine the forward- or reversebias across the base-collector junction at these two extremes. Assume β = 50, IS = 8 × 10−16 A, and VA = ∞.

5.30. We wish to design the CE stage of Fig. 5.123 for a voltage gain of 20. What is the minimum allowable supply voltage if Q 1 must remain in the active mode? Assume VA = ∞ and VBE = 0.8 V.

Problems

and no Early effect. Compute the voltage gain for a bias current of 1 mA.

VCC = 2.5 V

50 k Ω

V in

Vout

VCC

Q1

RC

Figure 5.123

VCC = 3 V

1 kΩ

1 kΩ

Vout

V in

5.31. The circuit of Fig. 5.124 must be designed for maximum gain while maintaining Q1 in the active mode. If VA = 10 V and VBE = 0.8 V, calculate the required bias current.

Vin

235

Q1

Figure 5.125

5.33. The CE stage of Fig. 5.126 employs an ideal current source as the load. If the voltage gain is equal to 50 and the output impedance equal to 10 k, determine the bias current of the transistor. VCC

Q1

Ideal

500 Ω

Vout V in

Q1

Figure 5.124 Figure 5.126

5.32. Suppose the bipolar transistor in Fig. 5.125 **5.34. Determine the voltage gain and I/O exhibits the following hypothetical characimpedances of the circuits shown in teristic: Fig. 5.127. Assume VA = ∞. Transistor Q 2 in Figs. 5.127(d) and (e) operates in soft VBE IC = IS exp , (5.341) saturation. 2VT VCC

VCC

Q2

Q2 V in

VCC Q2

R1 Vout

V in

Q1

(a)

RC

Vout

V in

Q1

(b)

(c)

VCC

VCC

Q2 RC V in

Q1

(d)

Figure 5.127

Q2

Vout

Q1

RC V in

Q1

(e)

Vout

Vout

236

Chapter 5 Bipolar Amplifiers VCC = 2.5 V 1 kΩ

5.35. Calculate the voltage gain of the stage shown in Fig. 5.128, if the voltage drop across RC is 1 V, β = 100 and VA = ∞. Vin

VCC = 5 V 1 kΩ

RC

RE

Vin

Figure 5.129

RE = 700 Ω Figure 5.128

**5.39. Compute the voltage gain the I/O impedances of the circuits depicted in 5.36. Design the degenerated stage of Fig. 5.129 Fig. 5.131. Assume VA = ∞. for a voltage gain of 5. Calculate the bias currents and value of RE , if β = 100, *5.40. Compare the output impedances of the circuits illustrated in Fig. 5.132. Assume β 1. IS = 5 × 10−16 A and VA = ∞. Calculate the input impedance of the circuit. *5.41. Calculate the output impedance of the circuits shown in Fig. 5.133. Assume β 1. 5.37. Construct the small-signal model of the CE stage shown in Fig. 5.43(a) and calculate the 5.42. Calculate vout /vin for each of the circuits voltage gain. Assume VA = ∞. depicted in Fig. 5.134. Assume IS = 8 × 10−16 A, β = 100, and VA = ∞. **5.38. Determine the voltage gain and I/O Also, assume the capacitors are very impedances of the circuits shown in large. Fig. 5.130. Assume VA = ∞.

VCC

VCC

Q2 R1 V in

VCC

RC

RC Vout

V in Vout

Q1

Vout

V in

Q1 Q2

Q1 Q2

RE (b)

(a)

(c)

VCC

VCC

RC V in

RC Vout

RB

Q1

V in

RB

Vout Q1

Q2

(d)

Figure 5.130

(e)

Q2

VB

Problems VCC

VCC

VCC

RE V in

237

VCC

Q3

RE

Q1

V in

RE V in

Q1

Vout

V in

Q1 Vout

RC

RC

RC

Q2

Q2

(a)

Vout

VCC

RC Vout

Q2

Q1

Q2

(b)

(c)

(d)

Figure 5.131

VCC

VCC

Q1

Q1

Q2

Q2

R out

R out (a)

(b)

Figure 5.132 R out R out

R out

Q1

Q1

Q1

Q2

VCC

VCC Q2

RB

Q2

I1

(a)

R1

(b)

(c)

Figure 5.133

V CC = 2.5 V 100 k Ω

V in

V CC = 2.5 V

1 kΩ

Vout Q1

C1

100 Ω

50 k Ω

V in

1 kΩ

Vout 1 kΩ

V CC = 2.5 V

Q1

C1

2 kΩ

C2

14 k Ω

V in

RC

Vout

C1 1 kΩ

Q1 11 k Ω

500 Ω 2 kΩ

C2 (a)

Figure 5.134

(b)

10 k Ω

(c)

238

Chapter 5 Bipolar Amplifiers VCC

5.43. The common base stage of Fig. 5.135 biased with a base current of 20 μA. Assume β = 100 and of VA = ∞. Calculate the voltage gain and input/output impedances of the circuit.

RC

500 Ω Vb

Vin

5.44. Determine the voltage gain of the circuits shown in Fig. 5.136. Assume VA = ∞, IC = 2 mA and βnpn = 2β pnp = 100.

Figure 5.135

VCC VCC RC RC

Vout

Vb

1 kΩ

Vout

VCC Vb

Q1

1 kΩ Vb

Vin

RE = 1 k Ω

Vin

(a)

(b)

(c)

Figure 5.136

VCC

1 kΩ

R1

Q2

1 kΩ

R1 R2

VCC

10 k Ω

1 kΩ

VCC

R1 R2

10 k Ω

Q1 Rin

Vb RE

Rin (a)

Rin

500 Ω

(b)

(c)

Figure 5.137

5.45. Compute the input impedance of the stages shown in Fig. 5.137. Assume VA = ∞, IC = 2 mA and β = 100. 5.46. Compute the input/output impedance and voltage gain of the stages shown in Fig. 5.138. Assume VA = ∞. VCC

1 kΩ

Vin

75 Ω

5.47. Consider CB stage depicted in Fig. 5.139, where β = 100, IS = 8 × 10−16 A, VA = ∞ and C B is very large. (a) Calculate the operating point of Q and (b) calculate the voltage gain. VCC = 2.5 V

15 k Ω

1 kΩ Vout

12 k Ω

330 Ω

Rc Vb

Vin

Rin Figure 5.138

Figure 5.139

Problems *5.48. Calculate the voltage gain and the I/O impedances of the stage depicted in Fig. 5.140 if VA = ∞ and CB is very large.

VCC RC

RC

Vout 1

Vout 2 Q1

Q2

VCC

Vb

ideal

Vin

R1

V out

239

CB

Figure 5.143

Q1 R2

V in

**5.52. Using a small-signal model, determine the voltage gain of a CB stage with emitter degeneration, a base resistance, and VA < ∞. Assume β 1.

Figure 5.140

5.49. Compute the voltage gain and I/O impedances of the stage shown in Fig. 5.141 if VA = ∞ and CB is very large. VCC

10 k Ω

Q2

VCC R1

Vin

R1

V out

5.53. For RE = 600 in Fig. 5.144, determine the bias current of Q1 such that the gain is equal to 0.9. Assume VA = ∞.

CB Q1

Q1 Vout

10 k Ω

R2

RE

R2

V in

Figure 5.144 Figure 5.141

5.50. Calculate the voltage gain of the circuit shown in Fig. 5.142. Assume VA < ∞, β = 100 and gm = (26 )−1 . VCC = 2.5 V

RC

10 k Ω Vin

RB

1 kΩ Vout

5.54. The circuit of Fig. 5.144 must provide an input impedance of greater than 10 k with a minimum gain of 0.9. Calculate the required bias current and RE . Assume β = 100 and VA = ∞. 5.55. A microphone having an output impedance RS = 250 drives an emitter follower as shown in Fig. 5.145. Determine the bias currents such that the output impedance does not exceed 10 . Assume β = 100 and VA = ∞.

RE = 500 Ω

VCC = 2.5 Figure 5.142

5.51. The circuit of Fig. 5.143 provides two outputs. If IS1 = 3IS2 , determine the relation between Vout1 /Vin and Vout2 /Vin . Assume VA = ∞.

Vin

RS

200 Ω

Rout

12 k Ω

Figure 5.145

240

Chapter 5 Bipolar Amplifiers VCC V in

VCC V in

Q1

V in

Q1

Vout Vb

VCC

Vout

Vout

Q2

RS

Q2

(a)

Q1

Q2

(b)

(c)

VCC V in

VCC V in

Q1

Q1

Vout RE

RE Q2

(d)

Vout Q2

(e)

Figure 5.146

5.56. Compute the voltage gain and I/O impedances of the circuits shown in Fig. 5.146. Assume VA = ∞. *5.57. Figure 5.147 depicts a “Darlington pair,” where Q 1 plays a role somewhat similar to an emitter follower driving Q 2 . Assume VA = ∞ and the collectors of Q 1 and Q 2 are tied to VCC . Note that IE1 (≈IC 1 ) = IB2 = IC 2 /β. (a) If the emitter of Q 2 is grounded, determine the impedance seen at the base of Q 1 . (b) If the base of Q 1 is grounded, calculate the impedance seen at the emitter ofQ 2 . (c) Compute the current gain of the pair, defined as (IC 1 + IC 2 )/IB1 .

VCC = 2.5 V 10 k Ω

V in

Q1

C1

C2

1 kΩ

Vout 100 Ω

Figure 5.148

5.59. Assuming VA = ∞ determine the voltage gain of the circuit shown in Fig. 5.149.

VCC RC Vout

RS R1

Q1 Q2

R2

Q1

Vin RE

Figure 5.147

5.58. Determine the voltage gain of the follower depicted in Fig. 5.148. Assume IS = 7 × 10−16 A, β = 100, and VA = 5 V. (But for bias calculations, assume VA = ∞.) Also, assume the capacitors are very large.

Figure 5.149

5.60. Calculate the input and output impedances of the circuit depicted in Fig. 5.150. Determine the voltage gain.

Problems VCC RC

Vin

most 400 mV of base-collector forward bias, design the stage.

Vout

VCC = 2.5 V RB

RE

V in

Figure 5.150

5.61. Figure 5.151 shows a cascade of an emitter follower and common base stage. Calculate the input/output impedances of the circuit. Assume VA = ∞, gm1 = gm2 = (26 )−1 and β = 100. VCC = 2.5 V RC = 1 kΩ

Vin

Q1

10 k Ω

Vb

Q2

RE

Figure 5.151

5.64. The CE stage of Fig. 5.153 must be designed for minimum supply voltage but with a voltage gain of 15 and an output impedance of 2 k. If the transistor is allowed to sustain a base-collector forward bias of 400 mV, design the stage and calculate the required supply voltage. 5.65. Design the degenerated CE stage of Fig. 5.154 for a voltage gain of 5 and an output impedance of 500 . Assume RE sustains a voltage drop of 300 mV and the current flowing through R1 is approximately 10 times the base current. R1

5.62. Design the CE stage shown in Fig. 5.152 for a voltage gain of 10, and input impedance of greater than 5 k, and an output impedance of 1 k. If the lowest signal frequency of interest is 200 Hz, estimate the minimum allowable value of CB . VCC = 2.5 V RC Vout CB

Vout Q1

V CC = 2.5 V

In the following problems, unless otherwise stated, assume β = 100, IS = 6×10−16 A, and VA = ∞.

V in

RC

Figure 5.153

Design Problems

RB

241

Q1

Figure 5.152

5.63. We wish to design the CE stage of Fig. 5.153 for maximum voltage gain but with an output impedance no greater than 500 . Allowing the transistor to experience at

RC Vout

V in

Q1 R2 RE

Figure 5.154

5.66. The stage of Fig. 5.154 must be designed for maximum voltage gain but an output impedance of no greater than 1 k. Design the circuit, assuming that RE sustains 200 mV, the current flowing through R1 is approximately 10 times the base current, and Q 1 experiences a maximum basecollector forward bias of 400 mV. 5.67. Design the common-base stage shown in Fig. 5.155 for a voltage gain of 20 and an input impedance of 50 . Assume a voltage drop of 10VT = 260 mV across RE so that this resistor does not affect the input impedance significantly. Also, assume the current flowing through R1 is approximately 10 times the base current, and the lowest frequency of interest is 200 Hz.

242

Chapter 5 Bipolar Amplifiers V CC = 2.5 V R1

RC Vout

CB Q1 R2 RE

is 100 MHz. (Hint: Select the voltage drop across RE to be much greater than VT so that this resistor does not affect the voltage gain significantly.)

Vin

VCC = 2.5 V R1 V in

Figure 5.155

Q1 Vout RL

5.68. The CB amplifier of Fig. 5.155 must achieve a voltage gain of 8 with an output impedance of 500 . Design the circuit with the same assumptions as those in Problem 5.67. 5.69. Design the emitter follower shown in Fig. 5.156 for a voltage gain of 0.85 and an input impedance of greater than 10 k. Assume RL = 200 . 5.70. The follower shown in Fig. 5.157 must drive a load resistance, RL = 50 , with a voltage gain of 0.8. Design the circuit assuming that the lowest frequency of interest

Figure 5.156 VCC = 2.5 V R1 V in

C1

Q1 RE

C2

Vout RL

Figure 5.157

SPICE PROBLEMS In the following problems, assume IS,npn = 5 × 10−16 A, βnpn = 100, VA,npn = 5 V, IS,pnp = 8 × 10−16 A, βpnp = 50, VA,pnp = 3.5 V. 5.1. The common-emitter shown in Fig. 5.158 must amplify signals in the range of 1 MHz to 100 MHz. V CC = 2.5 V 100 k Ω

V in

1 kΩ

P C1 C2

Vout Q1 500 Ω

Figure 5.158

(a) Using the .op command, determine the bias conditions of Q 1 and verify that it operates in the active region. (b) Running an ac analysis, choose the value of C 1 such that |VP /Vin | ≈ 0.99 at

1 MHz. This ensures that C 1 acts as a short circuit at all frequencies of interest. (c) Plot |Vout /Vin | as a function of frequency for several values of C 2 , e.g., 1 μF, 1 nF, and 1 pF. Determine the value of C 2 such that the gain of the circuit at 10 MHz is only 2% below its maximum (i.e., for C 2 = 1 μF). (d) With the proper value of C 2 found in (c), determine the input impedance of the circuit at 10 MHz. (One approach is to insert a resistor in series with Vin and adjust its value until VP /Vin or Vout /Vin drops by a factor of two.) 5.2. Predicting an output impedance of about 1 k for the stage shown in Fig. 5.159, a student constructs the circuit depicted in Fig. 5.159, where VX represents an ac source with zero dc value. Unfortunately, VN /VX is far from 0.5. Explain why.

Spice Problems V CC = 2.5 V 100 k Ω

1 kΩ

N C1 C2

Q 1 1 kΩ

IX VX

500 Ω

Figure 5.159

(c) Compute the voltage gain of the circuit at 10 MHz. (d) Determine the input impedance of the circuit at 10 MHz. (e) Suppose the supply voltage is provided by an aging battery. How much can VCC fall while the gain of the circuit degrades by only 5%? V CC = 2.5 V

5.3. Consider the self-biased stage shown in Fig. 5.160. (a) Determine the bias conditions of Q 1 . (b) Select the value of C 1 such that it operates as nearly a short circuit (e.g., |VP /Vin | ≈ 0.99) at 10 MHz.

243

10 k Ω

V in

C1

Figure 5.160

P

1 kΩ

Q1

Vout

Chapter

6

Physics of MOS Transistors

Today’s field of microelectronics is dominated by a type of device called the metaloxide-semiconductor field-effect transistor (MOSFET). Conceived in the 1930s but first realized in the 1960s, MOSFETs (also called MOS devices) offer unique properties that have led to the revolution of the semiconductor industry. This revolution has culminated in microprocessors having 100 million transistors, memory chips containing billions of transistors, and sophisticated communication circuits providing tremendous signal processing capability. Our treatment of MOS devices and circuits follows the same procedure as that taken in Chapters 2 and 3 for pn junctions. In this chapter, we analyze the structure and operation of MOSFETs, seeking models that prove useful in circuit design. In Chapter 7, we utilize the models to study MOS amplifier topologies. The outline below illustrates the sequence of concepts covered in this chapter.

Operation of MOSFETs • MOS Structure • Operation in Triode Region

MOS Device Models • Large–Signal Model

➤ • Small–Signal Model

PMOS Devices

➤

• Structure • Models

• Operation in Saturation • I/V Characteristics

6.1

STRUCTURE OF MOSFET Recall from Chapter 5 that any voltage-controlled current source can provide signal amplification. MOSFETs also behave as such controlled sources but their characteristics are different from those of bipolar transistors. In order to arrive at the structure of the MOSFET, we begin with a simple geometry consisting of a conductive (e.g., metal) plate, an insulator (“dielectric”), and a doped piece of silicon. Illustrated in Fig. 6.1(a), such a structure operates as a capacitor because

244

6.1 Structure of MOSFET

245

Conductive Plate Insulator

V1

V1

Channel of Electrons

p-Type Silicon

V2 (a)

(b)

(c)

(a) Hypothetical semiconductor device, (b) operation as a capacitor, (c) current flow as a result of potential difference.

Figure 6.1

the p-type silicon is somewhat conductive, “mirroring” any charge deposited on the top plate. What happens if a potential difference is applied as shown in Fig. 6.1(b)? As positive charge is placed on the top plate, it attracts negative charge, e.g., electrons, from the piece of silicon. (Even though doped with acceptors, the p-type silicon does contain a small number of electrons.) We therefore observe that a “channel” of free electrons may be created at the interface between the insulator and the piece of silicon, potentially serving as a good conductive path if the electron density is sufficiently high. The key point here is that the density of electrons in the channel varies with V1 , as evident from Q = CV, where C denotes the capacitance between the two plates. The dependence of the electron density upon V1 leads to an interesting property: if, as depicted in Fig. 6.1(c), we allow a current to flow from left to right through the silicon material, V1 can control the current by adjusting the resistivity of the channel. (Note that the current prefers to take the path of least resistance, thus flowing primarily through the channel rather than through the entire body of silicon.) This will serve our objective of building a voltage-controlled current source. Equation Q = CV suggests that, to achieve a strong control of Q by V, the value of C must be maximized, for example, by reducing the thickness of the dielectric layer separating the two plates.1 The ability of silicon fabrication technology to produce extremely thin but ˚ today) has proven essential to the uniform dielectric layers (with thicknesses below 20 A rapid advancement of microelectronic devices. The foregoing thoughts lead to the MOSFET structure shown in Fig. 6.2(a) as a candidate for an amplifying device. Called the “gate” (G), the top conductive plate resides on a thin dielectric (insulator) layer, which itself is deposited on the underlying p-type silicon “substrate.” To allow current flow through the silicon material, two contacts are attached to the substrate through two heavily-doped n-type regions because direct connection of metal to the substrate would not produce a good “ohmic” contact.2 These two terminals are called “source” (S) and “drain” (D) to indicate that the former can provide charge carriers and the latter can absorb them. Figure 6.2(a) reveals that the device is symmetric with respect to S and D; i.e., depending on the voltages applied to the device, either of these two terminals can drain the charge carriers from the other. As explained in Section 6.2, with n-type source/drain and p-type substrate, this transistor operates with electrons rather 1 The capacitance between two plates is given by A/t, where is the “dielectric constant” (also called the “permitivity”), A is the area of each plate, and t is the dielectric thickness. 2 Used to distinguish it from other types of contacts such as diodes, the term “ohmic” contact emphasizes bi-directional current flow—as in a resistor.

246

Chapter 6 Physics of MOS Transistors Conductive Plate

Gate

Source

n+

Drain

n+

p -Substrate

G

Insulator (a)

S

D

n+

n+

G S

p -Substrate (b)

Figure 6.2

D (c)

(a) Structure of MOSFET, (b) side view, (c) circuit symbol.

than holes and is therefore called an n-type MOS (NMOS) device. (The p-type counterpart is studied in Section 6.4.) We draw the device as shown in Fig. 6.2(b) for simplicity. Figure 6.2(c) depicts the circuit symbol for an NMOS transistor, wherein the arrow signifies the source terminal. Before delving into the operation of the MOSFET, let us consider the types of materials used in the device. The gate plate must serve as a good conductor and was in fact realized by metal (aluminum) in the early generations of MOS technology. However, it was discovered that noncrystalline silicon (“polysilicon” or simply “poly”) with heavy doping (for low resistivity) exhibits better fabrication and physical properties. Thus, today’s MOSFETs employ polysilicon gates. The dielectric layer sandwiched between the gate and the substrate plays a critical role in the performance of transistors and is created by growing silicon dioxide (or simply “oxide”) on top of the silicon area. The n+ regions are sometimes called source/drain “diffusion,” referring to a fabrication method used in early days of microelectronics. We should also remark that these regions in fact form diodes with the p-type substrate (Fig. 6.3).

Polysilicon

Oxide

S/D Diffusion

n+

n+ t ox = 18 A Length 90 nm

Figure 6.3

Typical dimensions of today’s MOSFETs.

p -Substrate Oxide-Silicon Interface

6.2 Operation of MOSFET

247

As explained later, proper operation of the transistor requires that these junctions remain reverse-biased. Thus, only the depletion region capacitance associated with the two diodes must be taken into account. Figure 6.3 shows some of the device dimensions in today’s state-of-the-art MOS technologies. The oxide thickness is denoted by tox .

6.2

OPERATION OF MOSFET This section deals with a multitude of concepts related to MOSFETs. The outline is shown in Fig. 6.4.

Qualitative Analysis

I/V Characteristics

Formation of Channel MOSFET as Resistor Channel Pinch-off I/V Characteristics

Channel Charge Density Drain Current Triode and Saturation Regions

Figure 6.4

Analog Properties Transconductance Channel–Length Modulation

Other Properties Body Effect Subthreshold Conduction Velocity Saturation

Outline of concepts to be studied.

6.2.1 Qualitative Analysis Our study of the simple structures shown in Figs. 6.1 and 6.2 suggests that the MOSFET may conduct current between the source and drain if a channel of electrons is created by making the gate voltage sufficiently positive. Moreover, we expect that the magnitude of the current can be controlled by the gate voltage. Our analysis will indeed confirm these conjectures while revealing other subtle effects in the device. Note that the gate terminal draws no (low-frequency) current as it is insulated from the channel by the oxide. Since the MOSFET contains three terminals,3 we may face many combinations of terminal voltages and currents. Fortunately, with the (low-frequency) gate current being zero, the only current of interest is that flowing between the source and the drain. We must study the dependence of this current upon the gate voltage (e.g., for a constant drain voltage) and upon the drain voltage (e.g., for a constant gate voltage). These concepts become clearer below. Let us first consider the arrangement shown in Fig. 6.5(a), where the source and drain are grounded and the gate voltage is varied. This circuit does not appear particularly useful but it gives us a great deal of insight. Recall from Fig. 6.1(b) that, as VG rises, the positive charge on the gate must be mirrored by negative charge in the substrate. While we stated in Section 6.1 that electrons are attracted to the interface, in reality, another phenomenon precedes the formation of the channel. As VG increases from zero, the positive charge on the gate repels the holes in the substrate, thereby exposing negative ions and creating a depletion region [Fig. 6.5(b)].4 Note that the device still acts as a capacitor—positive charge on the gate is mirrored by negative charge in the substrate—but no channel of mobile charge is created yet. Thus, no current can flow from the source to the drain. We say the MOSFET is off. 3

The substrate acts as a fourth terminal, but we ignore that for now. Note that this depletion region contains only one immobile charge polarity, whereas the depletion region in a pn junction consists of two areas of negative and positive ions on the two sides of the junction. 4

248

Chapter 6 Physics of MOS Transistors

VG

VG

n+

n+

p -Substrate (a)

VG

VG

n+

n+

n+

p -Substrate

n+ Free Electrons

p -Substrate Depletion Region

Negative Ions

(b)

(c)

(a) MOSFET with gate voltage, (b) formation of depletion region, (c) formation of channel.

Figure 6.5

Can the source-substrate and drain-substrate junctions carry current in this mode? To avoid this effect, the substrate itself is also tied to zero, ensuring that these diodes are not forward-biased. For simplicity, we do not show this connection in the diagrams. What happens as VG increases? To mirror the charge on the gate, more negative ions are exposed and the depletion region under the oxide becomes deeper. Does this mean the transistor never turns on?! Fortunately, if VG becomes sufficiently positive, free electrons are attracted to the oxide-silicon interface, forming a conductive channel [Fig. 6.5(c)]. We say the MOSFET is on. The gate potential at which the channel begins to appear is called the “threshold voltage,” VTH , and falls in the range of 300 mV to 500 mV. Note that the electrons are readily provided by the n+ source and drain regions, and need not be supplied by the substrate. It is interesting to recognize that the gate terminal of the MOSFET draws no (lowfrequency) current. Resting on top of the oxide, the gate remains insulated from other terminals and simply operates as a plate of a capacitor. MOSFET as a Variable Resistor The conductive channel between S and D can be viewed as a resistor. Furthermore, since the density of electrons in the channel must increase as VG becomes more positive (why?), the value of this resistor changes with the gate voltage. Conceptually illustrated in Fig. 6.6, such a voltage-dependent resistor proves extremely useful in analog and digital circuits.

G

S

Figure 6.6

MOSFET viewed as a voltage-dependent resistor.

D

6.2 Operation of MOSFET

249

Example 6.1

In the vicinity of a wireless base station, the signal received by a cellphone may become very strong, possibly “saturating” the circuits and prohibiting proper operation. Devise a variable-gain circuit that lowers the signal level as the cellphone approaches the base station.

Solution

A MOSFET can form a voltage-controlled attenuator along with a resistor as shown in Fig. 6.7. Since vout R1 = , vin RM + R 1

(6.1)

the output signal becomes smaller as Vcont falls because the density of electrons in the channel decreases and RM rises. MOSFETs are commonly utilized as voltage-dependent resistors in “variable-gain amplifiers.”

V cont

v in

v out RM

Figure 6.7 Exercise

R1

Use of MOSFET to adjust signal levels.

What happens to RM if the channel length is doubled?

In the arrangement of Fig. 6.5(c), no current flows between S and D because the two terminals are at the same potential. We now raise the drain voltage as shown in Fig. 6.8(a) and examine the drain current (= source current). If VG < VTH , no channel exists, the device is off, and ID = 0 regardless of the value of VD . On the other hand, if VG > VTH , then ID > 0 [Fig. 6.8(b)]. In fact, the source-drain path may act as a simple resistor, yielding the ID -VD characteristic shown in Fig. 6.8(c). The slope of the characteristic is equal to 1/Ron , where Ron denotes the “on-resistance” of the transistor.5 Our brief treatment of the MOS I-V characteristics thus far points to two different views of the operation: in Fig. 6.8(b), VG is varied while VD remains constant whereas in Fig. 6.8(c), VD is varied while VG remains constant. Each view provides valuable insight into the operation of the transistor. How does the characteristic of Fig. 6.8(b) change if VG increases? The higher density of electrons in the channel lowers the on-resistance, yielding a greater slope. Depicted in Fig. 6.8(d), the resulting characteristics strengthen the notion of voltage-dependent resistance.

5 The term “on-resistance” always refers to that between the source and drain, as no resistance exists between the gate and other terminals.

250

Chapter 6 Physics of MOS Transistors

n+

ID

ID

VG

VG

ID VD

ID

VD

n+

VG

VD

p -Substrate

VTH

(a)

ID

ID

ID VD

VG

(b)

VG3

VG

VG2 VG1

−1

R on (c)

VD

(d)

VD

(a) MOSFET with gate and drain voltages, (b) ID -VG characteristic, (c) ID -VD characteristic, (d) ID -VD characteristics for various gate voltages.

Figure 6.8

Recall from Chapter 2 that charge flow in semiconductors occurs by diffusion or drift. How about the transport mechanism in a MOSFET? Since the voltage source tied to the drain creates an electric field along the channel, the current results from the drift of charge. The ID -VG and ID -VD characteristics shown in Figs. 6.8(b) and (c), respectively, play a central role in our understanding of MOS devices. The following example reinforces the concepts studied thus far.

Example 6.2

Sketch the ID -VG and ID -VD characteristics for (a) different channel lengths, and (b) different oxide thicknesses.

Solution

As the channel length increases, so does the on-resistance.6 Thus, for VG > VTH , the drain current begins with lesser values as the channel length increases [Fig. 6.9(a)]. Similarly, ID exhibits a smaller slope as a function of VD [Fig. 6.9(b)]. It is therefore desirable to minimize the channel length so as to achieve large drain currents—an important trend in the MOS technology development. How does the oxide thickness, tox , affect the I-V characteristics? As tox increases, the capacitance between the gate and the silicon substrate decreases. Thus, from Q = CV, we note that a given voltage results in less charge on the gate and hence a lower electron density in the channel. Consequently, the device suffers from a higher on-resistance, producing less drain current for a given gate voltage [Fig. 6.9(c)] or drain voltage [Fig. 6.9(d)]. For this reason, the semiconductor industry has continued to reduce the gate oxide thickness.

6

Recall that the resistance of a conductor is proportional to the length.

6.2 Operation of MOSFET ID

251

ID

VTH

VG

VD

(a)

(b)

ID

ID

VTH

VG

VD

(c)

(d)

(a) ID -VG characteristics for different channel lengths, (b) ID -VD characteristics for different channel lengths, (c) ID -VG characteristics for different oxide thicknesses, (d) ID -VD characteristics for different oxide thicknesses.

Figure 6.9

Exercise

The current conduction in the channel is in the form of drift. If the mobility falls at high temperatures, what can we say about the on-resistance as the temperature goes up?

While both the length and the oxide thickness affect the performance of MOSFETs, only the former is under the circuit designer’s control, i.e., it can be specified in the “layout” of the transistor. The latter, on the other hand, is defined during fabrication and remains constant for all transistors in a given generation of the technology. Another MOS parameter controlled by circuit designers is the width of the transistor, the dimension perpendicular to the length [Fig. 6.10(a)]. We therefore observe that

t ox W

n+

n+

L (a)

ID

W

ID W S

VTH

VG

G

VD (b)

(c)

Figure 6.10 (a) Dimensions of a MOSFET (W and L are under circuit designer’s control), (b) ID characteristics for different values of W, (c) equivalence to devices in parallel.

D

252

Chapter 6 Physics of MOS Transistors “lateral” dimensions such as L and W can be chosen by circuit designers whereas “vertical” dimensions such as tox cannot. How does the gate width impact the I-V characteristics? As W increases, so does the width of the channel, thus lowering the resistance between the source and the drain7 and yielding the trends depicted in Fig. 6.10(b). From another perspective, a wider device can be viewed as two narrower transistors in parallel, producing a high drain current [Fig. 6.10(c)]. We may then surmise that W must be maximized, but we must also note that the total gate capacitance increases with W, possibly limiting the speed of the circuit. Thus, the width of each device in the circuit must be chosen carefully. Channel Pinch-Off Our qualitative study of the MOSFET thus far implies that the device acts as a voltage-dependent resistor if the gate voltage exceeds VTH . In reality, however, the transistor operates as a current source if the drain voltage is sufficiently positive. To understand this effect, we make two observations: (1) to form a channel, the potential difference between the gate and the oxide-silicon interface must exceed VTH ; (2) if the drain voltage remains higher than the source voltage, then the voltage at each point along the channel with respect to ground increases as we go from the source towards the drain. Illustrated in Fig. 6.11(a), this effect arises from the gradual voltage drop along the channel resistance. Since the gate voltage is constant (because the gate is conductive but carries no current in any direction), and since the potential at the oxide-silicon interface rises from the source to the drain, the potential difference between the gate and the oxide-silicon interface decreases along the x-axis [Fig. 6.11(b)]. The density of electrons in the channel follows the same trend, falling to a minimum at x = L.

VG

n+ ID Potential = V G Difference

VD

n+

< VG

x = VG − VD

Gate-Substrate Potential Difference

V (x ) VG

L (a)

Figure 6.11

x

VD − VG L

x

(b)

(a) Channel potential variation, (b) gate-substrate voltage difference along the

channel.

7 Recall that the resistance of a conductor is inversely proportional to the cross section area, which itself is equal to the product of the width and thickness of the conductor.

6.2 Operation of MOSFET ID

VG n+

> V TH

VD

n+

VG VD

Electrons

ID

VG n+

253

V TH VD

n+

VG VD

(a)

ID

VG n+

VD

n+

n+

E 0 (b)

Figure 6.12

L1 L

x (c)

(a) Pinchoff, (b) variation of length with drain voltage, (c) detailed operation near

the drain.

From these observations, we conclude that, if the drain voltage is high enough to produce VG − VD ≤ VTH , then the channel ceases to exist near the drain. We say the gatesubstrate potential difference is not sufficient at x = L to attract electrons and the channel is “pinched off” [Fig. 6.12(a)]. What happens if VD rises even higher than VG − VTH ? Since V(x) now goes from 0 at x = 0 to VD > VG − VTH at x = L, the voltage difference between the gate and the substrate falls to VTH at some point L1 < L [Fig. 6.12(b)]. The device therefore contains no channel between L1 and L. Does this mean the transistor cannot conduct current? No, the device still conducts: as illustrated in Fig. 6.12(c), once the electrons reach the end of the channel, they experience the high electric field in the depletion region surrounding the drain junction and are rapidly swept to the drain terminal. Nonetheless, as shown in the next section, the drain voltage no longer affects the current significantly, and the MOSFET acts as a constant current source—similar to a bipolar transistor in the forward active region. Note that the source-substrate and drain-substrate junctions carry no current. 6.2.2 Derivation of I-V Characteristics With the foregoing qualitative study, we can now formulate the behavior of MOSFETs in terms of their terminal voltages. Channel Charge Density Our derivations require an expression for the channel charge (i.e., free electrons) per unit length, also called the “charge density.” FromQ = CV, we note

254

Chapter 6 Physics of MOS Transistors

W

n+

Figure 6.13

n+

Illustration of capacitance per unit length.

that if C is the gate capacitance per unit length and V the voltage difference between the gate and the channel, then Q is the desired charge density. Denoting the gate capacitance per unit area by Cox (expressed in F/m2 or fF/μm2 ), we write C = WCox to account for the width of the transistor (Fig. 6.13). Moreover, we have V = VGS − VTH because no mobile charge exists for VGS < VTH . (Hereafter, we denote both the gate and drain voltages with respect to the source.) It follows that Q = WCox (VGS − VTH ).

(6.2)

Note that Q is expressed in coulomb/meter. Now recall from Fig. 6.11(a) that the channel voltage varies along the length of the transistor, and the charge density falls as we go from the source to the drain. Thus, Eq. (6.2) is valid only near the source terminal, where the channel potential remains close to zero. As shown in Fig. 6.14, we denote the channel potential at x by V(x) and write Q(x) = WCox [VGS − V(x) − VTH ],

(6.3)

noting that V(x) goes from zero to VD if the channel is not pinched off.

ID

VG n+

Figure 6.14

dx

VD

n+

V (x )

L

x

Device illustration for calculation of drain current.

Drain Current What is the relationship between the mobile charge density and the current? Consider a bar of semiconductor having a uniform charge density (per unit length) equal to Q and carrying a current I (Fig. 6.15). Note from Chapter 2 that (1) I is given by the total charge that passes through the cross section of the bar in one second, and (2) if the carriers move with a velocity of v m/s, then the charge enclosed in v meters along the bar passes through the cross section in one second. Since the charge enclosed in v meters is equal to Q · v, we have I = Q · v.

(6.4)

6.2 Operation of MOSFET v meters

t = t1

t = t1 + 1 s

L

W

h

x

x1

x

x1

V1

Figure 6.15

255

V1

Relationship between charge velocity and current.

As explained in Chapter 2, v = −μn E, = +μn

(6.5)

dV , dx

(6.6)

where dV/dx denotes the derivative of the voltage at a given point. Combining Eqs. (6.3), (6.4), and (6.6), we obtain ID = WCox [VGS − V(x) − VTH ]μn

dV(x) . dx

(6.7)

Interestingly, since ID must remain constant along the channel (why?), V(x) and dV/dx must vary such that the product of VGS − V(x) − VTH and dV/dx is independent of x. While it is possible to solve the above differential equation to obtain V(x) in terms of ID (and the reader is encouraged to do that), our immediate need is to find an expression for ID in terms of the terminal voltages. To this end, we write

x=L

ID dx =

x=0

V(x)=VDS

μnCox W[VGS − V(x) − VTH ] dV.

(6.8)

V(x)=0

That is, ID =

W 1 2 . μnCox 2(VGS − VTH )VDS − VDS 2 L

(6.9)

We now examine this important equation from different perspectives to gain more insight. First, the linear dependence of ID upon μn ,Cox , and W/L is to be expected: a higher mobility yields a greater current for a given drain-source voltage; a higher gate oxide capacitance leads to a larger electron density in the channel for a given gate-source voltage; and a larger W/L (called the device “aspect ratio”) is equivalent to placing more transistors in parallel [Fig. 6.10(c)]. Second, for a constant VGS , ID varies parabolically with VDS (Fig. 6.16), reaching a maximum of ID,max =

W 1 μnCox (VGS − VTH )2 2 L

(6.10)

at VDS = VGS − VTH . It is common to write W/L as the ratio of two values e.g., 5 μm/0.18 μm (rather than 27.8) to emphasize the choice of W and L. While only the

256

Chapter 6 Physics of MOS Transistors ID 1 µ C W (V − V ( 2 n ox GS TH L 2

VGS − V TH

Figure 6.16

VDS

Parabolic ID -VDS characteristic.

ratio appears in many MOS equations, the individual values of W and L also become critical in most cases. For example, if both W and L are doubled, the ratio remains unchanged but the gate capacitance increases.

Example 6.3

Plot the ID -VDS characteristics for different values of VGS .

Solution

As VGS increases, so do ID,max and VGS − VTH . Illustrated in Fig. 6.17, the characteristics exhibit maxima that follow a parabolic shape themselves because ID,max ∝ (VGS − VTH )2 .

Parabola

ID I D,max4

VGS3

I D,max3

VGS2

Exercise

VGS3 − V TH

VGS1 − V TH

Figure 6.17

VGS2 − V TH

VGS1

I D,max2

VDS

MOS characteristics for different gate-source voltages.

What happens to the above plots if tox is halved?

The nonlinear relationship between ID and VDS reveals that the transistor cannot generally be modeled as a simple linear resistor. However, if VDS 2(VGS − VTH ), Eq. (6.9) reduces to: ID ≈ μnCox

W (VGS − VTH )VDS , L

(6.11)

6.2 Operation of MOSFET VGS3

ID

ID VGS2

257

VGS3 VGS2 VGS1

VGS1 VDS VDS

Figure 6.18

Detailed characteristics for small VDS .

exhibiting a linear ID -VDS behavior for a given VGS . In fact, the equivalent on-resistance is given by VDS /ID : Ron =

1 . W μnCox (VGS − VTH ) L

(6.12)

From another perspective, at small VDS (near the origin), the parabolas in Fig. 6.17 can be approximated by straight lines having different slopes (Fig. 6.18). As predicted in Section 6.2.1, Eq. (6.12) suggests that the on-resistance can be controlled by the gate-source voltage. In particular, for VGS = VTH , Ron = ∞, i.e., the device can operate as an electronic switch.

Example 6.4

A cordless telephone incorporates a single antenna for reception and transmission. Explain how the system must be configured.

Solution

The system is designed so that the phone receives for half of the time and transmits for the other half. Thus, the antenna is alternately connected to the receiver and the transmitter in regular intervals, e.g., every 20 ms (Fig. 6.19). An electronic antenna switch is therefore necessary here.8

Figure 6.19 Exercise

Receiver

Receiver

Transmitter

Transmitter

Role of antenna switch in a cordless phone.

Some systems employ two antennas, each of which receives and transmits signals. How many switches are needed?

8

Some cellphones operate in the same manner.

258

Chapter 6 Physics of MOS Transistors In most applications, it is desirable to achieve a low on-resistance for MOS switches. The circuit designer must therefore maximize W/L and VGS . The following example illustrates this point.

Example 6.5

In the cordless phone of Example 6.4, the switch connecting the transmitter to the antenna must negligibly attenuate the signal, e.g., by no more than 10%. If VDD = 1.8 V, μnCox = 100 μA/V2 , and VTH = 0.4 V, determine the minimum required aspect ratio of the switch. Assume the antenna can be modeled as a 50- resistor.

Solution

As depicted in Fig. 6.20, we wish to ensure Vout ≥ 0.9 Vin

(6.13)

R on

R on

V out 50 Ω

Figure 6.20

Transmitter

V in

R ant

Signal degradation due to on-resistance of antenna switch.

and hence Ron ≤ 5.6 .

(6.14)

Setting VGS to the maximum value, VDD , we obtain from Eq. (6.12), W ≥ 1276. L

(6.15)

(Since wide transistors introduce substantial capacitance in the signal path, this choice of W/L may still attenuate high-frequency signals.) Exercise

What W/L is necessary if VDD drops to 1.2 V?

Triode and Saturation Regions Equation (6.9) expresses the drain current in terms of the device terminal voltages, implying that the current begins to fall for VDS > VGS − VTH .

6.2 Operation of MOSFET ID 1 μ C W (V – V ( n ox GS TH L 2

2

Triode Region

259

Saturation Region

VGS –V TH

VDS

Overall MOS characteristic.

Figure 6.21

We say the device operates in the “triode region” (also called the “linear region”) if VDS < VGS − VTH (the rising section of the parabola). We also use the term “deep triode region” for VDS 2(VGS − VTH ), where the transistor operates as a resistor. In reality, the drain current reaches “saturation,” that is, becomes constant for VDS > VGS − VTH (Fig. 6.21). To understand why, recall from Fig. 6.12 that the channel experiences pinch-off if VDS = VGS − VTH . Thus, further increase in VDS simply shifts the pinch-off point slightly toward the drain. Also, recall that Eqs. (6.7) and (6.8) are valid only where channel charge exists. It follows that the integration in Eq. (6.8) must encompass only the channel, i.e., from x = 0 to x = L1 in Fig. 6.12(b), and be modified to

x=L1 x=0

ID dx =

V(x)=VGS −VTH

μnCox W[VGS − V(x) − VTH ] dV.

(6.16)

V(x)=0

Note that the upper limits correspond to the channel pinch-off point. In particular, the integral on the right-hand side is evaluated up to VGS − VTH rather than VDS . Consequently,

ID =

1 W μnCox (VGS − VTH )2 , 2 L1

(6.17)

a result independent of VDS and identical to ID,max in Eq. (6.10) if we assume L1 ≈ L. Called the “overdrive voltage,” the quantity VGS − VTH plays a key role in MOS circuits. MOSFETs are sometimes called “square-law” devices to emphasize the relationship between ID and the overdrive. For the sake of brevity, we hereafter denote L1 with L. The I-V characteristic of Fig. 6.21 resembles that of bipolar devices, with the triode and saturation regions in MOSFETs appearing similar to saturation and forward active regions in bipolar transistors, respectively. It is unfortunate that the term “saturation” refers to completely different regions in MOS and bipolar I-V characteristics. We employ the conceptual illustration in Fig. 6.22 to determine the region of operation. Note that the gate-drain potential difference suits this purpose and we need not compute the gate-source and gate-drain voltages separately. Exhibiting a “flat” current in the saturation region, a MOSFET can operate as a current source having a value given by Eq. (6.17). Furthermore, the square-law dependence of ID upon VGS − VTH suggests that the device can act as a voltage-controlled current source.

260

Chapter 6 Physics of MOS Transistors VTH

> VTH

ID 1 µ C W (V − V ( 2 n ox GS TH L 2

Saturated Triode Region

M1

Saturation Region

VGS − V TH

VDS

(a)

Figure 6.22 Example 6.6

(b)

Illustration of triode and saturation regions based on the gate and drain voltages.

Calculate the bias current of M1 in Fig. 6.23. Assume μnCox = 100 μA/V2 and VTH = 0.4 V. If the gate voltage increases by 10 mV, what is the change in the drain voltage? VDD = 1.8 V RD

5 kΩ

ID

1V

Figure 6.23 Solution

X M1 W = 2 L 0.18

Simple MOS circuit.

It is unclear a priori in which region M1 operates. Let us assume M1 is saturated and proceed. Since VGS = 1 V, W 1 ID = μnCox (VGS − VTH )2 (6.18) 2 L = 200 μA. (6.19) We must check our assumption by calculating the drain potential: VX = VDD − RD ID = 0.8 V.

(6.20) (6.21)

The drain voltage is lower than the gate voltage, but by less than VTH . The illustration in Fig. 6.22 therefore indicates that M1 indeed operates in saturation. If the gate voltage increases to 1.01 V, then ID = 206.7 μA,

(6.22)

VX = 0.766 V.

(6.23)

lowering VX to Fortunately, M1 is still saturated. The 34-mV change in VX reveals that the circuit can amplify the input. Exercise

What choice of RD places the transistor at the edge of the triode region?

6.2 Operation of MOSFET

261

It is instructive to identify several points of contrast between bipolar and MOS devices. (1) A bipolar transistor with VBE = VCE resides at the edge of the active region whereas a MOSFET approaches the edge of saturation if its drain voltage falls below its gate voltage by VTH . (2) Bipolar devices exhibit an exponential IC -VBE characteristic while MOSFETs display a square-law dependence. That is, the former provide a greater transconductance than the latter (for a given bias current). (3) In bipolar circuits, most transistors have the same dimensions and hence the same IS , whereas in MOS circuits, the aspect ratio of each device may be chosen differently to satisfy the design requirements. (4) The gate of MOSFETs draws no bias current.9

Example 6.7

Determine the value of W/L in Fig. 6.23 that places M1 at the edge of saturation and calculate the drain voltage change for a 1-mV change at the gate. Assume VTH = 0.4 V.

Solution

With VGS = +1 V, the drain voltage must fall to VGS − VTH = 0.6 V for M1 to enter the triode region. That is, VDD − VDS RD

ID =

(6.24)

= 240 μA.

(6.25)

W 2 240 μA · = L max 200 μA 0.18

(6.26)

2.4 . 0.18

(6.27)

ID = 248.04 μA,

(6.28)

VX = ID · RD

(6.29)

= 4.02 mV.

(6.30)

Since ID scales linearly with W/L,

= If VGS increases by 1 mV,

changing VX by

The voltage gain is thus equal to 4.02 in this case. Exercise

Repeat the above example if RD is doubled.

9

New generations of MOSFETs suffer from gate “leakage” current, but we neglect this effect here.

262

Chapter 6 Physics of MOS Transistors

Example 6.8

Calculate the maximum allowable gate voltage in Fig. 6.24 if M1 must remain saturated.

VDD = 1.8 V 5 kΩ

RD ID

X M1 W = 2 L 0.18

V GS

Figure 6.24 Solution

Simple MOS circuit.

At the edge of saturation, VGS − VTH = VDS = VDD − RD ID . Substituting for ID from Eq. (6.17) gives VGS − VTH = VDD −

W RD μnCox (VGS − VTH )2 , 2 L

and hence VGS − VTH = Thus, VGS =

Exercise

−1 +

−1 +

1 + 2RD VDD μnCox W L

.

(6.32)

+ VTH .

(6.33)

RD μnCox W L

1 + 2RD VDD μnCox W L RD μnCox W L

(6.31)

Calculate the value of VGS if μnCox = 100 μA/V2 and VTH = 0.4.

6.2.3 Channel-Length Modulation In our study of the pinch-off effect, we observed that the point at which the channel vanishes in fact moves toward the source as the drain voltage increases. In other words, the value of L1 in Fig. 6.12(b) varies with VDS to some extent. Called “channel-length modulation” and illustrated in Fig. 6.25, this phenomenon yields a larger drain current as VDS increases because ID ∝ 1/L1 in Eq. (6.17). Similar to the Early effect in bipolar devices,

ID 1 µ C W (V − V ( 2 n ox GS TH L 2

VGS − V TH

Figure 6.25

Variation of ID in saturation region.

VDS

6.2 Operation of MOSFET

263

channel-length modulation results in a finite output impedance given by the inverse of the ID -VDS slope in Fig. 6.25. To account for channel-length modulation, we assume L is constant, but multiply the right-hand side of Eq. (6.17) by a corrective term: ID =

W 1 μnCox (VGS − VTH )2 (1 + λVDS ), 2 L

(6.34)

where λ is called the “channel-length modulation coefficient.” While only an approximation, this linear dependence of ID upon VDS still provides a great deal of insight into the circuit design implications of channel-length modulation. Unlike the Early effect in bipolar devices (Chapter 4), the amount of channel-length modulation is under the circuit designer’s control. This is because λ is inversely proportional to L: for a longer channel, the relative change in L (and hence in ID ) for a given change in VDS is smaller (Fig. 6.26).10 (By contrast, the base width of bipolar devices cannot be adjusted by the circuit designer, yielding a constant Early voltage for all transistors in a given technology.)

L1

L2

ID

ID

VDS

Figure 6.26

VDS

Channel-length modulation.

Example 6.9

A MOSFET carries a drain current of 1 mA with VDS = 0.5 V in saturation. Determine the change in ID if VDS rises to 1 V and λ = 0.1 V−1 . What is the device output impedance?

Solution

We write ID1 =

W 1 μnCox (VGS − VTH )2 (1 + λVDS1 ) 2 L

(6.35)

ID2 =

W 1 μnCox (VGS − VTH )2 (1 + λVDS2 ) 2 L

(6.36)

and hence ID2 = ID1

1 + λVDS2 . 1 + λVDS1

(6.37)

With ID1 = 1 mA, VDS1 = 0.5 V, VDS2 = 1 V, and λ = 0.1 V−1 , ID2 = 1.048 mA.

(6.38)

10 Since different MOSFETs in a circuit may be sized for different λ’s, we do not define a quantity similar to the Early voltage here.

264

Chapter 6 Physics of MOS Transistors The change in ID is therefore equal to 48 μA, yielding an output impedance of VDS ID

(6.39)

= 10.42 k.

(6.40)

rO =

Exercise

Does W affect the above results?

The above example reveals that channel-length modulation limits the output impedance of MOS current sources. The same effect was observed for bipolar current sources in Chapters 4 and 5. Example 6.10

Assuming λ ∝ 1/L, calculate ID and rO in Example 6.9 if both W and L are doubled.

Solution

In Eqs. (6.35) and (6.36), W/L remains unchanged but λ drops to 0.05 V−1 . Thus, ID2 = ID1

1 + λVDS2 1 + λVDS1

(6.41)

= 1.024 mA.

(6.42)

rO = 20.84 k.

(6.43)

That is, ID = 24 μA and

Exercise

What output impedance is achieved if W and L are quadrupled and ID is halved?

6.2.4 MOS Transconductance As a voltage-controlled current source, a MOS transistor can be characterized by its transconductance: gm =

∂ID . ∂VGS

(6.44)

This quantity serves as a measure of the “strength” of the device: a higher value corresponds to a greater change in the drain current for a given change in VGS . Using Eq. (6.17) for the saturation region, we have gm = μnCox

W (VGS − VTH ), L

(6.45)

concluding that (1) gm is linearly proportional to W/L for a given VGS − VTH , and (2) gm is linearly proportional to VGS − VTH for a given W/L. Also, substituting for VGS − VTH from Eq. (6.17), we obtain W (6.46) gm = 2μnCox ID . L

6.2 Operation of MOSFET

265

TABLE 6.1 Various dependencies of gm. W L

W L

Constant VGS − VTH Variable

Variable VGS − VTH Constant

√ ID

gm ∝ ID

gm ∝

gm ∝ VGS − VTH

gm ∝

W L

Variable VGS − VTH Constant gm ∝ W L gm ∝

W L

1 VGS − VTH

√ That is, (1) gm is proportional to W/L for a given ID , and (2) gm is proportional to ID for a given W/L. Moreover, dividing Eq. (6.45) by (6.17) gives gm =

2ID , VGS − VTH

(6.47)

revealing that (1) gm is linearly proportional to ID for a given VGS − VTH , and (2) gm is inversely proportional to VGS − VTH for a given ID . Summarized in Table 6.1, these dependencies prove critical in understanding performance trends of MOS devices and have no counterpart in bipolar transistors.11 Among these three expressions for gm, Eq. (6.46) is more frequently used because ID may be predetermined by power dissipation requirements. Example 6.11

For a MOSFET operating in saturation, how do gm and VGS − VTH change if both W/L and ID are doubled?

Solution

Equation (6.46) indicates that gm is also doubled. Moreover, Eq. (6.17) suggests that the overdrive remains constant. These results can be understood intuitively if we view the doubling of W/L and ID as shown in Fig. 6.27. Indeed, if VGS remains constant and the width of the device is doubled, it is as if two transistors carrying equal currents are placed in parallel, thereby doubling the transconductance. The reader can show that this trend applies to any type of transistor. V GS V GS

V DS

Figure 6.27 Exercise

V DS

Equivalence of a wide MOSFET to two in parallel.

How do gm and VGS − VTH change if only W and ID are doubled? There is some resemblance between the second column and the behavior of gm = IC /VT . If the bipolar transistor width is increased while VBE remains constant, then both IC and gm increase linearly.

11

266

Chapter 6 Physics of MOS Transistors 6.2.5 Velocity Saturation∗ Recall from Section 2.1.3 that at high electric fields, carrier mobility degrades, eventually leading to a constant velocity. Owing to their very short channels (e.g., 0.1 μm), modern MOS devices experience velocity saturation even with drain-source voltages as low as 1 V. As a result, the I/V characteristics no longer follow the square-law behavior. Let us examine the derivations in Section 6.2.2 under velocity saturation conditions. Denoting the saturated velocity by vsat , we have ID = vsat · Q

(6.48)

= vsat · WCox (VGS − VTH ).

(6.49)

Interestingly, ID now exhibits a linear dependence on VGS − VTH and no dependence on L.12 We also recognize that gm =

∂ID ∂VGS

(6.50)

= vsat WCox ,

(6.51)

a quantity independent of L and ID . 6.2.6 Other Second-Order Effects Body Effect In our study of MOSFETs, we have assumed that both the source and the substrate (also called the “bulk” or the “body”) are tied to ground. However, this condition need not hold in all circuits. For example, if the source terminal rises to a positive voltage while the substrate is at zero, then the source-substrate junction remains reverse-biased and the device still operates properly. Figure 6.28 illustrates this case. The source terminal is tied to a potential VS with respect to ground while the substrate is grounded through a p+ contact.13 The dashed line added to the transistor symbol indicates the substrate terminal. We denote the voltage difference between the source and the substrate (the bulk) by VSB .

VS

Substrate Contact

VG

VD VD

p+

n+

n+

VG VS

p -Substrate

Figure 6.28

∗

Body effect.

This section can be skipped in a first reading. Of course, if L is increased substantially, while VDS remains constant, then the device experiences less velocity saturation and Eq. (6.49) is not accurate. 13 The p+ island is necessary to achieve an “ohmic” contact with low resistance. 12

6.3 MOS Device Models

267

An interesting phenomenon occurs as the source-substrate potential difference departs from zero: the threshold voltage of the device changes. In particular, as the source becomes more positive with respect to the substrate, VTH increases. Called “body effect,” this phenomenon is formulated as VTH = VTH0 + γ ( |2φF + VSB | − |2φF |), (6.52) where VTH0 denotes the threshold voltage with VSB = 0 (as studied earlier), √ and γ and φF are technology-dependent parameters having typical values of 0.4 V and 0.4 V, respectively. Example 6.12

In the circuit of Fig. 6.28, assume VS = 0.5 V, VG = VD = 1.4 V, μnCox = 100 μA/V2 , W/L = 50, and VTH0 = 0.6 V. Determine the drain current if λ = 0.

Solution

Since the source-body voltage, VSB = 0.5 V, Eq. (6.52) and the typical values for γ and φF yield VTH = 0.698 V.

(6.53)

Also, with VG = VD , the device operates in saturation (why?) and hence ID =

W 1 μnCox (VG − VS − VTH )2 2 L

= 102 μA. Exercise

(6.54) (6.55)

Sketch the drain current as a function of VS as VS goes from zero to 1 V.

Body effect manifests itself in some analog and digital circuits and is studied in more advanced texts. We neglect body effect in this book. Subthreshold Conduction The derivation of the MOS I-V characteristic has assumed that the transistor abruptly turns on as VGS reaches VTH . In reality, formation of the channel is a gradual effect, and the device conducts a small current even for VGS < VTH . Called “subthreshold conduction,” this effect has become a critical issue in modern MOS devices and is studied in more advanced texts.

6.3

MOS DEVICE MODELS With our study of MOS I-V characteristics in the previous section, we now develop models that can be used in circuit analysis and design. 6.3.1 Large-Signal Model For arbitrary voltage and current levels, we must resort to Eqs. (6.9) and (6.34) to express the device behavior: W 1 2 ID = μnCox Triode Region (6.56) 2(VGS − VTH )VDS − VDS 2 L ID =

W 1 μnCox (VGS − VTH )2 (1 + λVDS ) Saturation Region 2 L

(6.57)

268

Chapter 6 Physics of MOS Transistors VGS < V TH VDS < VGS – V TH G

D 1 2

ID

2

μ n C ox W (VGS – V TH ( (1 + λVDS ) L

S (a)

VGS < V TH

VGS < V TH VDS >> 2 (VGS – V TH (

VDS > VGS – V TH G

D

ID

1 2

G

D

2 ] μ n C ox W [ 2 (VGS – V TH ( VDS + VDS L

R on =

S

S (b)

Figure 6.29

1 W μ n C ox (VGS – V TH ( L

(c)

MOS models for (a) saturation region, (b) triode region, (c) deep triode region.

In the saturation region, the transistor acts as a voltage-controlled current source, lending itself to the model shown in Fig. 6.29(a). Note that ID does depend on VDS and is therefore not an ideal current source. For VDS < VGS − VTH , the model must reflect the triode region, but it can still incorporate a voltage-controlled current source, as depicted in Fig. 6.29(b). Finally, if VDS 2(VGS − VTH ), the transistor can be viewed as a voltage-controlled resistor [Fig. 6.29(c)]. In all three cases, the gate remains an open circuit to represent the zero gate current.

Example 6.13

Sketch the drain current of M1 in Fig. 6.30(a) versus V1 as V1 varies from zero to VDD . Assume λ = 0. VDD

ID

M1 V1 VDD – V TH V1 (a)

Figure 6.30 Solution

(b)

(a) Simple MOS circuit, (b) variation of ID with V1 .

Noting that the device operates in saturation (why?), we write ID = =

1 W μnCox (VGS − VTH )2 2 L

(6.58)

1 W μnCox (VDD − V1 − VTH )2 . 2 L

(6.59)

6.3 MOS Device Models

269

At V1 = 0, VGS = VDD and the device carries maximum current. As V1 rises, VGS falls and so does ID . If V1 reaches VDD − VTH , VGS drops to VTH , turning the transistor off. The drain current thus varies as illustrated in Fig. 6.30(b). Note that, owing to body effect, VTH varies with V1 if the substrate is tied to ground. Exercise

Repeat the above example if the gate of M1 is tied to a voltage equal to 1.5 V and VDD = 2 V.

6.3.2 Small-Signal Model If the bias currents and voltages of a MOSFET are only slightly disturbed by signals, the nonlinear, large-signal models can be reduced to linear, small-signal representations. The development of the model proceeds in a manner similar to that in Chapter 4 for bipolar devices. Of particular interest to us in this book is the small-signal model for the saturation region. Viewing the transistor as a voltage-controlled current source, we draw the basic model as in Fig. 6.31(a), where i D = gmvGS and the gate remains open. To represent channel-length modulation, i.e., variation of i D with vDS , we add a resistor as in Fig. 6.31(b): rO =

=

∂ID ∂VDS

−1 (6.60)

1 . 1 W μnCox (VGS − VTH )2 · λ 2 L

(6.61)

Since channel-length modulation is relatively small, the denominator of Eq. (6.61) can be approximated as ID · λ, yielding rO ≈

G

D

g v GS

v GS

m

S (a)

Figure 6.31

1 . λID

(6.62)

G

D

g v GS

v GS

m

rO

S (b)

(a) Small-signal model of MOSFET, (b) inclusion of channel-length modulation.

270

Chapter 6 Physics of MOS Transistors

Example 6.14

A MOSFET is biased at a drain current of 0.5 mA. If μnCox = 100 μA/V2 , W/L = 10, and λ = 0.1 V−1 , calculate its small-signal parameters.

Solution

We have

gm = =

2μnCox

W ID L

(6.63)

1 . 1 k

(6.64)

1 λID

(6.65)

= 20 k.

(6.66)

Also, rO =

This means that the intrinsic gain, gmrO (Chapter 4), is equal to 20 for this choice of device dimensions and bias current. Exercise

6.4

Repeat the above example if W/L is doubled.

PMOS TRANSISTOR Having seen both npn and pnp bipolar transistors, the reader may wonder if a p-type counterpart exists for MOSFETs. Indeed, as illustrated in Fig. 6.32(a), changing the doping polarities of the substrate and the S/D areas results in a “PMOS” device. The channel now consists of holes and is formed if the gate voltage is below the source potential by one threshold voltage. That is, to turn the device on, VGS < VTH , where VTH itself is negative. Following the conventions used for bipolar devices, we draw the PMOS device as in Fig. 6.32(b), with the source terminal identified by the arrow and placed G S

D

p+

p+

S G

n -substrate

ID D

(a) Triode Region

> VTHP

(b) Edge of Saturation

Saturation Region

VTHP < VTHP (c)

Figure 6.32 (a) Structure of PMOS device, (b) PMOS circuit symbol, (c) illustration of triode and saturation regions based on gate and drain voltages.

6.4 PMOS Transistor

271

on top to emphasize its higher potential. The transistor operates in the triode region if the drain voltage is near the source potential, approaching saturation as VD falls to VG − VTH = VG + |VTH |. Figure 6.32(c) conceptually illustrates the gate-drain voltages required for each region of operation. We say that if VDS of a PMOS (NMOS) device is sufficiently negative (positive), then it is in saturation.

Example 6.15

In the circuit of Fig. 6.33, determine the region of operation of M1 as V1 goes from VDD to zero. Assume VDD = 2.5 V and |VTH | = 0.5 V. VDD M1 V1 1V

Figure 6.33 Solution

Simple PMOS circuit.

For V1 = VDD , VGS = 0 and M1 is off. As V1 falls and approaches VDD − |VTH |, the gatesource potential is negative enough to form a channel of holes, turning the device on. At this point, VG = VDD − |VTH | = +2 V while VD = +1 V; i.e., M1 is saturated [Fig. 6.32(c)]. As V1 falls further, VGS becomes more negative and the transistor current rises. For V1 = +1 V − |VTH | = 0.5 V, M1 is at the edge of the triode region. As V1 goes below 0.5 V, the transistor enters the triode region further.

The voltage and current polarities in PMOS devices can prove confusing. Using the current direction shown in Fig. 6.32(b), we express ID in the saturation region as W 1 ID,sat = − μ pCox (VGS − VTH )2 (1 − λVDS ), 2 L

(6.67)

where λ is multiplied by a negative sign.14 In the triode region, W 1 2 . 2(VGS − VTH )VDS − VDS ID,tri = − μ pCox 2 L

(6.68)

Alternatively, both equations can be expressed in terms of absolute values: |ID,sat | =

1 W μ pCox (|VGS | − |VTH |)2 (1 + λ|VDS |) 2 L

(6.69)

|ID,tri | =

W 1 2 μ pCox 2(|VGS | − |VTH |)|VDS | − VDS . 2 L

(6.70)

The small-signal model of PMOS transistor is identical to that of NMOS devices (Fig. 6.31). The following example illustrates this point. 14 To make this equation more consistent with that of NMOS devices [Eq. (6.34)], we can define λ itself to be negative and express ID as (1/2)μ pCox (W/L)(VGS − VTH )2 (1 + λVDS ). But a negative λ carries little physical meaning.

272

Chapter 6 Physics of MOS Transistors

Example 6.16

For the configurations shown in Fig. 6.34(a), determine the small-signal resistances RX and RY . Assume λ = 0.

RX

M2 VDD M2

iX vx

M1

v1

gm1v 1

iY

r O1

v1

gm2v 1

r O2

vY (a)

RY

(b)

(c)

Figure 6.34 (a) Diode-connected NMOS and PMOS devices, (b) small-signal model of (a), (c) small-signal model of (b).

Solution

For the NMOS version, the small-signal equivalent appears as depicted in Fig. 6.34(b), yielding RX =

vX iX

vX = gm1 vX + rO1 =

(6.71)

1 iX

1 ||rO1 . gm1

(6.72)

(6.73)

For the PMOS version, we draw the equivalent as shown in Fig. 6.34(c) and write vY iY 1 vY = gm2 vY + rO1 i Y

RY =

=

1 ||rO2 . gm2

(6.74)

(6.75)

(6.76)

In both cases, the small-signal resistance is equal to 1/gm if λ → 0. In analogy with their bipolar counterparts [Fig. 4.44(a)], the structures shown in Fig. 6.34(a) are called “diode-connected” devices and act as two-terminal components: we will encounter many applications of diode-connected devices in Chapters 9 and 10.

Owing to the lower mobility of holes (Chapter 2), PMOS devices exhibit a poorer performance than NMOS transistors. For example, Eq. (6.46) indicates that the transconductance of a PMOS device is lower for a given drain current. We therefore prefer to use NMOS transistors wherever possible.

6.6 Comparison of Bipolar and MOS Devices

6.5

273

CMOS TECHNOLOGY Is it possible to build both NMOS and PMOS devices on the same wafer? Figures 6.2(a) and 6.32(a) reveal that the two require different types of substrate. Fortunately, a local n-type substrate can be created in a p-type substrate, thereby accommodating PMOS transistors. As illustrated in Fig. 6.35, an “n-well” encloses a PMOS device while the NMOS transistor resides in the p-substrate. NMOS Device

PMOS Device

G

G

B

S

D

S

D

B

p+

n+

n+

p+

p+

n+

n -well p -substrate

Figure 6.35

CMOS technology.

Called “complementary MOS” (CMOS) technology, the above structure requires more complex processing than simple NMOS or PMOS devices. In fact, the first few generations of MOS technology contained only NMOS transistors,15 and the higher cost of CMOS processes seemed prohibitive. However, many significant advantages of complementary devices eventually made CMOS technology dominant and NMOS technology obsolete.

6.6

COMPARISON OF BIPOLAR AND MOS DEVICES Having studied the physics and operation of bipolar and MOS transistors, we can now compare their properties. Table 6.2 shows some of the important aspects of each device. Note that the exponential IC -VBE dependence of bipolar devices accords them a higher transconductance for a given bias current.

TABLE 6.2 Comparison of bipolar and MOS transistors.

Bipolar Transistor

MOSFET

Exponential Characteristic Active: VCB > 0 Saturation: VCB < 0 Finite Base Current Early Effect Diffusion Current —

Quadratic Characteristic Saturation: VDS > VGS − VTH (NMOS) Triode: VDS < VGS − VTH (NMOS) Zero Gate Current Channel-Length Modulation Drift Current Voltage-Dependent Resistor

15

The first Intel microprocessor, the 4004, was realized in NMOS technology.

274

Chapter 6 Physics of MOS Transistors

PROBLEMS In the following problems, unless otherwise stated, assume μnCox = 200 μA/V2 , μ pCox = 100 μA/V2 , and VTH = 0.4 V for NMOS devices and −0.4 V for PMOS devices. *6.1. Two identical MOSFETs are placed in series as shown in Fig. 6.36. If both devices operate as resistors, explain intuitively why this combination is equivalent to a single transistor, Meq . What are the width and length of Meq ?

M1 W L

M2

M eq

W L

Figure 6.36

6.2. What should be the value of oxide capacitance required to store a charge of 25 fc in a NMOS device, if W = 5 μm, VGS − VTH = 2 V? Assume VDS = 0 V. 6.3. Assuming ID is constant, solve Eq. (6.7) to obtain an expression for V(x). Plot both V(x) and dV/dx as a function of x for different values of W or VTH . *6.4. The drain current of a MOSFET in the triode region is expressed as ID = μnCox

W 1 2 . (VGS − VTH )VDS − VDS L 2 (6.77)

Suppose the values of μnCox and W/L are unknown. Is it possible to determine these quantities by applying different values of VGS − VTH and VDS and measuring ID ? 6.5. A MOSFET carries a drain current of 2 mA with VDS = 0.4 V in saturation. Determine the change in VDS required to double the drain current and λ = 0.1 V−1 . What is the device output impedance? 6.6. A NMOS device operating in the saturation region with W/L = 10, carries a current of 5 mA. Calculate the transconductance of the device.

6.7. For a MOS transistor biased in the triode region, we can define an incremental drainsource resistance as rDS,tri =

∂ID ∂VDS

−1

.

(6.78)

Derive an expression for this quantity. 6.8. A NMOS transistor is designed to be used as a resistor of resistance 500 in certain application, with W/L = 12. Find the overdrive voltage needed. 6.9. It is possible to define an “intrinsic time constant” for a MOSFET operating as a resistor: τ = RonCGS ,

(6.79)

where CGS = WLCox . Obtain an expression for τ and explain what the circuit designer must do to minimize the time constant. 6.10. Calculate the value of drain current in the circuit shown in Fig. 6.37, with W = 5 μm, L = 0.5 μm and λ = 0. VDD = 3 V RD

20 k Ω

M1 Figure 6.37

6.11. In the circuit shown in Fig. 6.37, what value of R is required to get a current of 75 μA with W = 5 μm, L = 0.5 μm and λ = 0? 6.12. For MOS devices with very short channel lengths, the square-law behavior is not valid, and we may instead write: ID = WCox (VGS − VTH )vsat ,

(6.80)

where vsat is a relatively constant velocity. Determine the transconductance of such a device.

Problems

275

6.13. Advanced MOS devices do not follow the where α is less than 2. Determine the square-law behavior expressed by Eq. (6.17). transconductance of such a device. A somewhat better approximation is: *6.14. Determine the region of operation of M1 in each of the circuits shown in Fig. 6.38. W 1 α ID = μnCox (VGS − VTH ) , (6.81) *6.15. Determine the region of operation of M1 in 2 L each of the circuits shown in Fig. 6.39.

M1

M1 1V

1V

(a) 1V

(b) 1V

M1

0.2 V

0.2 V

M1

0.2 V

0.7 V

(c)

(d)

Figure 6.38

0.5 V

M1 0.5 V

2V 1.5 V

(a)

1.5 V

2V

M1 0.5 V

0.5 V

(b)

M1 0.5 V

1.5 V

(d)

(c)

0.5 V

M1

0.5 V (f)

M1

0.5 V

M1

1V

0.5 V (g)

0.5 V

M1

(e)

M1

0.5 V

M1

1.5 V

0.5 V

(h)

(i)

Figure 6.39

6.16. Two current sources realized by identical MOSFETs (Fig. 6.40) match to within 1%, i.e., 0.99ID2 < ID1 < 1.01ID2 . If VDS1 = 0.5 V and VDS2 = 1 V, what is the maximum tolerable value of λ?

I D1 VB

Figure 6.40

M1

I D2 M2

276

Chapter 6 Physics of MOS Transistors

6.17. Assume λ = 0, compute W/L of M1 in Fig. 6.41 such that the device operates at the edge of saturation.

6.20. Compute the value of W/L for M1 in Fig. 6.44 for a bias current of 0.5 mA. Assume λ = 0.

VDD = 1.8 V

VDD = 1.8 V

1 kΩ

RD

M1

600 Ω

M1

1V

Figure 6.44

Figure 6.41

6.18. In the Fig. 6.42, what is the current when VGS = 2 VTH ? Find the region in which the device operates.

6.21. Calculate the bias current of M1 in Fig. 6.45 if λ = 0.

VDD = 1.8 V

VDD = 1.8 V

RD

500 Ω

RD

M 1 10 0.18

M1

VB

500 Ω

Figure 6.45

Figure 6.42

6.19. In the Fig. 6.43, compute the value of W/L required to operate the transistor M1 in saturation region.

**6.22. Sketch IX as a function of VX for the circuits shown in Fig. 6.46. Assume VX goes from 0 to VDD = 1.8 V. Also, λ = 0. Determine at what value of VX the device changes its region of operation. 6.23. Calculate the value of W/L required to get a drain current of 1 mA in the circuit shown in Fig. 6.47. Assume λ = 0.

VDD = 1.8 V RD = 500 Ω

6.24. In the circuit of Fig. 6.48 W/L = 10/0.18 and λ = 0. What is the value of current flowing through M1 , assuming that the device operating at the edge of saturation?

M1 W L Figure 6.43

IX

VDD = 1.8 V

IX

IX

M1 M1 VX (a)

Figure 6.46

1V 1V

M1

(b)

VX

M1

(c)

VX

IX

(d)

VX

Problems

277

VDD = 1.8 V VDD = 1.8 V

RD

RD

500 Ω

M1

0.7 V

M1 Figure 6.47

1 kΩ

Figure 6.48 VDD = 1.8 V RD

100 Ω

RD

M1

1V

VDD = 1.8 V

VDD = 1.8 V

5 kΩ

1 mA

M1

(a)

M1

(b)

(c)

VDD = 1.8 V M1

VDD = 1.8 V M1 0.5 mA

2 kΩ

(d)

(e)

Figure 6.49

6.25. A NMOS device operating in the deep all transistors operate in saturation and triode region with λ = 0 must provide a λ = 0. resistance of 20 k. Determine the required *6.31. Determine the region of operation of M1 in value of W/L if VGS = 0.5 V. each circuit shown in Fig. 6.51. 6.26. Determine the transconductance of a *6.32. Determine the region of operation of M1 in MOSFET operating in saturation, if each circuit shown in Fig. 6.52. W/L = 10/0.18 and ID = 3 mA. If W/L ratio is doubled, compute the new value of 6.33. If λ = 0, what value of W/L places the transistor M1 at the edge of saturation in transconductance keeping ID constant. Fig. 6.53? −1 6.27. If λ = 0.1 V and W/L = 20/0.18, construct the small-signal model of each of the circuits shown in Fig. 6.49.

6.34. If W/L = 10/0.18 and λ = 0, determine the operating point of M1 in each circuit depicted in Fig. 6.54.

6.28. Assuming a constant VDS , a graph of gmro verses (VGS − VTH ) of a NMOS gives a **6.35. Sketch IX as a function of VX for the circuits slope of 50 V−1 . Find the W/L ratio if shown in Fig. 6.55. Assume VX goes from λ = 0.1 V −1 and ID = 0.5 mA. 0 to VDD = 1.8 V. Also, λ = 0. Determine at what value of VX the device changes its 6.29. A NMOS device has a current of 0.5 mA region of operation. with W/L = 5 and λ = 0.1 V −1 . Calculate the intrinsic gain gm ro . 6.36. Construct the small-signal model of each 6.30. Construct the small-signal model of the circuits depicted in Fig. 6.50. Assume

circuit shown in Fig. 6.56 if all of the transistors operate in saturation and λ = 0.

278

Chapter 6 Physics of MOS Transistors VDD

VDD

RD

RD

Vout

Vout V in

M2 V in

VDD

RD

Vout V in

M1

VB

M1

M2

M1 (a)

M2 (b)

(c)

VDD

VDD V in

M1

RD Vout

Vout

M2

V in M2

VB

(d)

M1

(e)

Figure 6.50

M1

2V

2V

0.3 V

0.3 V (a)

1V

M1

0.3 V

M1

(b)

M1

0.6 V

(c)

(d)

Figure 6.51 M1

M1

1.5 V

0.9 V

0.9

0.5 V (a)

(b)

M1

M1

0.9 V

0.4 V

1V

0.9 V 0.4 V

(c)

(d)

Figure 6.52

VDD = 1.8 V M1

VDD = 1.8 V

1 kΩ

1 kΩ

M1

1 kΩ (a)

Figure 6.53

VDD = 1.8 V

M1

500 Ω

M1

1V

VDD = 1.8 V

Figure 6.54

(b)

(c)

Problems VDD = 1.8 V

VDD = 1.8 V

M1 VX

279

M1 1V

IX

IX

(a)

VX

(b)

VDD = 1.8 V IX

M1

VX

M1

IX

VX

(d)

(c)

Figure 6.55

V in VDD

VDD

RS V in

V in

Vb

M1

M1

Vout Vout

M1

R1

RD

Vout RD

M2

(b)

(a)

(c)

VDD V in

VDD R2

M1 Vout

V in

M2

(d)

Vout

M1

RD

R1

M2

RD

M2 R1

(e)

Figure 6.56

6.37. For the circuit shown in Fig. 6.57, draw the ac equivalent circuit assuming M1 and M2 VDD M2 V in

Vout M1

–VDD Figure 6.57

operate in saturation and each has channel length modulation coefficients λn and λ p respectively. Determine the small signal voltage gain of the circuit.

280

Chapter 6 Physics of MOS Transistors

SPICE PROBLEMS In the following problems, use the MOS models and source/drain dimensions given in Appendix A. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD , respectively.

6.2. Plot the input/output characteristic of the stage shown in Fig. 6.59 for 0 < Vin < 1.8 V. At what value of Vin does the slope (gain) reach a maximum? VDD = 1.8 V

6.1. For the circuit shown in Fig. 6.58, plot VX as a function of IX for 0 < IX < 3 mA. Explain the sharp change in VX as IX exceeds a certain value.

500 Ω

M1 V in

Vout 10 0.18

Figure 6.59 M1 0.9 V

2 0.18

VX

6.3. For the arrangements shown in Fig. 6.60, plot ID as a function of VX as VX varies from 0 to 1.8 V. Can we say these two arrangements are equivalent?

IX

Figure 6.58

IX M1 0.9 V

5 0.36

IX M1 VX 0.9 V

M2

(a)

Figure 6.60

5 0.36 5 0.36

(b)

VX

Chapter

7

CMOS Amplifiers

Most CMOS amplifiers have identical bipolar counterparts and can therefore be analyzed in the same fashion. Our study in this chapter parallels the developments in Chapter 5, identifying both similarities and differences between CMOS and bipolar circuit topologies. It is recommended that the reader review Chapter 5, specifically, Section 5.1. We assume the reader is familiar with concepts such as I/O impedances, biasing, and dc and small-signal analysis. The outline of the chapter is shown below.

General Concepts

MOS Amplifiers

• Biasing of MOS Stages

• Common–Source Stage

• Realization of Current Sources

7.1

➤

• Common–Gate Stage • Source Follower

GENERAL CONSIDERATIONS 7.1.1 MOS Amplifier Topologies Recall from Section 5.3 that the nine possible circuit topologies using a bipolar transistor in fact reduce to three useful configurations. The similarity of bipolar and MOS small-signal models (i.e., a voltage-controlled current source) suggests that the same must hold for MOS amplifiers. In other words, we expect three basic CMOS amplifiers: the “common-source” (CS) stage, the “common-gate” (CG) stage, and the “source follower.”

7.1.2 Biasing Depending on the application, MOS circuits may incorporate biasing techniques that are quite different from those described in Chapter 5 for bipolar stages. Most of these techniques are beyond the scope of this book and some methods are studied in Chapter 5. Nonetheless, it is still instructive to apply some of the biasing concepts of Chapter 5 to MOS stages.

281

282

Chapter 7 CMOS Amplifiers VDD = 1.8 V 4 kΩ

RD

R1 Y

X 10 k Ω

Figure 7.1

ID M1

RS

R2

1 kΩ

MOS stage with biasing.

Consider the circuit shown in Fig. 7.1, where the gate voltage is defined by R1 and R2 . We assume M1 operates in saturation. Also, in most bias calculations, we can neglect channel-length modulation. Noting that the gate current is zero, we have VX =

R2 VDD . R1 + R 2

(7.1)

Since VX = VGS + ID RS , R2 VDD = VGS + ID RS . R1 + R 2

(7.2)

Also, ID =

W 1 μnCox (VGS − VTH )2 . 2 L

(7.3)

Equations (7.2) and (7.3) can be solved to obtain ID and VGS , either by iteration or by finding ID from Eq. (7.2) and replacing for it in Eq. (7.3): R2 1 W 1 VDD − VGS = μnCox (VGS − VTH )2 . (7.4) R1 + R 2 RS 2 L That is,

VGS = −(V1 − VTH ) +

2 (V1 − VTH )2 − VTH +

= −(V1 − VTH ) +

V12

+ 2V1

2R2 V1 VDD , R1 + R 2

R2 VDD − VTH , R1 + R 2

(7.5)

(7.6)

where V1 =

1 . W μnCox RS L

(7.7)

This value of VGS can then be substituted in Eq. (7.2) to obtain ID . Of course, VY must exceed VX − VTH to ensure operation in the saturation region. Example 7.1

Determine the bias current of M1 in Fig. 7.1 assuming VTH = 0.5 V, μnCox = 100 μA/V2 , W/L = 5/0.18, and λ = 0. What is the maximum allowable value of RD for M1 to remain in saturation?

7.1 General Considerations Solution

283

We have VX =

R2 VDD R1 + R 2

= 1.286 V.

(7.8) (7.9)

With an initial guess VGS = 1 V, the voltage drop across RS can be expressed as VX − VGS = 286 mV, yielding a drain current of 286 μA. Substituting for ID in Eq. (7.3) gives the new value of VGS as 2ID (7.10) VGS = VTH + W μnCox L = 0.954 V.

(7.11)

Consequently, ID =

VX − VGS RS

= 332 μA,

(7.12) (7.13)

and hence VGS = 0.989 V.

(7.14)

This gives ID = 297 μA. As seen from the iterations, the solutions converge more slowly than those encountered in Chapter 5 for bipolar circuits. This is due to the quadratic (rather than exponential) ID -VGS dependence. We may therefore utilize the exact result in Eq. (7.6) to avoid lengthy calculations. Since V1 = 0.36 V, VGS = 0.974 V

(7.15)

VX − VGS RS

(7.16)

and ID =

= 312 μA.

(7.17)

The maximum allowable value of RD is obtained if VY = VX − VTH = 0.786 V. That is, RD =

VDD − VY ID

= 3.25 k. Exercise

What is the value of R2 that places M1 at the edge of saturation?

(7.18) (7.19)

284

Chapter 7 CMOS Amplifiers

Example 7.2

In the circuit of Example 7.1, assume M1 is in saturation and RD = 2.5 k and compute (a) the maximum allowable value of W/L and (b) the minimum allowable value of RS (with W/L = 5/0.18). Assume λ = 0.

Solution

(a) As W/L becomes larger, M1 can carry a larger current for a given VGS . With RD = 2.5 k and VX = 1.286 V, the maximum allowable value of ID is given by ID =

VDD − VY RD

= 406 μA.

(7.20) (7.21)

The voltage drop across RS is then equal to 406 mV, yielding VGS = 1.286 V− 0.406 V = 0.88 V. In other words, M1 must carry a current of 406 μA with VGS = 0.88 V: W 1 μnCox (VGS − VTH )2 2 L W 406 μA = (50 μA/V2 ) (0.38 V)2 ; L ID =

(7.22) (7.23)

thus, W = 56.2. (7.24) L (b) With W/L = 5/0.18, the minimum allowable value of RS gives a drain current of 406 μA. Since 2ID (7.25) VGS = VTH + W μnCox L = 1.041 V,

(7.26)

the voltage drop across RS is equal to VX − VGS = 245 mV. It follows that RS =

VX − VGS ID

= 604 . Exercise

(7.27) (7.28)

Repeat the above example if VTH = 0.35 V.

The self-biasing technique of Fig. 5.22 can also be applied to MOS amplifiers. Depicted in Fig. 7.2, the circuit can be analyzed by noting that M1 is in saturation (why?) and the voltage drop across RG is zero. Thus, ID RD + VGS + RS ID = VDD .

(7.29)

Finding VGS from this equation and substituting it in Eq. (7.3), we have ID =

W 1 μnCox [VDD − (RS + RD )ID − VTH ]2 , 2 L

(7.30)

7.1 General Considerations

285

VDD RD RG ID M1 RS

Figure 7.2

Self-biased MOS stage.

where channel-length modulation is neglected. It follows that ⎡ ⎤ ⎢ 2 − 2⎣(VDD − VTH )(RS + RD ) + (RS + RD )2 ID

Example 7.3

⎥ I + (VDD − VTH )2 = 0. W⎦D μnCox L (7.31) 1

Calculate the drain current of M1 in Fig. 7.3 if μnCox = 100 μA/V2 , VTH = 0.5 V, and λ = 0. What value of RD is necessary to reduce ID by a factor of two? VDD = 1.8 V 1 kΩ

RD 20 k Ω

5 W M 1 L = 0.18 200 Ω

Figure 7.3

Solution

Example of self-biased MOS stage.

Equation (7.31) gives ID = 556 μA.

(7.32)

To reduce ID to 278 μA, we solve Eq. (7.31) for RD : RD = 2.867 k. Exercise

(7.33)

Repeat the above example if VDD drops to 1.2 V.

7.1.3 Realization of Current Sources MOS transistors operating in saturation can act as current sources. As illustrated in Fig. 7.4(a), an NMOS device serves as a current source with one terminal tied to ground, i.e., it draws current from node X to ground. On the other hand, a PMOS transistor

286

Chapter 7 CMOS Amplifiers

X Vb

VDD

X

Vb

VDD

Vb

M2

Vb

M1 Y (a)

VDD

Y

M1

M1

Y

X

(b)

(c)

(d)

(a) NMOS device operating as a current source, (b) PMOS device operating as a current source, (c) PMOS topology not operating as a current source, (d) NMOS topology not operating as a current source.

Figure 7.4

[Fig. 7.4(b)] draws current from VDD to node Y. If λ = 0, these currents remain independent of VX or VY (so long as the transistors are in saturation). It is important to understand that only the drain terminal of a MOSFET can draw a dc current and still present a high impedance. Specifically, NMOS or PMOS devices configured as shown in Figs. 7.4(c) and (d) do not operate as current sources because variation of VX or VY directly changes the gate-source voltage of each transistor, thus changing the drain current considerably. From another perspective, the small-signal model of these two structures is identical to that of the diode-connected devices in Fig. 6.34, revealing a small-signal impedance of only 1/gm (if λ = 0) rather than infinity.

7.2

COMMON-SOURCE STAGE 7.2.1 CS Core Shown in Fig. 7.5(a), the basic CS stage is similar to the common-emitter topology, with the input applied to the gate and the output sensed at the drain. For small signals, M1 converts the input voltage variations to proportional drain current changes, and RD transforms the drain currents to the output voltage. If channel-length modulation is neglected, the small-signal model in Fig. 7.5(b) yields vin = v1 and vout = −gmv1 RD . That is, vout = −gmRD , vin

(7.34)

a result similar to that obtained for the common emitter stage in Chapter 5.

VDD RD

v in Vout

ID V in

M1

v out g v1

v1

m

Output Sensed at Drain

Input Applied to Gate (a)

Figure 7.5

(a) Common-source stage, (b) small-signal mode.

(b)

RD

7.2 Common-Source Stage

287

The voltage gain of the CS stage is also limited by the supply voltage. Since gm = 2μnCox (W/L)ID , we have Av = − 2μnCox

W ID RD , L

(7.35)

concluding that if ID or RD is increased, so is the voltage drop across RD ( = ID RD ).1 For M1 to remain in saturation, VDD − RD ID > VGS − VTH ,

(7.36)

RD ID < VDD − (VGS − VTH ).

(7.37)

that is,

Example 7.4

Calculate the small-signal voltage gain of the CS stage shown in Fig. 7.6 if ID = 1 mA, μnCox = 100 μA/V2 , VTH = 0.5 V, and λ = 0. Verify that M1 operates in saturation. VDD = 1.8 V 1 kΩ

RD

v out 10 M1 W = L 0.18

v in

Figure 7.6

Solution

Example of CS stage.

We have

gm =

2μnCox

W ID L

(7.38)

1 . 300

(7.39)

Av = −gmRD

(7.40)

= 3.33.

(7.41)

= Thus,

To check the operation region, we first determine the gate-source voltage: 2ID VGS = VTH + W μnCox L = 1.1 V.

(7.42)

(7.43)

1 It is possible to raise the gain to some extent by increasing W, but “subthreshold conduction” eventually limits the transconductance. This concept is beyond the scope of this book.

288

Chapter 7 CMOS Amplifiers The drain voltage is equal to VDD − RD ID = 0.8 V. Since VGS − VTH = 0.6 V, the device indeed operates in saturation and has a margin of 0.2 V with respect to the triode region. For example, if RD is doubled with the intention of doubling Av , then M1 enters the triode region and its transconductance drops.

Exercise

What value of VTH places M1 at the edge of saturation?

Since the gate terminal of MOSFETs draws a zero current (at very low frequencies), we say the CS amplifier provides a current gain of infinity. By contrast, the current gain of a common-emitter stage is equal to β. Let us now compute the I/O impedances of the CS amplifier. Since the gate current is zero (at low frequencies), Rin = ∞,

(7.44)

a point of contrast to the CE stage (whose Rin is equal to rπ ). The high input impedance of the CS topology plays a critical role in many analog circuits. The similarity between the small-signal equivalents of CE and CS stages indicates that the output impedance of the CS amplifier is simply equal to Rout = RD .

(7.45)

This is also seen from Fig. 7.7. iX g v1

v1

Figure 7.7

vX

RD

m

Output impedance of CS stage.

In practice, channel-length modulation may not be negligible, especially if RD is large. The small-signal model of CS topology is therefore modified as shown in Fig. 7.8, revealing that Av = −gm(RD ||rO )

(7.46)

Rin = ∞

(7.47)

Rout = RD ||rO .

(7.48)

In other words, channel-length modulation and the Early effect impact the CS and CE stages, respectively, in a similar manner. iX v1

Figure 7.8

g v1 m

rO

RD

Effect of channel-length modulation on CS stage.

vX

7.2 Common-Source Stage Example 7.5

289

Assuming M1 operates in saturation, determine the voltage gain of the circuit depicted in Fig. 7.9(a) and plot the result as a function of the transistor channel length while other parameters remain constant. VDD

v in

Av

v out M1 L (a)

(b)

(a) CS stage with ideal current source as a load, (b) gain as a function of device channel length.

Figure 7.9

Solution

The ideal current source presents an infinite small-signal resistance, allowing the use of Eq. (7.46) with RD = ∞: Av = −gmrO . (7.49) This is the highest voltage gain that a single transistor can provide. Writing gm = 2μnCox (W/L)ID and rO = (λID )−1 , we have W 2μnCox L |Av | = . (7.50) √ λ ID This result may imply that |Av | falls as L increases, but recall from Chapter 6 that λ ∝ L−1 : 2μnCox WL . (7.51) |Av | ∝ ID Consequently, |Av | increases with L [Fig. 7.9(b)].

Exercise

Repeat the above example if a resistor of value R1 is tied between the gate and drain of M1 .

7.2.2 CS Stage With Current-Source Load As seen in the above example, the trade-off between the voltage gain and the voltage headroom can be relaxed by replacing the load resistor with a current source. The observations made in relation to Fig. 7.4(b) therefore suggest the use of a PMOS device as the load of an NMOS CS amplifier [Fig. 7.10(a)]. Let us determine the small-signal gain and output impedance of the circuit. Having a constant gate-source voltage, M2 simply behaves as a resistor equal to its output impedance [Fig. 7.10(b)] because v1 = 0 and hence gm2 v1 = 0. Thus, the drain node of M1 sees both rO1 and rO2 to ac ground. Equations (7.46) and (7.48) give Av = −gm1 (rO1 ||rO2 ) Rout = rO1 ||rO2 .

(7.52) (7.53)

290

Chapter 7 CMOS Amplifiers VDD Vb

VDD v1

M2

gm2v 1

v out v in

r O2

v out

M1

v in

r O1 M1

(a)

Figure 7.10

Example 7.6

(b)

(a) CS stage using a PMOS device as a current source, (b) small-signal model.

Figure 7.11 shows a PMOS CS stage using an NMOS current source load. Compute the voltage gain of the circuit. VDD v in

M2 v out

Vb

Figure 7.11

Solution

M1

CS stage using an NMOS device as current source.

Transistor M2 generates a small-signal current equal to gm2 vin , which then flows through rO1 ||rO2 , producing vout = −gm2 vin (rO1 ||rO2 ). Thus, Av = −gm2 (rO1 ||rO2 ).

Exercise

(7.54)

Calculate the gain if the circuit drives a loads resistance equal to RL .

7.2.3 CS Stage With Diode-Connected Load In some applications, we may use a diode-connected MOSFET as the drain load. Illustrated in Fig. 7.12(a), such a topology exhibits only a moderate gain due to the relatively low impedance of the diode-connected device (Section 7.1.3). With λ = 0, M2 acts as a smallsignal resistance equal to 1/gm2 , and Eq. (7.34) yields Av = −gm1 ·

1 gm2

2μnCox (W/L)1 ID = − 2μnCox (W/L)2 ID (W/L)1 . =− (W/L)2

(7.55)

(7.56)

(7.57)

7.2 Common-Source Stage VDD

VCC 1 g m2

Q2

M2 V in

Vout M1

291

r O2

Vout V in

v in

Q1

(a)

(b)

v out r O1

M1 (c)

Figure 7.12 (a) MOS stage using a diode-connected load, (b) bipolar counterpart, (c) simplified circuit of (a).

Interestingly, the gain is given by the dimensions of M1 and M2 and remains independent of process parameters μn and Cox and the drain current, ID . The reader may wonder why we did not consider a common-emitter stage with a diodeconnected load in Chapter 5. Shown in Fig. 7.12(b), such a circuit is not used because it provides a voltage gain of only unity: Av = −gm1 · =−

1 gm2

(7.58)

IC 1 1 · VT IC 2 /VT

≈ −1.

(7.59) (7.60)

The contrast between Eqs. (7.57) and (7.60) arises from a fundamental difference between MOS and bipolar devices: transconductance of the former depends on device dimensions whereas that of the latter does not. A more accurate expression for the gain of the stage in Fig. 7.12(a) must take channellength modulation into account. As depicted in Fig. 7.12(c), the resistance seen at the drain is now equal to (1/gm2 )||rO2 ||rO1 , and hence 1 (7.61) ||rO2 ||rO1 . Av = −gm1 gm2 Similarly, the output resistance of the stage is given by Rout =

Example 7.7

1 ||rO2 ||rO1 . gm2

Determine the voltage gain of the circuit shown in Fig. 7.13(a) if λ = 0. VDD V in

M2 Vout M1

Figure 7.13

CS stage with diode-connected PMOS device.

(7.62)

292

Chapter 7 CMOS Amplifiers

Solution

This stage is similar to that in Fig. 7.12(a), but with NMOS devices changed to PMOS transistors: M1 serves as a common-source device and M2 as a diode-connected load. Thus, 1 Av = −gm2 (7.63) ||rO1 ||rO2 . gm1

Exercise

Repeat the above example if the gate of M1 is tied to a constant voltage equal to 0.5 V.

7.2.4 CS Stage With Degeneration Recall from Chapter 5 that a resistor placed in series with the emitter of a bipolar transistor alters characteristics such as gain, I/O impedances, and linearity. We expect similar results for a degenerated CS amplifier. VDD RD

v in Vout

V in

v out g v1

v1

m

M1 RS

RS

(a)

Figure 7.14

RD

(b)

(a) CS stage with degeneration, (b) small-signal model.

Figure 7.14 depicts the stage along with its small-signal equivalent (if λ = 0). As with the bipolar counterpart, the degeneration resistor sustains a fraction of the input voltage change. From Fig. 7.14(b), we have vin = v1 + gmv1 RS

(7.64)

and hence v1 =

vin . 1 + gmRS

(7.65)

Since gmv1 flows through RD , vout = −gmv1 RD and gmRD vout =− vin 1 + gmRS =−

RD , 1 + RS gm

a result identical to that expressed by Eq. (5.157) for the bipolar counterpart.

(7.66) (7.67)

7.2 Common-Source Stage Example 7.8

293

Compute the voltage gain of the circuit shown in Fig. 7.15(a) if λ = 0. VDD RD

RD v out

Vout V in

v in

M1

1 g m2

M2

(a)

Figure 7.15

Solution

(b)

(a) Example of CS stage with degeneration, (b) simplified circuit.

Transistor M2 serves as a diode-connected device, presenting an impedance of 1/gm2 [Fig. 7.15(b)]. The gain is therefore given by Eq. (7.67) if RS is replaced with 1/gm2 : Av = −

Exercise

M1

RD . 1 1 + gm1 gm2

(7.68)

What happens if λ = 0 for M2 ?

In parallel with the developments in Chapter 5, we may study the effect of a resistor appearing in series with the gate (Fig. 7.16). However, since the gate current is zero (at low frequencies), RG sustains no voltage drop and does not affect the voltage gain or the I/O impedances. Effect of Transistor Output Impedance As with the bipolar counterparts, the inclusion of the transistor output impedance complicates the analysis and is studied in Problem 7.32. Nonetheless, the output impedance of the degenerated CS stage plays a critical role in analog design and is worth studying here. Figure 7.17 shows the small-signal equivalent of the circuit. Since RS carries a current equal to iX (why?), we have v1 = −iX RS . Also, the current through rO is equal to

VDD RD V in

Vout

RG M1 RS

Figure 7.16

CS stage with gate resistance.

294

Chapter 7 CMOS Amplifiers iX g v1

v1

m

rO

vX

RS

Figure 7.17

Output impedance of CS stage with degeneration.

iX − gmv1 = iX − gm(− iX RS ) = iX + gmiX RS . Adding the voltage drops across rO and RS and equating the result to vX , we have rO (iX + gmiX RS ) + iX RS = vX ,

(7.69)

vX = rO (1 + gmRS ) + RS iX

(7.70)

= (1 + gmrO )RS + rO

(7.71)

≈ gmrO RS + rO .

(7.72)

and hence

Alternatively, we observe that the model in Fig. 7.17 is similar to its bipolar counterpart in Fig. 5.46(a) but with rπ = ∞. Letting rπ → ∞ in Eqs. (5.196) and (5.197) yields the same results as above. As expected from our study of the bipolar degenerated stage, the MOS version also exhibits a “boosted” output impedance.

Example 7.9

Compute the output resistance of the circuit in Fig. 7.18(a) if M1 and M2 are identical.

R out

Vb

M1

R out

r O1

M1

1 r g m2 O2

M2 (a)

Figure 7.18

Solution

(b)

(a) Example of CS stage with degeneration, (b) simplified circuit.

The diode-connected device M2 can be represented by a small-signal resistance of (1/gm2 )||rO2 ≈ 1/gm2 . Transistor M1 is degenerated by this resistance, and from Eq. (7.70): 1 1 + Rout = rO1 1 + gm1 gm2 gm2

(7.73)

7.2 Common-Source Stage

295

which, since gm1 = gm2 = gm, reduces to Rout = 2rO1 +

1 gm

(7.74)

≈ 2rO1 .

(7.75)

Exercise

Do the results remain unchanged if M2 is replaced with a diode-connected PMOS device?

Example 7.10

Determine the output resistance of the circuit in Fig. 7.19(a) and compare the result with that in the above example. Assume M1 and M2 are in saturation. R out

V b2

M1

V b1

M2

R out

(a)

Figure 7.19

Solution

r O1

M1

r O2 (b)

(a) Example of CS stage with degeneration, (b) simplified circuit.

With its gate-source voltage fixed, transistor M2 operates as a current source, introducing a resistance of rO2 from the source of M1 to ground [Fig. 7.19(b)]. Equation (7.71) can therefore be written as Rout = (1 + gm1rO1 )rO2 + rO1

(7.76)

≈ gm1rO1rO2 + rO1 .

(7.77)

Assuming gm1rO2 1 (which is valid in practice), we have Rout ≈ gm1rO1rO2 .

(7.78)

We observe that this value is quite higher than that in Eq. (7.75). Exercise

Repeat the above example for the PMOS counterpart of the circuit.

7.2.5 CS Core With Biasing The effect of the simple biasing network shown in Fig. 7.1 is similar to that analyzed for the bipolar stage in Chapter 5. Depicted in Fig. 7.20(a) along with an input coupling capacitor (assumed a short circuit), such a circuit no longer exhibits an infinite input impedance: Rin = R1 ||R2 .

(7.79)

296

Chapter 7 CMOS Amplifiers VDD RD

R1 V in

VDD

C1 M1 R2

RS

RD

R1

Vout V in

M1 R2

RD

R1

Vout

RG C1

(a)

VDD

V in

RS

(b)

Vout

RG C1 M1 R in

R2

RS

C2

(c)

Figure 7.20 (a) CS stage with input coupling capacitor, (b) inclusion of gate resistance, (c) use of bypass capacitor.

Thus, if the circuit is driven by a finite source impedance [Fig. 7.20(b)], the voltage gain falls to R1 ||R2 −RD Av = · , (7.80) RG + R1 ||R2 1 + RS gm where λ is assumed to be zero. As mentioned in Chapter 5, it is possible to utilize degeneration for bias point stability but eliminate its effect on the small-signal performance by means of a bypass capacitor [Fig. 7.20(c)]. Unlike the case of bipolar realization, this does not alter the input impedance of the CS stage: Rin = R1 ||R2 ,

(7.81)

but raises the voltage gain: Av = −

R1 ||R2 gmRD . RG + R1 ||R2

(7.82)

Example 7.11

Design the CS stage of Fig. 7.20(c) for a voltage gain of 5, an input impedance of 50 k, and a power budget of 5 mW. Assume μnCox = 100 μA/V2 , VTH = 0.5 V, λ = 0, and VDD = 1.8 V. Also, assume a voltage drop of 400 mV across RS .

Solution

The power budget along with VDD = 1.8 V implies a maximum supply current of 2.78 mA. As an initial guess, we allocate 2.7 mA to M1 and the remaining 80 μA to R1 and R2 . It follows that RS = 148 . (7.83) As with typical design problems, the choice of gm and RD is somewhat flexible so long as gmRD = 5. However, with ID known, we must ensure a reasonable value for VGS , e.g., VGS = 1 V. This choice yields gm = =

2ID VGS − VTH

(7.84)

1 , 92.6

(7.85)

7.3 Common-Gate Stage

297

and hence RD = 463 .

(7.86)

Writing ID =

1 W μnCox (VGS − VTH )2 2 L

(7.87)

gives

With VGS that

W = 216. (7.88) L = 1 V and a 400-mV drop across RS , the gate voltage reaches 1.4 V, requiring R2 VDD = 1.4 V, R1 + R 2

(7.89)

which, along with Rin = R1 ||R2 = 50 k, yields R1 = 64.3 k

(7.90)

R2 = 225 k.

(7.91)

We must now check to verify that M1 indeed operates in saturation. The drain voltage is given by VDD − ID RD = 1.8 V − 1.25 V = 0.55 V. Since the gate voltage is equal to 1.4 V, the gate-drain voltage difference exceeds VTH , driving M1 into the triode region! How did our design procedure lead to this result? For the given ID , we have chosen an excessively large RD , i.e., an excessively small gm (because gmRD = 5), even though VGS is reasonable. We must therefore increase gm so as to allow a lower value for RD . For example, suppose we halve RD and double gm by increasing W/L by a factor of four: W = 864 (7.92) L 1 gm = . (7.93) 46.3 The corresponding gate-source voltage is obtained from (7.84): VGS = 250 mV,

(7.94)

yielding a gate voltage of 650 mV. Is M1 in saturation? The drain voltage is equal to VDD − RD ID = 1.17 V, a value higher than the gate voltage minus VTH . Thus, M1 operates in saturation. Exercise

7.3

Repeat the above example for a power budget of 3 mW and VDD = 1.2 V.

COMMON-GATE STAGE Shown in Fig. 7.21, the CG topology resembles the common-base stage studied in Chapter 5. Here, if the input rises by a small value, V, then the gate-source voltage of M1 decreases by the same amount, thereby lowering the drain current by gmV and

298

Chapter 7 CMOS Amplifiers VDD RD Vout V in

M1

Vb

Output Sensed at Drain

Input Applied to Source

Figure 7.21

Common-gate stage.

raising Vout by gmVRD . That is, the voltage gain is positive and equal to Av = gmRD .

(7.95)

The CG stage suffers from voltage headroom-gain trade-offs similar to those of the CB topology. In particular, to achieve a high gain, a high ID or RD is necessary, but the drain voltage, VDD − ID RD , must remain above Vb − VTH to ensure M1 is saturated.

Example 7.12

A microphone having a dc level of zero drives a CG stage biased at ID = 0.5 mA. If W/L = 50, μnCox = 100 μA/V2 , VTH = 0.5 V, and VDD = 1.8 V, determine the maximum allowable value of RD and hence the maximum voltage gain. Neglect channellength modulation.

Solution

With W/L known, the gate-source voltage can be determined from ID =

W 1 μnCox (VGS − VTH )2 2 L

(7.96)

as VGS = 0.947 V.

(7.97)

VDD − ID RD > Vb − VTH

(7.98)

RD < 2.71 k.

(7.99)

For M1 to remain in saturation,

and hence

Also, the above value of W/L and ID yield gm = (447 )−1 and Av ≤ 6.06.

(7.100)

Figure 7.22 summarizes the allowable signal levels in this design. The gate voltage can be generated using a resistive divider similar to that in Fig. 7.20(a). Exercise

If a gain of 10 is required, what value should be chosen for W/L?

7.3 Common-Gate Stage

299

VDD RD Vout

Vb – V TH = 0.447 V

Vb = 0.947 V

M1 V in

Figure 7.22

Signal levels in CG stage.

We now compute the I/O impedances of the CG stage, expecting to obtain results similar to those of the CB topology. Neglecting channel-length modulation for now, we have from Fig. 7.23(a) v1 = −vX and iX = −gmv1

(7.101)

= gmvX .

(7.102)

That is, Rin =

1 , gm

(7.103)

a relatively low value. Also, from Fig. 7.23(b), v1 = 0 and hence Rout = RD ,

(7.104)

an expected result because the circuits of Figs. 7.23(b) and 7.7 are identical. Let us study the behavior of the CG stage in the presence of a finite source impedance (Fig. 7.24) but still with λ = 0. In a manner similar to that depicted in Chapter 5 for the CB topology, we write

vX =

=

1 gm 1 + RS gm

vin

(7.105)

1 vin . 1 + gmRS

(7.106)

iX g v1

v1

vX

m

RD

m

iX

(a)

Figure 7.23

g v1

v1

(a) Input and (b) output impedances of CG stage.

(b)

RD

vX

300

Chapter 7 CMOS Amplifiers VDD RD Vout Vb

M1

RS

RS

X v in

Figure 7.24

1 gm

v in

1 gm

vX

Simplification of CG stage with signal source resistance.

Thus, vout vout vX = · vin vX vin

(7.107)

=

gmRD 1 + gmRS

=

RD . 1 + RS gm

(7.108)

(7.109)

The gain is therefore equal to that of the degenerated CS stage except for a negative sign. In contrast to the common-source stage, the CG amplifier exhibits a current gain of unity: the current provided by the input voltage source simply flows through the channel and emerges from the drain node. The analysis of the common-gate stage in the general case, i.e., including both channellength modulation and a finite source impedance, is beyond the scope of this book. However, we can make two observations. First, a resistance appearing in series with the gate terminal [Fig. 7.25(a)] does not alter the gain or I/O impedances (at low frequencies) because it sustains a zero potential drop—as if its value were zero. Second, the output resistance of the CG stage in the general case [Fig. 7.25(b)] is identical to that of the degenerated CS topology: Rout = (1 + gmrO )RS + rO .

(7.110)

VDD R out

RD Vout M1

RG

Vb

RS

rO M1

v in

(a)

Figure 7.25

(b)

(a) CG stage with gate resistance, (b) output resistance of CG stage.

7.3 Common-Gate Stage Example 7.13

301

For the circuit shown in Fig. 7.26(a), calculate the voltage gain if λ = 0 and the output impedance if λ > 0. VDD

R out1

RD Vout RS M 1 V in

Vb

RS

X M2

v in

(a)

Figure 7.26

1 g m1

RS

r O1 M1

vX 1 g m2

(b)

1 r g m2 O2 (c)

(a) Example of CG stage, (b) equivalent input network, (c) calculation of output

resistance. Solution

We first compute vX /vin with the aid of the equivalent circuit depicted in Fig. 7.26(b): 1 1 vX gm2 gm1 = (7.111) 1 1 vin + R S gm2 gm1 =

1 . 1 + (gm1 + gm2 )RS

(7.112)

Noting that vout /vX = gm1 RD , we have vout gm1 RD = . vin 1 + (gm1 + gm2 )RS

(7.113)

To compute the output impedance, we first consider Rout1 , as shown in Fig. 7.26(c), which from Eq. (7.110) is equal to 1 Rout1 = (1 + gm1rO1 ) ||rO2 ||RS + rO1 (7.114) gm2 1 ≈ gm1rO1 ||RS + rO1 . (7.115) gm2 The overall output impedance is then given by Rout = Rout1 ||RD 1 ≈ gm1rO1 ||RS + rO1 RD . gm2 Exercise

Calculate the output impedance if the gate of M2 is tied to a constant voltage.

(7.116) (7.117)

302

Chapter 7 CMOS Amplifiers 7.3.1 CG Stage With Biasing Following our study of the CB biasing in Chapter 5, we surmise the CG amplifier can be biased as shown in Fig. 7.27. Providing a path for the bias current to ground, resistor R3 lowers the input impedance—and hence the voltage gain—if the signal source exhibits a finite output impedance, RS .

VDD RD Vout

Figure 7.27

M1 X

RS

V in

C1

R1

R2 R3

CG stage with biasing.

Since the impedance seen to the right of node X is equal to R3 ||(1/gm), we have vX vout vout = · vin vin vX =

R3 ||(1/gm) · gmRD , R3 ||(1/gm) + RS

(7.118)

(7.119)

where channel-length modulation is neglected. As mentioned earlier, the voltage divider consisting of R1 and R2 does not affect the small-signal behavior of the circuit (at low frequencies).

Example 7.14

Design the common-gate stage of Fig. 7.27 for the following parameters: vout / vin = 5, RS = 0, R3 = 500 , 1/gm = 50 , power budget = 2 mW, VDD = 1.8 V. Assume μnCox = 100 μA/V2 , VTH = 0.5 V, and λ = 0.

Solution

From the power budget, we obtain a total supply current of 1.11 mA. Allocating 10 μA to the voltage divider, R1 and R2 , we leave 1.1 mA for the drain current of M1 . Thus, the voltage drop across R3 is equal to 550 mV. We must now compute two interrelated parameters: W/L and RD . A larger value of W/L yields a greater gm, allowing a lower value of RD . As in Example 7.11, we choose an initial value for VGS to arrive at a reasonable guess for W/L. For example, if VGS = 0.8 V, then W/L = 244, and gm = 2ID /(VGS − VTH ) = (136.4 )−1 , dictating RD = 682 for vout /vin = 5. Let us determine whether M1 operates in saturation. The gate voltage is equal to VGS plus the drop across R3 , amounting to 1.35 V. On the other hand, the drain voltage is given by VDD − ID RD = 1.05 V. Since the drain voltage exceeds VG − VTH , M1 is indeed in saturation.

7.4 Source Follower

303

The resistive divider consisting of R1 and R2 must establish a gate voltage equal to 1.35 V while drawing 10 μA: VDD = 10 μA (7.120) R1 + R 2 R2 VDD = 1.35 V. R1 + R 2

(7.121)

It follows that R1 = 45 k and R2 = 135 k. Exercise

If W/L cannot exceed 100, what voltage gain can be achieved?

Example 7.15

Suppose in Example 7.14, we wish to minimize W/L (and hence transistor capacitances). What is the minimum acceptable value of W/L?

Solution

For a given ID , as W/L decreases, VGS − VTH increases. Thus, we must first compute the maximum allowable VGS . We impose the condition for saturation as VDD − ID RD > VGS + VR3 − VTH ,

(7.122)

where VR3 denotes the voltage drop across R3 , and set gmRD to the required gain: 2ID RD = Av . VGS − VTH

(7.123)

Eliminating RD from Eqs. (7.122) and (7.123) gives: VDD −

Av (VGS − VTH ) > VGS − VTH + VR3 2

and hence VGS − VTH <

VDD − VR3 . Av +1 2

(7.124)

(7.125)

In other words, W/L >

2ID

μnCox

VDD − VR3 2 Av + 2

2 .

(7.126)

It follows that W/L > 172.5. Exercise

7.4

(7.127)

Repeat the above example for Av = 10.

SOURCE FOLLOWER The MOS counterpart of the emitter follower is called the “source follower” (or the “common-drain” stage) and shown in Fig. 7.28. The amplifier senses the input at the gate and produces the output at the source, with the drain tied to VDD . The circuit’s behavior is similar to that of the bipolar counterpart.

304

Chapter 7 CMOS Amplifiers VDD V in

M1 Vout

Input Applied to Gate

Figure 7.28

RL

Output Sensed at Source

Source follower.

7.4.1 Source Follower Core If the gate voltage of M1 in Fig. 7.28 is raised by a small amount, Vin , the gate-source voltage tends to increase, thereby raising the source current and hence the output voltage. Thus, Vout “follows” Vin . Since the dc level of Vout is lower than that of Vin by VGS , we say the follower can serve as a “level shift” circuit. From our analysis of emitter followers in Chapter 5, we expect this topology to exhibit a subunity gain, too. Figure 7.29(a) depicts the small-signal equivalent of the source follower, including channel-length modulation. Recognizing that rO appears in parallel with RL , we have gmv1 (rO ||RL ) = vout .

(7.128)

vin = v1 + vout .

(7.129)

gm(rO ||RL ) vout = vin 1 + gm(rO ||RL )

(7.130)

Also,

It follows that

=

rO ||RL . 1 + rO ||RL gm

(7.131)

The voltage gain is therefore positive and less than unity. It is desirable to maximize RL (and rO ). As with emitter followers, we can view the above result as voltage division between a resistance equal to 1/gm and another equal to rO ||RL [Fig. 7.29(b)]. Note, however, that a resistance placed in series with the gate does not affect Eq. (7.131) (at low frequencies) because it sustains a zero drop.

v in

g v1

v1

m

v out

1 gm

rO

v out v in

RL r O

RL (a)

Figure 7.29

(b)

(a) Small-signal equivalent of source follower, (b) simplified circuit.

7.4 Source Follower Example 7.16

305

A source follower is realized as shown in Fig. 7.30(a), where M2 serves as a current source. Calculate the voltage gain of the circuit.

VDD V in

V in

M1 Vout

Vb

Solution

Vout r O2

M2 (a)

Figure 7.30

r O1

M1

(b)

(a) Follower with ideal current source, (b) simplified circuit.

Since M2 simply presents an impedance of rO2 from the output node to ac ground [Fig. 7.30(b)], we substitute RL = rO2 in Eq. (7.131): Av =

rO1 ||rO2 1 + rO1 ||rO2 gm1

.

(7.132)

If rO1 ||rO2 1/gm1 , then Av ≈ 1. Exercise

Repeat the above example if a resistance of value RS is placed in series with the source of M2 .

Example 7.17

Design a source follower to drive a 50- load with a voltage gain of 0.5 and a power budget of 10 mW. Assume μnCox = 100 μA/V2 , VTH = 0.5 V, λ = 0, and VDD = 1.8 V.

Solution

With RL = 50 and rO = ∞ in Fig. 7.28, we have Av =

RL 1 + RL gm

(7.133)

and hence gm =

1 . 50

(7.134)

The power budget and supply voltage yield a maximum supply current of 5.56 mA. Using this value for ID in gm = 2μnCox (W/L)ID gives W/L = 360. Exercise

What voltage gain can be achieved if the power budget is raised to 15 mW?

(7.135)

306

Chapter 7 CMOS Amplifiers

rO

M1 RL

Figure 7.31

rO

M1

1 gm

R out

rO

RL

Output resistance of source follower.

It is instructive to compute the output impedance of the source follower.2 As illustrated in Fig. 7.31, Rout consists of the resistance seen looking up into the source in parallel with that seen looking down into RL . With λ = 0, the former is equal to (1/gm)||rO , yielding Rout =

≈

1 ||rO ||RL gm

(7.136)

1 ||RL . gm

(7.137)

In summary, the source follower exhibits a very high input impedance and a relatively low output impedance, thereby providing buffering capability. VDD V in

C1

RG M1

C2 Vout

RS

Figure 7.32

Source follower with input and output coupling capacitors.

7.4.2 Source Follower With Biasing The biasing of source followers is similar to that of emitter followers (Chapter 5). Figure 7.32 depicts an example where RG establishes a dc voltage equal to VDD at the gate of M1 (why?) and RS sets the drain bias current. Note that M1 operates in saturation because the gate and drain voltages are equal. Also, the input impedance of the circuit has dropped from infinity to RG . Let us compute the bias current of the circuit. With a zero voltage drop across RG , we have VGS + ID RS = VDD .

2

The input impedance is infinite at low frequencies.

(7.138)

7.4 Source Follower

307

Neglecting channel-length modulation, we write ID =

=

W 1 μnCox (VGS − VTH )2 2 L

(7.139)

1 W μnCox (VDD − ID RS − VTH )2 . 2 L

(7.140)

The resulting quadratic equation can be solved to obtain ID . Example 7.18

Design the source follower of Fig. 7.32 for a drain current of 1 mA and a voltage gain of 0.8. Assume μnCox = 100 μA/V2 , VTH = 0.5 V, λ = 0, VDD = 1.8 V, and RG = 50 k.

Solution

The unknowns in this problem are VGS , W/L, and RS . The following three equations can be formed: W 1 ID = μnCox (VGS − VTH )2 (7.141) 2 L ID RS + VGS = VDD Av =

RS 1 + RS gm

(7.142) .

(7.143)

If gm is written as 2ID /(VGS − VTH ), then Eqs. (7.142) and (7.143) do not contain W/L and can be solved to determine VGS and RS . With the aid of Eq. (7.142), we write Eq. (7.143) as Av =

RS VGS − VTH + RS 2ID

(7.144)

=

2ID RS VGS − VTH + 2ID RS

(7.145)

=

2ID RS . VDD − VTH + ID RS

(7.146)

VDD − VTH Av ID 2 − Av

(7.147)

Thus, RS =

= 867 .

(7.148)

VGS = VDD − ID RS

(7.149)

and

= VDD − (VDD − VTH ) = 0.933 V.

Av 2 − Av

(7.150) (7.151)

308

Chapter 7 CMOS Amplifiers It follows from Eq. (7.141) that W = 107. L

Exercise

(7.152)

What voltage gain can be achieved if W/L cannot exceed 50?

Equation (7.140) reveals that the bias current of the source follower varies with the supply voltage. To avoid this effect, integrated circuits bias the follower by means of a current source (Fig. 7.33). VDD V in

C1

VDD

RG M1

V in

C2

C1

RG M1

C2

Vout

Vout Vb

Figure 7.33

M2

Source follower with biasing.

PROBLEMS In the following problems, unless otherwise stated, assume μnCox = 200 μA/V2 , μ pCox = 100 μA/V2 , λ = 0, and VTH = 0.4 V for NMOS devices and −0.4 V for PMOS devices. 7.1. For the circuit shown in Fig. 7.34, determine the maximum value of R that will keep M1 in saturation. Assume λ = 0; W/L = 3 : 1.

25 kΩ

VDD = 1.8 V R

VDD = 1.8 V 500 Ω

R1

M1 R2

Figure 7.35

7.3. Consider the circuit shown in Fig. 7.36. Calculate the maximum transconductance that M1 can provide (without going into the triode region.) VDD = 1.8 V

Figure 7.34

7.2. We wish to design the circuit of Fig. 7.35 for a drain current of 1 mA. If W/L = 20/0.18, compute R1 and R2 such that the input impedance is at least 20 k.

10 k Ω

1 kΩ

M1 100 Ω

Figure 7.36

Problems 7.4. The circuit of Fig. 7.37 must be designed for a voltage drop of 200 mV across RS . (a) Calculate the minimum allowable value of W/L if M1 must remain in saturation. (b) What are the required values of R1 and R2 if the input impedance must be at least 30 k?

7.7. We wish to design the stage in Fig. 7.40 for a drain current of 0.5 mA. If W/L = 50/0.18, calculate the values of R1 and R2 such that these resistors carry a current equal to onetenth of ID1 . VDD = 1.8 V

500 Ω

2 kΩ

R1

VDD = 1.8 V R1

309

M1 R2

M1 R2

100 Ω

RS

Figure 7.37

7.5. Consider the circuit depicted in Fig. 7.38, where W/L = 20/0.18. Assuming the current flowing through R2 is one-tenth of ID1 , calculate the values of R1 and R2 so that ID1 = 0.5 mA.

Figure 7.40

*7.8. Due to a manufacturing error, a parasitic resistor, RP has appeared in the circuit of Fig. 7.41. We know that circuit samples free from this error exhibit VGS = VDS + 100 mV whereas defective samples exhibit VGS = VDS + 50 mV. Determine the values of W/L and RP . VDD = 1.8 V

VDD = 1.8 V

30 k Ω

500 Ω

R1

RP

2 kΩ

M1

M1 R2

Figure 7.41 200 Ω

RS

Figure 7.38

7.6. The self-biased stage of Fig. 7.39 must be designed for a drain current of 1 mA. If M1 is to provide a transconductance of 1/(100 ), calculate the required value of RD .

*7.9. Due to a manufacturing error, a parasitic resistor, RP has appeared in the circuit of Fig. 7.42. We know that circuit samples free from this error exhibit VGS = VDS whereas defective samples exhibit VGS = VDS + VTH . Determine the values of W/L and RP if the drain current is 1 mA without RP . VDD = 1.8 V

VDD = 1.8 V RG

RD

10 k Ω

M1

20 k Ω

RS

M1

Figure 7.39

1 kΩ

Figure 7.42

RP

200 Ω

310

Chapter 7 CMOS Amplifiers

7.10. In the circuit of Fig. 7.43, M1 and M2 have *7.14. A student mistakenly uses the circuit of lengths equal to 0.25 μm and λ = 0.1 V−1 . Fig. 7.47 as a current source. If W/L = 10/0.25, λ = 0.1 V−1 , VB1 = 0.2 V, and VX Determine W1 and W2 such that IX = 2IY = 1 mA. Assume VDS1 = VDS2 = has a dc level of 1.2 V, calculate the VB = 0.8 V. What is the output resistance impedance seen at the source of M1 . of each current source?

VB

IX

IY

M1

M2

V B1

Figure 7.47

Figure 7.43

7.11. The current source shown in Fig. 7.44 are to be designed for Ix = I y = 0.6 mA. If VB1 = 1.1 V, VB2 = 1.0 V, λ = 0.1V−1 and L1 = L2 = 0.25 μm, calculate W 1 and W 2 . Calculate output resistances of these current sources.

VB1

VX

M1

IX

IY

M1

M2

VB2

7.15. For the circuit shown in Fig. 7.48, (W/L)1 = 4/0.15, (W/L)2 = 10/0.2, λ1 = 0.1 V−1 and λ2 = 0.12 V−1 , determine the inversion point V in (=V B ) for VX = 0.8 V. VDD = 1.8 V M2 VB

IX

M1

VX

Figure 7.44 Figure 7.48

7.12. Consider the circuit shown in Fig. 7.45, where (W/L)1 = 10/0.18 and (W/L)2 = 30/0.18. If λ = 0.1 V−1 , calculate VB such that VX = 0.9 V. VDD = 1.8 V M2 VB

X M1

7.16. In the common-source stage of Fig. 7.49, W/L = 30/0.18 and λ = 0. (a) What gate voltage yields a drain current of 0.5 mA? (Verify that M1 operates in saturation.) (b) With such a drain bias current, calculate the voltage gain of the stage. VDD = 1.8 V

Figure 7.45

2 kΩ

RD

7.13. Verify Fig. 7.46 for a current source. If W/L = 8/0.2, λ = 0.1 V−1 , VB1 = 0.25 V, V X has dc level of 1.2 V. Calculate impedance of source of M1 .

Vout V in

M1

Figure 7.49

VB1

Figure 7.46

M1 VX

7.17. We wish to design the stage of Fig. 7.50 for a voltage gain of 5 with W/L ≤ 20/0.18. Determine the required value of RD if the power dissipation must not exceed 1 mW.

Problems

current of 0.5 mA. If λ1 = 0.15 V−1 and λ2 = 0.05 V−1 , determine the required value of (W/L)2 .

VDD = 1.8 V RD Vout V in

M1

7.21. Explain which one of the topologies shown in Fig. 7.54 is preferred.

Figure 7.50

VDD

7.18. The CS stage of Fig. 7.51 must provide a voltage gain of 10 with a bias current of 0.5 mA. Assume λ1 = 0.1 V−1 , and λ2 = 0.15 V−1 . (a) Compute the required value of (W/L)1 . (b) If (W/L)2 = 20/0.18, calculate the required value of VB .

311

Vb

VDD V in

M2

M2

Vout V in

Vout Vb

M1 (a)

M1 (b)

Figure 7.54

VDD = 1.8 V V in

M2 Vout

Vb

7.22. For the circuit of Fig. 7.55, find voltage gain (λ = 0).

M1

VDD ID

Figure 7.51

V in

M2 Vout

7.19. For the circuit shown in Fig. 7.52, calculate Rout for given data. ID = 1 mA(W/L)2 = 5/1 (W/L)1 = 10/1, λ2 = 0.1 V−1 , λ1 = 0.1V−1 . VDD M2 Vin

M1 Figure 7.55

7.23. The CS stage shown in Fig. 7.56 must achieve a gain of 7. If (W/L)2 = 2/0.18, compute required value of (W/L)1 .

M1

VDD = 1.8 V M2

Figure 7.52

Vout

7.20. The CS stage depicted in Fig. 7.53 must achieve a voltage gain of 15 at a bias VDD ID V in

M2 Vout M1

Figure 7.53

Vin

M1

Figure 7.56

**7.24. If λ = 0, determine the voltage gain of the stages shown in Fig. 7.57. 7.25. For the circuit shown in Fig.7.58, determine the gate voltage at which M1 operates at the edge of saturation.

312

Chapter 7 CMOS Amplifiers VDD

VDD Vb

M2

M2 V in

M1

Vout V in

M1

M1

(b)

V in

M2 Vout M1

M3

VDD

M2

M2 Vout

Vb

(d)

M1

RD Vout

M3 V in

(e)

M3

(c)

VDD

VDD

Vb

M2

Vout

(a)

V in

Vb

M3

Vout V in

VDD

M1 (f)

Figure 7.57

VDD = 1.8 V RD ID Vout

Vin

M 1 VDS

Figure 7.58

7.26. For the circuit shown in Fig. 7.59, find the value of RC , which should give gain of 5 with a bias current of 0.5 mA. Assume a drop of 250 mV across RS and λ = 0. (a) If RD = 2 k, determine the required value of (W/L). (b) If (W/L) = 40/0.18, determine the value of RD . VDD = 1.8 V RD Vout Vin

M1 RS

Figure 7.59

**7.27. Calculate the voltage gain of the circuits depicted in Fig. 7.60. Assume λ = 0. *7.28. Determine the output impedance of each circuit shown in Fig. 7.61. Assume λ = 0. 7.29. The circuit in Fig. 7.62 has bias current of 0.8 mA. If RD = 1.5 k, λ = 0.1 V−1 compute required value of W/L for gate voltage of 1 V. What is voltage gain of circuit? 7.30. For the circuit shown in Fig. 7.63, find output voltage and gain. 7.31. For Fig. 7.64 circuit, I 1 is ideal current source, I1 = 1.5 mA, RD = 350 , λ = 0, C, is very large. Compute (W/L) value to obtain gain of 7. 7.32. For a circuit in Fig. 7.65, for λ = 0, I1 = 2 mA, what is the maximum value of RD for M1 to be in saturation? 7.33. For the circuit shown in Fig. 7.66, find voltage transfer function. Determine value of V out /V in . Assume ID = 400 μA, λ = 0, in small-signal model take C gs = 0.5 PF and C gd = 0.1 PF. 7.34. Identify the poles and zeros for Problem 7.33.

Problems VDD M2

RD

M2 Vout

V in

VDD

VDD

Vout

RD V in

Vout

M1 V in

M3

Vb

M2

M1

M1

I1

M3 (b)

(a)

(c)

VDD

VDD Vb

RD Vout V in

V in

M1

M3

Vb

(d)

(e)

Figure 7.60

VDD

R out

R out V in

M1

Vb

I1

(a)

(b)

VDD

R out Vb

M2

M1

Vb

M2

M1 Vout

M2

V in

M2

V in

M2

M2

VDD = 1.8 V Vb

V in

M1

M3

M1

M3

R out

(c)

RD Vin

Vout

M1

(d)

Figure 7.62

Figure 7.61

RD ID

Vin VB

VDD = 1.8 V R1

M1 Vout

ID

Vin

RS Figure 7.63

RD

Figure 7.64

Vout

R2

I1

C1

313

314

Chapter 7 CMOS Amplifiers VDD R D 10 k Ω Vout

VDD = 1.8 V R1

RD VB

I1

Vin

C1

Figure 7.65

Figure 7.66

7.35. The CG stage depicted in Fig. 7.67 must provide an input impedance of 50 and an output impedance of 500 . Assume λ = 0. (a) What is the maximum allowable value of ID ? (b) With the value obtained in (a), calculate the required value of W/L. (c) Compute the voltage gain.

7.36. For the circuit shown in Fig. 7.68, find the voltage gain. Assume RI = 1 k, gm = 1 ms, C gs = 1 PF, RL = 20 k, C gd = 1PF. Ignore rds . RI = 1 k Ω

Vout

Vin

VDD = 1.8 V

R L = 20 k Ω

Figure 7.68

RD

*7.37. Determine the voltage gain of each stage depicted in Fig. 7.69. Assume λ = 0.

Vout V in

ID RS = 1 k Ω

M1

R2

Vin

10/1

VB

Vout

M1

Figure 7.67 VDD

VDD

M2 Vout V in

M2 Vout

RD

Vb

M1

Vout

RS

V in (a)

Vb

M1

M3

R1 (c)

VDD

Vb

M1

Vout V in

M1 (d)

M2 Vout

RD

Figure 7.69

RS

V in

M2

Vb

M1

V in

(b)

VDD Vb

VDD

M2

RD I1

Vb (e)

Problems 7.38. For circuit shown in Fig. 7.70, calculate output swing limits. VSGI

VDD

Vin

7.42. For a source follower shown in Fig. 7.74, with W/L = 360, RL = 50 power budget of 20 mW, find voltage gain (VDD = 2 V). VDD

M1 ID

I Vout

VGGI

315

W/L = 360/1

Vin

M2

Vout

50 Ω = RL Figure 7.70

Figure 7.74

7.39. Repeat Problem 7.38 for the circuit shown in Fig. 7.71. VDD R D2 V in

7.43. Design a source follower shown in Fig. 7.75 with drain current 2 mA, voltage gain 0.85. λ = 0, VDD = 1.8 V, R1 = 5 k, R2 = 220 k.

Vout

M1

VDD = 1.8 V

Vb

M2

R1

X

R D1

VB

Vin C1

C2

R2

Figure 7.71

7.40. Show that small-signal resistance of a gatedrain connected DMOS device (Fig. 7.72) behaves like a resistor of value 1/gm . VDD R

C VX

Figure 7.75

7.44. In Fig. 7.75, what changes do you suggest to make gate bias voltage max VDD = 1.8 V? What are its effects and what will be the design values? 7.45. Calculate voltage gain of circuit as shown in Fig. 7.76.

Figure 7.72

RD

7.41. For the circuit shown in Fig. 7.73, CS stage with degeneration (MOS connected load), find R0 using equivalent circuit diagram.

M1

M2

Figure 7.73

VDD Vout

Vin

Rout Vb

Vout

RS

M1

M2

VB

I1 Figure 7.76

7.46. For the current in Fig. 7.77 determine required (W/L) ratio, given o/p impedance less than 60 , power budget of 3 mW, and λ = 0.

316

Chapter 7 CMOS Amplifiers 7.49. Calculate voltage gain of current shown in Fig. 7.80. Given data RG = 40 k, ID = 5 mA, λ1 = λ2 = 0.001 V−1· (W/L)1 = 300/1.

VDD = 1.8 V Vin

M1

Vout I1

Design Problems In the following problems, unless otherwise stated, assume λ = 0.

Figure 7.77

7.47. For the circuit shown in Fig. 7.78, AV = 0.85, power budget 2 mN determine required (W/L) ratio. C is very large and λ = 0. VDD = 1.8 V Vin

M1

C Vout I1

RL 50 Ω

Figure 7.78

*7.48. Determine the voltage gain of the stages shown in Fig. 7.79. Assume λ = 0.

7.50. Design the CS stage shown in Fig. 7.81 for a voltage gain of 5 and an output impedance of 1 k. Bias the transistor so that it operates 100 mV away from the triode region. Assume the capacitors are very large and RD = 10 k. 7.51. The degenerated stage depicted in Fig. 7.82 must provide a voltage gain of 4 with a power budget of 2 mW while the voltage drop across RS is equal to 200 mV. If the overdrive voltage of the transistor must not exceed 300 mV and R1 + R2 must consume less than than 5% of the allocated power, design the circuit. Make the same assumptions as those in Problem 7.50.

VDD V in

VDD V in

M1

(b)

VDD M1 Vout

(c)

VDD Vb

M3

M1 Vout

M2

V in

M2

R2

Figure 7.79

M2

RS

(a)

(d)

Vout

M2

M2

R1

M1

Vout Vb

RS

V in

V in

M1

Vout

Vb

VDD

(e)

VDD V b2

M3

V b1

M2 Vout

V in

M1 (f)

Problems

317

VDD = 1.8 V 40 kΩ

RG

VDD = 1.8 V

M1

C1

C2

M2

VB

RG

Vout

C2 Vout

C1

V in

Figure 7.80

RD M1

Figure 7.81

VDD = 1.8 V C1

R1

RD

Vout

M1 V in

R2 RS

Figure 7.82

7.52. The circuit shown in Fig. 7.83 must provide a voltage gain of 6, with C S serving as a low impedance at the frequencies of interest. Assuming a power budget of 2 mW and an input impedance of 20 k, design the circuit such that M1 operates 200 mV away from the triode region. Select the values of C 1 and C S so that their impedance is negligible at 1 MHz. VDD = 1.8 V C1

R1

RD

Vout

M1 V in

RS

VDD = 1.8 V Vb

M2 Vout

V in

M1

Figure 7.84

7.54. Consider the circuit shown in Fig. 7.85, where CB is very large and λn = 0.5λ p = 0.1 V−1 . VDD = 1.8 V

CB

M2 RG

CS

Figure 7.83

V in

Vout M1

Figure 7.85

7.53. In the circuit of Fig. 7.84, M2 serves as a current source. Design the stage for a voltage gain of 20 and a power budget of 2 mW. Assume λ = 0.1 V−1 for both transistors and the maximum allowable level at the output is 1.5 V (i.e., M2 must remain in saturation if Vout ≤ 1.5 V).

(a) Calculate the voltage gain. (b) Design the circuit for a voltage gain of 15 and a power budget of 3 mW. Assume RG ≈ 10(rO1 ||rO2 ) and the dc level of the output must be equal to VDD /2.

318

Chapter 7 CMOS Amplifiers

7.55. The CS stage of Fig. 7.86 incorporates a degenerated PMOS current source. The degeneration must raise the output impedance of the current source to about 10rO1 such that the voltage gain remains nearly equal to the intrinsic gain of M1 . Assume λ = 0.1 V−1 for both transistors and a power budget of 2 mW. (a) If VB = 1 V, determine the values of (W/L)2 and RS so that the impedance seen looking into the drain of M2 is equal to 10rO1 . (b) Determine (W/L)1 to achieve a voltage gain of 30.

a voltage gain of 5. Assume a power budget of 3 mW. 7.58. Design the circuit of Fig. 7.89 such that M1 operates 100 mV away from the triode region while providing a voltage gain of 4. Assume a power budget of 2 mW. VDD = 1.8 V RD Vout M1

V in

RS

VDD = 1.8 V

Figure 7.89

RS Vb

M2 Vout

V in

M1

Figure 7.86

7.56. Assuming a power budget of 1 mW and an overdrive of 200 mV for M1 , design the circuit shown in Fig. 7.87 for a voltage gain of 4. VDD = 1.8 V

7.59. Figure 7.90 shows a self-biased commongate stage, where RG ≈ 10RD andCG serves as a low impedance so that the voltage gain is still given by gmRD . Design the circuit for a power budget of 5 mW and a voltage gain of 5. Assume RS ≈ 10/gm so that the input impedance remains approximately equal to 1/gm. VDD = 1.8 V RD V out

M2 Vout V in

V in

Figure 7.90

Figure 7.87

7.57. Design the common-gate stage depicted in Fig. 7.88 for an input impedance of 50 and

7.60. Design the CG stage shown in Fig. 7.91 such that it can accommodate an output

VDD = 1.8 V

VDD = 1.8 V

RD

V in

RD

V in

Figure 7.88

R2

V out

M1 I1

CG

RS

M1

Vout

RG

M1

M1 R1 RS

Figure 7.91

Spice Problems swing of 500 mVpp , i.e., Vout can fall below its bias value by 250 mV without driving M1 into the triode region. Assume a voltage gain of 4 and an input impedance of 50 . Select RS ≈ 10/gm and R1 + R2 = 20 k. (Hint: since M1 is biased 250 mV away from the triode region, we have RS ID + VGS − VTH + 250 mV = VDD − ID RD .) 7.61. Design the source follower depicted in Fig. 7.92 for a voltage gain of 0.8 and a power budget of 2 mW. Assume the output dc level is equal to VDD /2 and the input impedance exceeds 10 k.

319

7.62. Consider the source follower shown in Fig. 7.93. The circuit must provide a voltage gain of 0.6 at 100 MHz. Design the circuit such that the dc voltage at node X is equal to VDD /2. Assume the input impedance exceeds 20 k. VDD = 1.8 V RG V in

M1 X

C1 Vout

RS

50 Ω

RL

Figure 7.93 VDD = 1.8 V RG V in

M1 Vout RS

Figure 7.92

SPICE PROBLEMS In the following problems, use the MOS models and source/drain dimensions given in Appendix A. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD , respectively. 7.1. In the circuit of Fig. 7.94, I1 is an ideal current source equal to 1 mA. VDD = 1.8 V 10 k Ω

V in

1 kΩ

C1

I1 Vout

( W (1 M1

L

Figure 7.94

(a) Using hand calculations, determine (W/L)1 such that gm1 = (100 )−1 .

(b) Select C1 for an impedance of ≈ 100 ( 1 k) at 50 MHz. (c) Simulate the circuit and obtain the voltage gain and output impedance at 50 MHz. (d) What is the change in the gain if I1 varies by ±20%? 7.2. The source follower of Fig. 7.95 employs a bias current source, M2 . (a) What value of Vin places M2 at the edge of saturation? (b) What value of Vin places M1 at the edge of saturation? (c) Determine the voltage gain if Vin has a dc value of 1.5 V. (d) What is the change in the gain if Vb changes by ±50 mV?

320

Chapter 7 CMOS Amplifiers M1 V in

VDD = 1.8 V 20 0.18

Vout M2 0.8 V

10 0.18

(b) Verify that the gain drops if the dc value of Vin is higher or lower than 1.2 V. (c) What dc value at the input reduces the gain by 10% with respect to that obtained in (a)? VDD

Figure 7.95

7.3. Figure 7.96 depicts a cascade of a source follower and a common-gate stage. Assume Vb = 1.2 V and (W/L)1 = (W/L)2 = 10 μm/0.18 μm. (a) Determine the voltage gain if Vin has a dc value of 1.2 V.

1 kΩ

Vout V in

M1

M2 1 mA

Figure 7.96

Vb

Chapter

8

Operational Amplifier as a Black Box

The term “operational amplifier” (op amp) was coined in the 1940s, well before the invention of the transistor and the integrated circuit. Op amps realized by vacuum tubes1 served as the core of electronic “integrators,” “differentiators,” etc., thus forming systems whose behavior followed a given differential equation. Called “analog computers,” such circuits were used to study the stability of differential equations that arose in fields such as control or power systems. Since each op amp implemented a mathematical operation (e.g., integration), the term “operational amplifier” was born. Op amps find wide application in today’s discrete and integrated electronics. In the cellphone studied in Chapter 1, for example, integrated op amps serve as building blocks in (active) filters. Similarly, the analog-to-digital converter(s) used in digital cameras often employ op amps. In this chapter, we study the operational amplifier as a black box, developing opamp-based circuits that perform interesting and useful functions. The outline is shown below.

General Concepts • Op Amp Properties

➤

Linear Op Amp Circuits • Noninverting Amplifier

➤

Nonlinear Op Amp Circuits • Precision Rectifier

• Inverting Amplifier

• Logarithmic Amplifier

• Integrator and Differentiator

• Square Root Circuit

• Voltage Adder

➤

Op Amp Nonidealities • DC Offsets • Input Bias Currents • Speed Limitations • Finite Input and Output Impedances

1 Vacuum tubes were amplifying devices consisting of a filament that released electrons, a plate that collected them, and another that controlled the flow—somewhat similar to MOSFETs.

321

322

Chapter 8 Operational Amplifier as a Black Box V in1 V in2

Vout V in1

Vout

A 0 (V in1 – V in2 ) V in2

(a)

Figure 8.1

8.1

(b)

(a) Op amp symbol, (b) equivalent circuit.

GENERAL CONSIDERATIONS The operational amplifier can be abstracted as a black box having two inputs and one output.2 Shown in Fig. 8.1(a), the op amp symbol distinguishes between the two inputs by the plus and minus sign; Vin1 and Vin2 are called the “noninverting” and “inverting” inputs, respectively. We view the op amp as a circuit that amplifies the difference between the two inputs, arriving at the equivalent circuit depicted in Fig. 8.1(b). The voltage gain is denoted by A0 : Vout = A0 (Vin1 − Vin2 ).

(8.1)

we call A0 the “open-loop” gain. It is instructive to plot Vout as a function of one input while the other remains at zero. With Vin2 = 0, we have Vout = A0 Vin1 , obtaining the behavior shown in Fig. 8.2(a). The positive slope (gain) is consistent with the label “noninverting” given to Vin1 . On the other hand, if Vin1 = 0, Vout = −A0 Vin2 [Fig. 8.2(b)], revealing a negative slope and hence an “inverting” behavior. The reader may wonder why the op amp has two inputs. After all, the amplifier stages studied in Chapters 5 and 7 have only one input node (i.e., they sense the input voltage with respect to ground). As seen throughout this chapter, the principal property of the op amp, Vout = A0 (Vin1 − Vin2 ), forms the foundation for many circuit topologies that would be difficult to realize using an amplifier having Vout = AVin . Amplifier circuits having two inputs are studied in Chapter 10. Vout V in1

Vout

Vout A0 V in1

(a)

Figure 8.2

V in2

Vout

–A 0

V in2 (b)

Op amp characteristics from (a) noninverting and (b) inverting inputs to output.

How does the “ideal” op amp behave? Such an op amp would provide an infinite voltage gain, an infinite input impedance, a zero output impedance, and infinite speed. In fact, the first-order analysis of an op-amp-based circuit typically begins with this idealization, quickly revealing the basic function of the circuit. We can then consider the effect of the op amp “nonidealities” on the performance. 2 In modern integrated circuits, op amps typically have two outputs that vary by equal and opposite amounts.

8.1 General Considerations

323

The very high gain of the op amp leads to an important observation. Since realistic circuits produce finite output swings, e.g., 2 V, the difference between Vin1 and Vin2 in Fig. 8.1(a) is always small: Vin1 − Vin2 =

Vout . A0

(8.2)

In other words, the op amp, along with the circuitry around it, brings Vin1 and Vin2 close to each other. Following the above idealization, we may say Vin1 = Vin2 if A0 = ∞. A common mistake is to interpret Vin1 = Vin2 as if the two terminals Vin1 and Vin2 are shorted together. It must be borne in mind that Vin1 − Vin2 becomes only infinitesimally small as A0 → ∞ but cannot be assumed exactly equal to zero.

Example 8.1

The circuit shown in Fig. 8.3 is called a “unity-gain” buffer. Note that the output is tied to the inverting input. Determine the output voltage if Vin1 = +1 V and A0 = 1000.

A 0 = 1000 +1V

V in

Figure 8.3

Solution

Vout

Unity-gain buffer.

If the voltage gain of the op amp were infinite, the difference between the two inputs would be zero and Vout = Vin ; hence the term “unity-gain buffer.” For a finite gain, we write Vout = A0 (Vin1 − Vin2 )

(8.3)

= A0 (Vin − Vout ).

(8.4)

That is, Vout A0 = . Vin 1 + A0

(8.5)

As expected, the gain approaches unity as A0 becomes large. In this example, A0 = 1000, Vin = 1 V, and Vout = 0.999 V. Indeed, Vin1 − Vin2 is small compared to Vin and Vout . Exercise

What value of A0 is necessary so that the output voltage is equal to 0.9999?

Op amps are sometimes represented as shown in Fig. 8.4 to indicate explicitly the supply voltages, VEE and VCC . For example, an op amp may operate between ground and a positive supply, in which case VEE = 0.

324

Chapter 8 Operational Amplifier as a Black Box VCC V in1 V in2 Vout

VEE

Figure 8.4

8.2

Op amp with supply rails.

OP-AMP-BASED CIRCUITS In this section, we study a number of circuits that utilize op amps to process analog signals. In each case, we first assume an ideal op amp to understand the underlying principles and subsequently examine the effect of the finite gain on the performance. 8.2.1 Noninverting Amplifier Recall from Chapters 5 and 7 that the voltage gain of amplifiers typically depends on the load resistor and other parameters that may vary considerably with temperature or process.3 As a result, the voltage gain itself may suffer from a variation of, say, ±20%. However, in some applications (e.g., A/D converters), a much more precise gain (e.g., 2.000) is required. Op-amp-based circuits can provide such precision. V in1 A0 V in

V in2

Vout R1 R2

Figure 8.5

Noninverting amplifier.

Illustrated in Fig. 8.5, the noninverting amplifier consists of an op amp and a voltage divider that returns a fraction of the output voltage to the inverting input: Vin2 =

R2 Vout . R1 + R 2

(8.6)

Since a high op amp gain translates to a small difference between Vin1 and Vin2 , we have Vin1 ≈ Vin2 R2 ≈ Vout ; R1 + R 2

(8.7) (8.8)

and hence R1 Vout ≈1+ . Vin R2

(8.9)

3 Variation with process means that circuits fabricated in different “batches” exhibit somewhat different characteristics.

8.2 Op-Amp-Based Circuits

325

Due to the positive gain, the circuit is called a “noninverting amplifier.” We call this result the “closed-loop” gain of the circuit. Interestingly, the voltage gain depends on only the ratio of the resistors; if R1 and R2 increase by 20%, R1 /R2 remains constant. The idea of creating dependence on only the ratio of quantities that have the same dimension plays a central role in circuit design. Example 8.2

Study the noninverting amplifier for two extreme cases: R1 /R2 = ∞ and R1 /R2 = 0.

Solution

If R1 /R2 → ∞, e.g., if R2 approaches zero, we note that Vout /Vin → ∞. Of course, as depicted in Fig. 8.6(a), this occurs because the circuit reduces to the op amp itself, with no fraction of the output fed back to the input. Resistor R1 simply loads the output node, with no effect on the gain if the op amp is ideal. If R1 /R2 → 0, e.g., if R2 approaches infinity, we have Vout /Vin → 1. Shown in Fig. 8.6(b), this case in fact reduces to the unity-gain buffer of Fig. 8.3 because the ideal op amp draws no current at its inputs, yielding a zero drop across R1 and hence Vin2 = Vout . Vout

V in

R1

Vout

V in

R1

R2 = 0

R2 =

(a)

Figure 8.6 Exercise

(b)

Noninverting amplifier with (a) zero and (b) infinite value for R2 .

Suppose the circuit is designed for a nominal gain of 2.00 but the R1 and R2 suffer from a mismatch of 5% (i.e., R1 = (1 ± 0.05)R2 ). What is the actual voltage gain?

Let us now take into account the finite gain of the op amp. Based on the model shown in Fig. 8.1(b), we write (Vin1 − Vin2 )A0 = Vout ,

(8.10)

and substitute for Vin2 from Eq. (8.6): Vout = Vin

A0 . R2 1+ A0 R1 + R 2

(8.11)

As expected, this result reduces to Eq. (8.9) if A0 R2 /(R1 + R2 ) 1. To avoid confusion between the gain of the op amp, A0 , and the gain of the overall amplifier, Vout /Vin , we call the former the “open-loop” gain and the latter the “closed-loop” gain.

326

Chapter 8 Operational Amplifier as a Black Box Equation (8.11) indicates that the finite gain of the op amp creates a small error in the value of Vout /Vin . If much greater than unity, the term A0 R2 /(R1 + R2 ) can be factored from the denominator to permit the approximation (1 + )−1 ≈ 1 − for 1: R1 1 R1 Vout 1− 1+ . (8.12) ≈ 1+ Vin R2 R2 A0 Called the “gain error,” the term (1 + R1 /R2 )/A0 must be minimized according to each application’s requirements.

Example 8.3

A noninverting amplifier incorporates an op amp having a gain of 1000. Determine the gain error if the circuit is to provide a nominal gain of (a) 5, or (b) 50.

Solution

For a nominal gain of 5, we have 1 + R1 /R2 = 5, obtaining a gain error of: R1 1 1+ = 0.5%. R2 A0 On the other hand, if 1 + R1 /R2 = 50, then R1 1 1+ = 5%. R2 A0

(8.13)

(8.14)

In other words, a higher closed-loop gain inevitably suffers from less accuracy. Exercise

Repeat the above example if the op amp has a gain of 500.

With an ideal op amp, the noninverting amplifier exhibits an infinite input impedance and a zero output impedance. For a nonideal op amp, the I/O impedances are derived in Problem 8.5. 8.2.2 Inverting Amplifier Depicted in Fig. 8.7(a), the “inverting amplifier” incorporates an op amp along with resistors R1 and R2 while the noninverting input is grounded. Recall from Section 8.1 that if the op amp gain is infinite, then a finite output swing translates to Vin1 − Vin2 → 0; i.e., node X bears a zero potential even though it is not shorted to ground. For this reason, node X is called a “virtual ground.” Under this condition, the entire input voltage appears across R2 , producing a current of Vin /R2 , which must then flow through R1 if the op amp input draws no current [Fig. 8.7(b)]. Since the left terminal of R1 remains at zero and the right terminal at Vout , Vin 0 − Vout = R1 R2

(8.15)

−R1 Vout = . Vin R2

(8.16)

yielding

8.2 Op-Amp-Based Circuits V in R2

R1 R2 X

327

R1

R2 X Vout

V in

Vout

V in Virtual Ground (b)

(a)

R2

A

B

R1 (c)

Figure 8.7

(a) Inverting amplifier, (b) currents flowing in resistors, (c) analogy with a seesaw.

Due to the negative gain, the circuit is called the “inverting amplifier.” As with its noninverting counterpart, the gain of this circuit is given by the ratio of the two resistors, thereby experiencing only small variations with temperature and process. It is important to understand the role of the virtual ground in this circuit. If the inverting input of the op amp were not near zero potential, then neither Vin /R2 nor Vout /R1 would accurately represent the currents flowing through R2 and R1 , respectively. This behavior is similar to a seesaw [Fig. 8.7(c)], where the point between the two arms is “pinned” (e.g., does not move), allowing displacement of point A to be “amplified” (and “inverted”) at point B. The above development also reveals why the virtual ground cannot be shorted to the actual ground. Such a short in Fig. 8.7(b) would force to ground all of the current flowing through R2 , yielding Vout = 0. It is interesting to note that the inverting amplifier can also be drawn as shown in Fig. 8.8, displaying a similarity with the noninverting circuit but with the input applied at a different point. In contrast to the noninverting amplifier, the topology of Fig. 8.7(a) exhibits an input impedance equal to R2 —as can be seen from the input current, Vin /R2 , in Fig. 8.7(b). That is, a lower R2 results in a greater gain but a smaller input impedance. This trade-off sometimes makes this amplifier less attractive than its noninverting counterpart.

Vout

R2 V in

Figure 8.8

Inverting amplifier.

R1

328

Chapter 8 Operational Amplifier as a Black Box Let us now compute the closed-loop gain of the inverting amplifier with a finite op amp gain. We note from Fig. 8.7(a) that the currents flowing through R2 and R1 are given by (Vin − VX )/R2 and (VX − Vout )/R1 , respectively. Moreover, Vout = A0 (Vin1 − Vin2 )

(8.17)

= −A0 VX .

(8.18)

Equating the currents through R2 and R1 and substituting −Vout /A0 for VX , we obtain Vout 1 =− 1 R2 1 Vin + +1 A0 R1 A 0 =−

R2 1 + R1 A0

1 1+

R2 R1

.

(8.19)

(8.20)

Factoring R2 /R1 from the denominator and assuming (1 + R1 /R2 )/A0 1, we have Vout 1 R1 R1 1− 1+ . (8.21) ≈− Vin R2 A0 R2 As expected, a higher closed-loop gain (≈ −R1 /R2 ) is accompanied with a greater gain error. Note that the gain error expression is the same for noninverting and inverting amplifiers. Example 8.4

Design the inverting amplifier of Fig. 8.7(a) for a nominal gain of 4, a gain error of 0.1%, and an input impedance of at least 10 k.

Solution

Since both the nominal gain and the gain error are given, we must first determine the minimum op amp gain. We have R1 =4 R2 1 R1 1+ = 0.1%. A0 R2

(8.22) (8.23)

Thus, A0 = 5000.

(8.24)

Since the input impedance is approximately equal to R2 , we choose:

Exercise

R2 = 10 k

(8.25)

R1 = 40 k.

(8.26)

Repeat the above example for a gain error of 1% and compare the results.

In the above example, we assumed the input impedance is approximately equal to R2 . How accurate is this assumption? With A0 = 5000, the virtual ground experiences a voltage of −Vout /5000 ≈ −4Vin /5000, yielding an input current of (Vin + 4Vin /5000)/R1 .

8.2 Op-Amp-Based Circuits

329

Z1 Z2 Vout

V in

Figure 8.9

Circuit with general impedances around the op amp.

That is, our assumption leads to an error of about 0.08%—an acceptable value in most applications. 8.2.3 Integrator and Differentiator Our study of the inverting topology in previous sections has assumed a resistive network around the op amp. In general, it is possible to employ complex impedances instead (Fig. 8.9). In analogy with Eq. (8.16), we can write Vout Z1 ≈− , Vin Z2

(8.27)

where the gain of the op amp is assumed large. If Z1 or Z2 is a capacitor, two interesting functions result. Integrator Suppose in Fig. 8.9, Z1 is a capacitor and Z2 a resistor (Fig. 8.10). That is, Z1 = (C 1 s)−1 and Z2 = R1 . With an ideal op amp, we have 1 Vout C 1s =− Vin R1 1 =− . R1C 1 s

(8.28) (8.29)

Providing a pole at the origin,4 the circuit operates as an integrator (and a low-pass filter). Figure 8.11 plots the magnitude of Vout /Vin as a function of frequency. This can also be seen in the time domain. Equating the currents flowing through R1 and C 1 gives Vin dVout = −C 1 R1 dt and hence Vout = −

1 R1C 1

(8.30)

Vin dt. C1

R1 X V in

Figure 8.10 4

Vout

Integrator.

Pole frequencies are obtained by setting the denominator of the transfer function to zero.

(8.31)

330

Chapter 8 Operational Amplifier as a Black Box Vout Vin

f

Figure 8.11

Frequency response of integrator.

Equation (8.29) indicates that Vout /Vin approaches infinity as the input frequency goes to zero. This is to be expected: the capacitor impedance becomes very large at low frequencies, approaching an open circuit and reducing the circuit to the open-loop op amp. As mentioned at the beginning of the chapter, integrators originally appeared in analog computers to simulate differential equations. Today, electronic integrators find usage in analog filters, control systems, and many other applications. Example 8.5

Plot the output waveform of the circuit shown in Fig. 8.12(a). Assume a zero initial condition across C1 and an ideal op amp. V1

V in 0

C1 V1 0

V in Tb

Tb

V1 R1

I C1

R1 X Vout

V1 R1

Vout –

V1 R 1C1

0 (a)

Figure 8.12

Solution

–

V1 T b R 1C1 t

(b)

(a) Integrator with pulse input, (b) input and output waveforms.

When the input jumps from 0 to V1 , a constant current equal to V1 /R1 begins to flow through the resistor and hence the capacitor, forcing the right plate voltage of C1 to fall linearly with time while its left plate is pinned at zero [Fig. 8.12(b)]: 1 Vout = − Vin dt (8.32) R1C1 =−

V1 t R1C1

0 < t < Tb .

(8.33)

(Note that the output waveform becomes “sharper” as R1C1 decreases.) When Vin returns to zero, so do the currents through R1 and C1 . Thus, the voltage across the capacitor and hence Vout remain equal to −V1 Tb/(R1C1 ) (proportional to the area under the input pulse) thereafter. Exercise

Repeat the previous example if V1 is negative.

8.2 Op-Amp-Based Circuits

331

The previous example demonstrates the role of the virtual ground in the integrator. The ideal integration expressed by Eq. (8.32) occurs because the left plate of C1 is pinned at zero. To gain more insight, let us compare the integrator with a first-order RC filter in terms of their step response. As illustrated in Fig. 8.13, the integrator forces a constant current (equal to V1 /R1 ) through the capacitor. On the other hand, the RC filter creates a current equal to (Vin − Vout )/R1 , which decreases as Vout rises, leading to an increasingly slower voltage variation across C1 . We may therefore consider the RC filter as a “passive” approximation of the integrator. In fact, for a large R1C1 product, the exponential response of Fig. 8.13(b) becomes slow enough to be approximated as a ramp. C1 V1 0

V in

V1

R1 X Vout

V1 R1

Figure 8.13

R1

V in

V 1 – V out R1

Vout C1

Comparison of integrator with and RC circuit.

We now examine the performance of the integrator for A0 < ∞. Denoting the potential of the virtual ground node in Fig. 8.10 with VX , we have Vin − VX VX − Vout = 1 R1 C1 s

(8.34)

and VX =

Vout . −A0

(8.35)

Thus, Vout −1 = , 1 1 Vin R1C1 s + 1+ A0 A0

(8.36)

revealing that the gain at s = 0 is limited to A0 (rather than infinity) and the pole frequency has moved from zero to −1 sp = . (8.37) (A0 + 1)R1C1 Such a circuit is sometimes called a “lossy” integrator to emphasize the nonideal gain and pole position. Example 8.6

Recall from basic circuit theory that the RC filter shown in Fig. 8.14 contains a pole at −1/(RXCX ). Determine RX and CX such that this circuit exhibits the same pole as that of the above integrator. V in

RX

Vout CX

Figure 8.14

Simple low-pass filter.

332

Chapter 8 Operational Amplifier as a Black Box

Solution

From Eq. (8.37), RXCX = (A0 + 1)R1C1 .

(8.38)

The choice of RX and CX is arbitrary so long as their product satisfies Eq. (8.38). An interesting choice is RX = R1

(8.39)

CX = (A0 + 1)C1 .

(8.40)

It is as if the op amp “boosts” the value of C1 by a factor of A0 + 1. Exercise

What value of RX is necessary if CX = C1 ?

Differentiator If in the general topology of Fig. 8.9, Z1 is a resistor and Z2 a capacitor (Fig. 8.15), we have Vout R1 =− 1 Vin C1 s

(8.41)

= −R1C1 s.

(8.42)

R1 C1

X Vout

V in

Figure 8.15

Differentiator.

Exhibiting a zero at the origin, the circuit acts as a differentiator (and a high-pass filter). Figure 8.16 plots the magnitude of Vout /Vin as a function of frequency. From a time-domain perspective, we can equate the currents flowing through C1 and R1 : C1

dVin Vout =− , dt R1

(8.43)

arriving at Vout = −R1C1

dVin . dt

Vout Vin R 1 C1 f

Figure 8.16

Frequency response of differentiator.

(8.44)

8.2 Op-Amp-Based Circuits Example 8.7

333

Plot the output waveform of the circuit shown in Fig. 8.17(a) assuming an ideal op amp. V1

V in 0

Tb

I C1 R1 V1 0

V in Tb

C1

X Vout

I in

Vout 0

0 (a)

Figure 8.17 Solution

t (b)

(a) Differentiator with pulse input, (b) input and output waveforms.

At t = 0− , Vin = 0 and Vout = 0 (why?). When Vin jumps to V1 , an impulse of current flows through C1 because the op amp maintains VX constant: Iin = C1

dVin dt

= C1 V1 δ(t).

(8.45) (8.46)

The current flows through R1 , generating an output given by Vout = −Iin R1 = −R1C1 V1 δ(t).

(8.47) (8.48)

Figure 8.17(b) depicts the result. At t = Tb, Vin returns to zero, again creating an impulse of current in C1 : Iin = C1

dVin dt

= C1 V1 δ(t).

(8.49) (8.50)

It follows that Vout = −Iin R1 = R1C1 V1 δ(t).

(8.51) (8.52)

We can therefore say that the circuit generates an impulse of current [± C1 V1 δ(t)] and “amplifies” it by R1 to produce Vout . In reality, of course, the output exhibits neither an infinite height (limited by the supply voltage) nor a zero width (limited by the op amp nonidealities). Exercise

Plot the output if V1 is negative. It is instructive to compare the operation of the differentiator with that of its “passive” counterpart (Fig. 8.18). In the ideal differentiator, the virtual ground node permits the input

334

Chapter 8 Operational Amplifier as a Black Box R1 V1 0

V in

C1

V1

X Vout

I in

V in

V1

X

Vout R1

(a)

Figure 8.18

C1

(b)

Comparison of differentiator and RC circuit.

to change the voltage acrossC1 instantaneously. In the RC filter, on the other hand, node X is not “pinned,” thereby following the input change at t = 0 and limiting the initial current in the circuit to V1 /R1 . If the decay time constant, R1C1 , is sufficiently small, the passive circuit can be viewed as an approximation of the ideal differentiator. Let us now study the differentiator with a finite op amp gain. Equating the capacitor and resistor currents in Fig. 8.15 gives VX − Vout Vin − VX = . 1 R1 C1 s

(8.53)

Substituting −Vout /A0 for VX , we have Vout = Vin

−R1C1 s . 1 R1C1 s 1+ + A0 A0

(8.54)

In contrast to the ideal differentiator, the circuit contains a pole at sp = −

Example 8.8

A0 + 1 . R1C1

(8.55)

Determine the transfer function of the high-pass filter shown in Fig. 8.19 and choose RX and CX such that the pole of this circuit coincides with Eq. (8.55). V in

CX

Vout RX

Figure 8.19 Solution

Simple high-pass filter.

The capacitor and resistor operate as a voltage divider: Vout = Vin =

RX RX +

1 CX s

RXCX s . RXCX s + 1

(8.56)

(8.57)

8.2 Op-Amp-Based Circuits

335

The circuit therefore exhibits a zero at the origin (s = 0) and a pole at −1/(RXCX ). For this pole to be equal to Eq. (8.55), we require 1 A0 + 1 = . RXCX R1C1

(8.58)

One choice of RX and CX is RX =

R1 A0 + 1

(8.59)

CX = C1 , Exercise

(8.60)

What is the necessary value of CX if RX = R1 ?

An important drawback of differentiators stems from the amplification of highfrequency noise. As suggested by Eq. (8.42) and Fig. 8.16, the increasingly larger gain of the circuit at high frequencies tends to boost noise in the circuit. The general topology of Fig. 8.9 and its integrator and differentiator descendants operate as inverting circuits. The reader may wonder if it is possible to employ a configuration similar to the noninverting amplifier of Fig. 8.5 to avoid the sign reversal. Shown in Fig. 8.20, such a circuit provides the following transfer function: Z1 Vout =1+ , Vin Z2

(8.61)

if the op amp is ideal. Unfortunately, this function does not translate to ideal integration or differentiation. For example, Z1 = R1 and Z2 = 1/(C 2 s) yield a nonideal differentiator (why?). 8.2.4 Voltage Adder The need for adding voltages arises in many applications. In audio recording, for example, a number of microphones may convert the sounds of various musical instruments to voltages, and these voltages must then be added to create the overall musical piece. This operation is called “mixing” in the audio industry.5 For example, in “noise cancelling” headphones, the environmental noise is applied to an inverting amplifier and subsequently added to the signal so as to cancel itself. Vout

V in Z2

Figure 8.20

5

Z1

Op amp with general network.

The term “mixing” bears a completely different meaning in the RF and wireless industry.

336

Chapter 8 Operational Amplifier as a Black Box RF R1

V1 V2

Figure 8.21

X Vout

R2

Voltage adder.

Figure 8.21 depicts a voltage adder (“summer”) incorporating an op amp. With an ideal op amp, VX = 0, and R1 and R2 carry currents proportional to V1 and V2 , respectively. The two currents add at the virtual ground node and flow through RF : V1 V2 −Vout + = . R1 R2 RF

(8.62)

That is, Vout = −RF

V1 V2 . + R1 R2

(8.63)

For example, if R1 = R2 = R, then Vout =

−RF (V1 + V2 ). R

(8.64)

This circuit can therefore add and amplify voltages. Extension to more than two voltages is straightforward. Equation (8.63) indicates that V1 and V2 can be added with different weightings: RF /R1 and RF /R2 , respectively. This property also proves useful in many applications. For example, in audio recording it may be necessary to lower the “volume” of one musical instrument for part of the piece, a task possible by varying R1 and R2 .

8.3

NONLINEAR FUNCTIONS It is possible to implement useful nonlinear functions through the use of op amps and nonlinear devices such as transistors. The virtual ground property plays an essential role here as well. 8.3.1 Precision Rectifier The rectifier circuits described in Chapter 3 suffer from a “dead zone” due to the finite voltage required to turn on the diodes. That is, if the input signal amplitude is less than approximately 0.7 V, the diodes remain off and the output voltage remains at zero. This drawback prohibits the use of the circuit in high-precision applications, e.g., if a small signal received by a cellphone must be rectified to determine its amplitude. It is possible to place a diode around an op amp to form a “precision rectifier,” i.e., a circuit that rectifies even very small signals. Let us begin with a unity-gain buffer tied to a resistive load [Fig. 8.22(a)]. We note that the high gain of the op amp ensures that node X tracks Vin (for both positive and negative cycles). Now suppose we wish to hold X at

8.3 Nonlinear Functions

337

V in V in X

t

V in

Vout

Y

X V out

R1

R1

VY

D1

V D,on t

V out t (a)

Figure 8.22

(b)

(c)

(a) Simple op amp circuit, (b) precision rectifier, (c) circuit waveforms.

zero during negative cycles, i.e., “break” the connection between the output of the op amp and its inverting input. This can be accomplished as depicted in Fig. 8.22(b), where D1 is inserted in the feedback loop. Note that Vout is sensed at X rather than at the output of the op amp. To analyze the operation of this circuit, let us first assume that Vin = 0. In its attempt to minimize the voltage difference between the noninverting and the inverting inputs, the op amp raises VY to approximately VD1,on , turning D1 barely on but with little current so that VX ≈ 0. Now if Vin becomes slightly positive, VY rises further so that the current flowing through D1 and R1 yields Vout ≈ Vin . That is, even small positive levels at the input appear at the output. What happens if Vin becomes slightly negative? For Vout to assume a negative value, D1 must carry a current from X to Y, which is not possible. Thus, D1 turns off and the op amp produces a very large negative output (near the negative supply rail) because its noninverting input falls below its inverting input. Figure 8.22(c) plots the circuit’s waveforms in response to an input sinusoid.

Example 8.9

Plot the waveforms in the circuit of Fig. 8.23(a) in response to an input sinusoid.

V in t

D1 VX

R1 X

t

Y V in VY

t

– V D,on (a)

Figure 8.23

(a) Inverting precision rectifier, (b) circuit waveforms.

(b)

338

Chapter 8 Operational Amplifier as a Black Box

Solution

For Vin = 0, the op amp creates VY ≈ −VD,on so that D1 is barely on, R1 carries little current, and X is a virtual ground. As Vin becomes positive, thus raising the current through R1 , VY only slightly decreases to allow D1 to carry the higher current. That is, VX ≈ 0 and VY ≈ −VD,on for positive input cycles. For Vin < 0, D1 turns off (why?), leading to VX = Vin and driving VY to a very positive value. Figure 8.23(b) shows the resulting waveforms.

Exercise

Repeat the above example for a triangular input that goes from −2 V to +2 V.

The large swings at the output of the op amp in Figs. 8.22(b) and 8.23(a) lower the speed of the circuit as the op amp must “recover” from a saturated value before it can turn D1 on again. Additional techniques can resolve this issue (Problem 8.33). 8.3.2 Logarithmic Amplifier Consider the circuit of Fig. 8.24, where a bipolar transistor is placed around the op amp. With an ideal op amp, R1 carries a current equal to Vin /R1 and so does Q 1 . Thus, VBE = VT ln

Vin /R1 . IS

(8.65)

Vin . R1 IS

(8.66)

Also, Vout = −VBE and hence Vout = −VT ln

The output is therefore proportional to the natural logarithm of Vin . As with previous linear and nonlinear circuits, the virtual ground plays an essential role here as it guarantees the current flowing through Q 1 is xactly proportional to Vin . Logarithmic amplifiers (“logamps”) prove useful in applications where the input signal level may vary by a large factor. It may be desirable in such cases to amplify weak signals and attenuate (“compress”) strong signals hence a logarithmic dependence. The negative sign in Eq. (8.66) is to be expected: if Vin rises, so do the currents flowing through R1 and Q 1 , requiring an increase in VBE . Since the base is at zero, the emitter voltage must fall below zero to provide a greater collector current. Note that Q 1 operates in the active region because both the base and the collector remain at zero. The reader may wonder what happens if Vin becomes negative. Equation (8.66) predicts that Vout is not defined. In the actual circuit, Q 1 cannot carry a “negative” current, V in R1 R1 X V in

Figure 8.24

Logarithmic amplifier.

Q1 Vout

8.4 Op Amp Nonidealities

R1 X V in

Figure 8.25

339

M1 Vout

Square-root circuit.

the loop around the op amp is broken, and Vout approaches the positive supply rail. It is therefore necessary to ensure Vin remains positive. 8.3.3 Square-Root Amplifier Recognizing that the logarithmic amplifier of Fig. 8.24 in fact implements the inverse function of the exponential characteristic, we surmise that replacing the bipolar transistor with a MOSFET leads to a “square-root” amplifier. Illustrated in Fig. 8.25, such a circuit requires that M1 carry a current equal to Vin /R1 : Vin W 1 = μnCox (VGS − VTH )2 . R1 2 L (Channel-length modulation is neglected here.) Since VGS = −Vout , 2Vin Vout = − − VTH . W μnCox R1 L

(8.67)

(8.68)

If Vin is near zero, then Vout remains at −VTH , placing M1 at the edge of conduction. As Vin becomes more positive, Vout falls to allow M1 to carry a greater current. With its gate and drain at zero, M1 operates in saturation.

8.4

OP AMP NONIDEALITIES Our study in previous sections has dealt with a relatively idealized op amp model—except for the finite gain—so as to establish insight. In practice, however, op amps suffer from other imperfections that may affect the performance significantly. In this section, we deal with such nonidealities. 8.4.1 DC Offsets The op amp characteristics shown in Fig. 8.2 imply that Vout = 0 if Vin1 = Vin2 . In reality, a zero input difference may not give a zero output difference! Illustrated in Fig. 8.26(a), the characteristic is “offset” to the right or to the left; i.e., for Vout = 0, the input difference must be raised to a certain value, Vos , called the input “offset voltage.” What causes offset? The internal circuit of the op amp experiences random asymmetries (“mismatches”) during fabrication and packaging. For example, as shown conceptually in Fig. 8.26(b), the bipolar transistors sensing the two inputs may display slightly different base-emitter voltages. The same effect occurs for MOSFETs. We model the offset by a single voltage source placed in series with one of the inputs [Fig. 8.26(c)]. Since

340

Chapter 8 Operational Amplifier as a Black Box Vout Vos

Vos

V in1 – V in1

(a)

Vout

(b)

(c)

Figure 8.26 (a) Offset in an op amp, (b) mismatch between input devices, (c) representation of offset.

offsets are random and hence can be positive or negative, Vos can appear at either input with arbitrary polarity. Why are DC offsets important? Let us reexamine some of the circuit topologies studied in Section 8.2 in the presence of op amp offsets. Depicted in Fig. 8.27, the noninverting amplifier now sees a total input of Vin + Vos , thereby generating R1 (Vin + Vos ). (8.69) Vout = 1 + R2 In other words, the circuit amplifies the offset as well as the signal, thus incurring accuracy limitations.6 Vos V in

Vout R1 R2

Figure 8.27

Offset in noninverting amplifier.

Example 8.10

A truck weighing station employs an electronic pressure meter whose output is amplified by the circuit of Fig. 8.27. If the pressure meter generates 20 mV for every 100 kg of load and if the op amp offset is 2 mV, what is the accuracy of the weighing station?

Solution

An offset of 2 mV corresponds to a load of 10 kg. We therefore say the station has an error of ±10 kg in its measurements.

Exercise

What offset voltage is required for an accuracy of ±1 kg?

DC offsets may also cause “saturation” in amplifiers. The following example illustrates this point. 6 The reader can show that placing Vos in series with the inverting input of the op amp yields the same result.

8.4 Op Amp Nonidealities Example 8.11

341

An electrical engineering student constructs the circuit shown in Fig. 8.28 to amplify the signal produced by a microphone. The targeted gain is 104 so that very low level sounds (i.e., microvolt signals) can be detected. Explain what happens if op amp A1 exhibits an offset of 2 mV. A2

A1 X 10 k Ω

10 k Ω

100 Ω

Figure 8.28

Vout

100 Ω

Two-stage amplifier.

Solution

From Fig. 8.27, we recognize that the first stage amplifies the offset by a factor of 100, generating a dc level of 200 mV at node X (if the microphone produces a zero dc output). The second stage now amplifies VX by another factor of 100, thereby attempting to generate Vout = 20 V. If A2 operates with a supply voltage of, say, 3 V, the output cannot exceed this value, the second op amp drives its transistors into saturation (for bipolar devices) or triode region (for MOSFETs), and its gain falls to a small value. We say the second stage is saturated. (The problem of offset amplification in cascaded stages can be resolved through ac coupling.)

Exercise

Repeat the above example if the second stage has a voltage gain of 10.

DC offsets impact the inverting amplifier of Fig. 8.7(a) in a similar manner. We now examine the effect of offset on the integrator of Fig. 8.10. Suppose the input is set to zero and Vos is referred to the noninverting input [Fig. 8.29(a)]. What happens at the output? Recall from Fig. 8.20 and Eq. (8.61) that the response to this “input” consists of the input itself [the unity term in Eq. (8.61)] and the integral of the input [the second term in Eq. (8.61)]. We can therefore express Vout in the time domain as Vout

1 = Vos + R1C1

= Vos +

t

Vos dt

(8.70)

Vos t, R1C1

(8.71)

where the initial condition across C1 is assumed zero. In other words, the circuit integrates the op amp offset, generating an output that tends to +∞ or −∞ depending on the sign of Vos . Of course, as Vout approaches the positive or negative supply voltages, the transistors in the op amp fail to provide gain and the output saturates [Fig. 8.29(b)]. The problem of offsets proves quite serious in integrators. Even in the presence of an input signal, the circuit of Fig. 8.29(a) integrates the offset and reaches saturation. Figure 8.29(c) depicts a modification where resistor R2 is placed in parallel withC1 . Now the effect of Vos at the output is given by (8.9) because the circuits of Figs. 8.5 and 8.29(c) are similar

342

Chapter 8 Operational Amplifier as a Black Box C1 R1

Vout VCC

VCC Vout

V os

VEE

t

(a)

(b)

R2

R2

C1

C1

R1

R1

Vout

Vout

V in V os

(c)

(d)

Figure 8.29 (a) Offset in integrator, (b) output waveform, (c) addition of R2 to reduce effect of offset, (d) determination of transfer function.

at low frequencies:

R2 . Vout = Vos 1 + R1

(8.72)

For example, if Vos = 2 mV and R2 /R1 = 100, then Vout contains a dc error of 202 mV, but at least remains away from saturation. How does R2 affect the integration function? Disregarding Vos , viewing the circuit as shown in Fig. 8.29(d), and using (8.27), we have Vout 1 R2 =− . Vin R1 R2C1 s + 1

(8.73)

Thus, the circuit now contains a pole at −1/(R2C1 ) rather than at the origin. If the input signal frequencies of interest lie well above this value, then R2C1 s 1 and Vout 1 =− . Vin R1C1 s

(8.74)

That is, the integration function holds for input frequencies much higher than 1/(R2C1 ). Thus, R2 /R1 must be sufficiently small so as to minimize the amplified offset given by Eq. (8.72) whereas R2C1 must be sufficiently large so as to negligibly impact the signal frequencies of interest. 8.4.2 Input Bias Current Op amps implemented in bipolar technology draw a base current from each input. While relatively small (≈ 0.1–1 μA), the input bias currents may create inaccuracies in some circuits. As shown in Fig. 8.30, each bias current is modeled by a current source tied between the corresponding input and ground. Nominally, IB1 = IB2 .

8.4 Op Amp Nonidealities

343

V in1 V in2 I B1

Figure 8.30

I B2

Vout

Input bias currents.

Let us study the effect of the input currents on the noninverting amplifier. As depicted in Fig. 8.31(a), IB1 has no effect on the circuit because it flows through a voltage source. The current IB2 , on the other hand, flows through R1 and R2 , introducing an error. Using superposition and setting Vin to zero, we arrive at the circuit in Fig. 8.31(b), which can be transformed to that in Fig. 8.31(c) if IB2 and R2 are replaced with their Thevenin equivalent. Interestingly, the circuit now resembles the inverting amplifier of Fig. 8.7(a), thereby yielding R1 (8.75) Vout = −R2 IB2 − R2 = R1 IB2

(8.76)

if the op amp gain is infinite. This expression suggests that IB2 flows only through R1 , an expected result because the virtual ground at X in Fig. 8.31(b) forces a zero voltage across R2 and hence a zero current through it.

V in

Vout R1

I B1 I B2

Vout I B1

R2

X I B2

(a)

R1 R2

(b)

Vout R1

R2 – I B2 R 2 (c)

Figure 8.31 (a) Effect of input bias currents on noninverting amplifier, (b) simplified circuit, (c) Thevenin equivalent.

The error due to the input bias current appears similar to the DC offset effects illustrated in Fig. 8.27, corrupting the output. However, unlike DC offsets, this phenomenon is not random; for a given bias current in the bipolar transistors used in the op amp, the base currents drawn from the inverting and noninverting inputs remain approximately equal. We may therefore seek a method of canceling this error. For example, we can insert a corrective voltage in series with the noninverting input so as to drive Vout to zero (Fig. 8.32). Since Vcorr “sees” a noninverting amplifier, we have R1 + IB2 R1 . (8.77) Vout = Vcorr 1 + R2

344

Chapter 8 Operational Amplifier as a Black Box Vcorr Vout = 0 R1

X I B2

Figure 8.32

R2

Addition of voltage source to correct for input bias currents.

For Vout = 0, Vcorr = −IB2 (R1 ||R2 ).

(8.78)

Example 8.12

A bipolar op amp employs a collector current of 1 mA in each of the input devices. If β = 100 and the circuit of Fig. 8.32 incorporates R2 = 1 k, R1 = 10 k, determine the output error and the required value of Vcorr .

Solution

We have IB = 10 μA and hence Vout = 0.1 mV.

(8.79)

Vcorr = −9.1 μV.

(8.80)

Thus, Vcorr is chosen as

Exercise

Determine the correction voltage if β = 200.

Equation (8.78) implies that Vcorr depends on IB2 and hence the current gain of transistors. Since β varies with process and temperature, Vcorr cannot remain at a fixed value and must “track” β. Fortunately, (8.78) also reveals that Vcorr can be obtained by passing a base current through a resistor equal to R1 ||R2 , leading to the topology shown in Fig. 8.33. Here, if IB1 = IB2 , then Vout = 0 for Vin = 0. The reader is encouraged to take the finite gain of the op amp into account and prove that Vout is still near zero. From the drawing in Fig. 8.31(b), we observe that the input bias currents have an identical effect on the inverting amplifier. Thus, the correction technique shown in Fig. 8.33 applies to this circuit as well. In reality, asymmetries in the op amp’s internal circuitry introduce a slight (random) mismatch between IB1 and IB2 . Problem 8.44 studies the effect of this mismatch on the output in Fig. 8.33. R1 V in R2

I B1 Vout I B2

R1 R2

Figure 8.33

Correction for variation of beta.

8.4 Op Amp Nonidealities C1

345

C1

R1

R1 Vout

Vout – I B2 R 1

I B2 (a)

Figure 8.34

(b)

(a) Effect of input bias currents on integrator, (b) Thevenin equivalent.

We now consider the effect of the input bias currents on the performance of integrators. Illustrated in Fig. 8.34(a) with Vin = 0 and IB1 omitted (why?), the circuit forces IB2 to flow through C1 because R1 sustains a zero voltage drop. In fact, the Thevenin equivalent of R1 and IB2 [Fig. 8.34(b)] yields 1 Vin dt (8.81) Vout = − R1C1 =+

=

1 IB2 R1 dt R1C1

(8.82)

IB2 dt. C1

(8.83)

(Of course, the flow of IB2 through C1 leads to the same result.) In other words, the circuit integrates the input bias current, thereby forcing Vout to eventually saturate near the positive or negative supply rails. Can we apply the correction technique of Fig. 8.33 to the integrator? The model in Fig. 8.34(b) suggests that a resistor equal to R1 placed in series with the noninverting input can cancel the effect. The result is depicted in Fig. 8.35. C1 V in

R1 Vout R1

Figure 8.35

Correction for input currents in an integrator.

Example 8.13

An electrical engineering student attempts the topology of Fig. 8.35 in the laboratory but observes that the output still saturates. Give three possible reasons for this effect.

Solution

First, the DC offset voltage of the op amp itself is still integrated (Section 8.4.1). Second, the two input bias currents always suffer from a slight mismatch, thus causing incomplete cancellation. Third, the two resistors in Fig. 8.35 also exhibit mismatches, creating an additional error.

Exercise

Is resistor R1 necessary if the internal circuitry of the op amp uses MOS devices?

346

Chapter 8 Operational Amplifier as a Black Box Av A0

1

Figure 8.36

f1

fu

f

Frequency response of an op amp.

The problem of input bias current mismatch requires a modification similar to that in Fig. 8.29(c). The mismatch current then flows through R2 rather than through C1 (why?). 8.4.3 Speed Limitations Finite Bandwidth Our study of op amps has thus far assumed no speed limitations. In reality, the internal capacitances of the op amp degrade the performance at high frequencies. For example, as illustrated in Fig. 8.36, the gain begins to fall as the frequency of operation exceeds f1 . In this chapter, we provide a simple analysis of such effects, deferring a more detailed study to Chapter 11. To represent the gain roll-off shown in Fig. 8.36, we must modify the op amp model offered in Fig. 8.1. As a simple approximation, the internal circuitry of the op amp can be modeled by a first-order (one-pole) system having the following transfer function: A0 Vout (s) = s , Vin1 − Vin2 1+ ω1

(8.84)

where ω1 = 2π f1 . Note that at frequencies well below ω1 , s/ω1 1 and the gain is equal to A0 . At very high frequencies, s/ω1 1, and the gain of the op amp falls to unity at ωu = A0 ω1 . This frequency is called the “unity-gain bandwidth” of the op amp. Using this model, we can reexamine the performance of the circuits studied in the previous sections. Consider the noninverting amplifier of Fig. 8.5. We utilize Eq. (8.11) but replace A0 with the above transfer function: A0 Vout (s) = Vin

1+ 1+

s ω1

R2 A0 + s R1 + R 2 1+ ω1

.

(8.85)

Multiplying the numerator and the denominator by (1 + s/ω1 ) gives A0 Vout . (s) = s R Vin 2 + A0 + 1 ω1 R1 + R 2

(8.86)

The system is still of first order and the pole of the closed-loop transfer function is given by R2 |ω p,closed | = 1 + A0 ω1 . (8.87) R1 + R 2

8.4 Op Amp Nonidealities Av A0

Op Amp Frequency Response Noninverting Amplifier Frequency Response

A0 (1+

R2 A ) R 1+ R 2 0 1

fu

f1 (1+

Figure 8.37

347

f

R2 A )f R 1+ R 2 0 1

Frequency response of open-loop op amp and closed-loop circuit.

As depicted in Fig. 8.37, the bandwidth of the closed-loop circuit is substantially higher than that of the op amp itself. This improvement, of course, accrues at the cost of a proportional reduction in gain—from A0 to 1 + R2 A0 /(R1 + R2 ). Example 8.14

A noninverting amplifier incorporates an op amp having an open-loop gain of 100 and bandwidth of 1 MHz. If the circuit is designed for a closed-loop gain of 16, determine the resulting bandwidth and time constant.

Solution

For a closed-loop gain of 16, we require that 1 + R1 /R2 = 16 and hence R2 A 0 ω1 |ω p,closed | = 1 + R1 + R 2 ⎛ ⎞ ⎜ =⎜ ⎝1 +

1 R1 +1 R2

⎟ A0 ⎟ ⎠ω1

= 2π × (635 MHz).

(8.88)

(8.89)

(8.90)

−1

Given by |ω p,closed | , the time constant of the circuit is equal to 2.51 ns. Exercise

Repeat the above example if the op amp gain is 500. The above analysis can be repeated for the inverting amplifier as well. The reader can prove that the result is similar to Eq. (8.87). The finite bandwidth of the op amp may considerably degrade the performance of integrators. The analysis is beyond the scope of this book, but it is outlined in Problem 8.47 for the interested reader. Another critical issue in the use of op amps is stability; if placed in the topologies seen above, some op amps may oscillate. Arising from the internal circuitry of the op amp, this phenomenon often requires internal or external stabilization, also called “frequency compensation.” These concepts are studied in Chapter 12. Slew Rate In addition to bandwidth and stability problems, another interesting effect is observed in op amps that relates to their response to large signals. Consider the noninverting configuration shown in Fig. 8.38(a), where the closed-loop transfer function is given by Eq. (8.86). A small step of V at the input thus results in an amplified output waveform

348

Chapter 8 Operational Amplifier as a Black Box

V in

V in Vout

V in

t

ΔV

2 ΔV

t R2

R1

Linear Settling

V out

V out

Ramp

t (a)

t

(b)

(c)

Figure 8.38 (a) Noninverting amplifier, (b) input and output waveforms in linear regime, (c) input and output waveforms in slewing regime.

V in

t Without Slewing

V out

With Slewing

t

Figure 8.39

Output settling speed with and without slewing.

having a time constant equal to |ω p,closed |−1 [Fig. 8.38(b)]. If the input step is raised to 2V, each point on the output waveform also rises by a factor of two.7 In other words, doubling the input amplitude doubles both the output amplitude and the output slope. In reality, op amps do not exhibit the above behavior if the signal amplitudes are large. As illustrated in Fig. 8.38(c), the output first rises with a constant slope (i.e., as a ramp) and eventually settles as in the linear case of Fig. 8.38(b). The ramp section of the waveform arises because, with a large input step, the internal circuitry of the op amp reduces to a constant current source charging a capacitor. We say the op amp “slews” during this time. The slope of the ramp is called the “slew rate” (SR). Slewing further limits the speed of op amps. While for small-signal steps, the output response is determined by the closed-loop time constant, large-signal steps must face slewing prior to linear settling. Figure 8.39 compares the response of a non-slewing circuit with that of a slewing op amp, revealing the longer settling time in the latter case. It is important to understand that slewing is a nonlinear phenomenon. As suggested by the waveforms in Fig. 8.38(c), the points on the ramp section do not follow linear scaling (if x → y, then 2x → / 2y). The nonlinearity can also be observed by applying a 7

Recall that in a linear system, if x(t) → y(t), then 2x(t) → 2y(t).

8.4 Op Amp Nonidealities

V in

Vout

V in R2

349

Vout

t

R1

(b)

(a)

Vout

V in t1

t2

t (c)

Figure 8.40 (a) Simple noninverting amplifier, (b) input and output waveforms without slewing, (c) input and output waveforms with slewing.

large-signal sine wave to the circuit of Fig. 8.38(a) and gradually increasing the frequency (Fig. 8.40). At low frequencies, the op amp output “tracks” the sine wave because the maximum slope of the sine wave remains less than the op amp slew rate [Fig. 8.40(a)]. Writing Vin (t) = V0 sin ωt and Vout (t) = V0 (1 + R1 /R2 ) sin ωt, we observe that R1 dVout ω cos ωt. (8.91) = V0 1 + dt R2 The output therefore exhibits a maximum slope of V0 ω(1 + R1 /R2 ) (at its zero crossing points), and the op amp slew rate must exceed this value to avoid slewing. What happens if the op amp slew rate is insufficient? The output then fails to follow the sinusoidal shape while passing through zero, exhibiting the distorted behavior shown in Fig. 8.40(b). Note that the output tracks the input so long as the slope of the waveform does not exceed the op amp slew rate, e.g., between t1 and t2 . Example 8.15

The internal circuitry of an op amp can be simplified to a 1-mA current source charging a 5-pF capacitor during large-signal operation. If an amplifier using this op amp produces a sinusoid with a peak amplitude of 0.5 V, determine the maximum frequency of operation that avoids slewing.

Solution

The slew rate is given by I/C = 0.2 V/ns. For an output given by Vout = Vp sin ωt, where Vp = 0.5 V, the maximum slope is equal to dVout = Vp ω. (8.92) dt max Equating this to the slew rate, we have ω = 2π (63.7 MHz).

(8.93)

That is, for frequencies above 63.7 MHz, the zero crossings of the output experience slewing. Exercise

Plot the output waveform if the input frequency is 200 MHz.

350

Chapter 8 Operational Amplifier as a Black Box VDD

VDD V max

V in1 V in2 Vout 0

Figure 8.41

V min

Maximum op amp output swings.

Equation (8.91) indicates that the onset of slewing depends on the closed-loop gain, 1 + R1 /R2 . To define the maximum sinusoidal frequency that remains free from slewing, it is common to assume the worst case, namely, when the op amp produces its maximum allowable voltage swing without saturation. As exemplified by Fig. 8.41, the largest sinusoid permitted at the output is given by Vout =

Vmax + Vmin Vmax − Vmin sin ωt + , 2 2

(8.94)

where Vmax and Vmin denote the bounds on the output level without saturation. If the op amp provides a slew rate of SR, then the maximum frequency of the above sinusoid can be obtained by writing dVout = SR (8.95) dt max and hence ωFP =

SR . Vmax − Vmin 2

(8.96)

Called the “full-power bandwidth,” ωFP serves as a measure of the useful large-signal speed of the op amp. 8.4.4 Finite Input and Output Impedances Actual op amps do not provide an infinite input impedance8 or a zero output impedance— the latter often creating limitations in the design. We analyze the effect of this nonideality on one circuit here. Consider the inverting amplifier shown in Fig. 8.42(a), assuming the op amp suffers from an output resistance, Rout . How should the circuit be analyzed? We return to the model in Fig. 8.1 and place Rout in series with the output voltage source [Fig. 8.42(b)]. We must solve the circuit in the presence of Rout . Recognizing that the current flowing through Rout is equal to (−A0 vX − vout )/Rout , we write a KVL from vin to vout through R2 and R1 : vin + (R1 + R2 )

−A0 vX − vout = vout . Rout

8 Op amps employing MOS transistors at their input exhibit a very high input impedance at low frequencies.

(8.97)

8.5 Design Examples R1

R1

R2 X

R2 Vout

V in

R out

X

v in

v out

– A 0v X

(a)

Figure 8.42

351

(b)

(a) Inverting amplifier, (b) effect of finite output resistance of op amp.

To construct another equation for vX , we view R1 and R2 as a voltage divider: vX =

R2 (vout − vin ) + vin . R1 + R 2

(8.98)

Substituting for vX in Eq. (8.97) thus yields R1 vout =− vin R2

A0 − 1+

Rout R1

Rout R1 + A0 + R2 R2

.

(8.99)

The additional terms −Rout /R1 in the numerator and Rout /R2 in the denominator increase the gain error of the circuit.

Example 8.16

An electrical engineering student purchases an op amp with A0 = 10,000 and Rout = 1 and constructs the amplifier of Fig. 8.42(a) using R1 = 50 and R2 = 10 . Unfortunately, the circuit fails to provide large voltage swings at the output even though Rout /R1 and Rout /R2 remain much less than A0 in Eq. (8.99). Explain why.

Solution

For an output swing of, say, 2 V, the op amp may need to deliver a current as high as 40 mA to R1 (why?). Many op amps can provide only a small output current even though their small-signal output impedance is very low.

Exercise

If the op amp can deliver a current of 5 mA, what value of R1 is acceptable for output voltages as high as 1 V?

8.5

DESIGN EXAMPLES Following our study of op amp applications in the previous sections, we now consider several examples of the design procedure for op amp circuits. We begin with simple examples and gradually proceed to more challenging problems.

352

Chapter 8 Operational Amplifier as a Black Box

Example 8.17

Design an inverting amplifier with a nominal gain of 4, a gain error of 0.1%, and an input impedance of at least 10 k. Determine the minimum op amp gain required here.

Solution

For an input impedance of 10 k, we choose the same value of R2 in Fig. 8.7(a), arriving at R1 = 40 k for a nominal gain of 4. Under these conditions, Eq. (8.21) demands that 1 R1 1+ < 0.1% (8.100) A0 R2 and hence A0 > 5000.

(8.101)

Exercise

Repeat the above example for a nominal gain of 8 and compare the results.

Example 8.18

Design a noninverting amplifier for the following specifications: closed-loop gain = 5, gain error = 1%, closed-loop bandwidth = 50 MHz. Determine the required open-loop gain and bandwidth of the op amp. Assume the op amp has an input bias current of 0.2 μA.

Solution

From Fig. 8.5 and Eq. (8.9), we have R1 = 4. R2

(8.102)

The choice of R1 and R2 themselves depends on the “driving capability” (output resistance) of the op amp. For example, we may select R1 = 4 k and R2 = 1 k and check the gain error from Eq. (8.99) at the end. For a gain error of 1%, 1 R1 1+ < 1% (8.103) A0 R2 and hence A0 > 500. Also, from Eq. (8.87), the open-loop bandwidth is given by ω p,closed ω1 > R2 1+ A0 R1 + R 2 ω p,closed ω1 > R1 −1 1+ 1+ A0 R2 2π (50 MHz) . 100 Thus, the op amp must provide an open-loop bandwidth of at least 500 kHz. >

Exercise

Repeat the above example for a gain error of 2% and compare the results.

(8.104)

(8.105)

(8.106)

(8.107)

Problems

353

Example 8.19

Design an integrator for a unity-gain frequency of 10 MHz and an input impedance of 20 k. If the op amp provides a slew rate of 0.1 V/ns, what is the largest peakto-peak sinusoidal swing at the input at 1 MHz that produces an output free from slewing?

Solution

From Eq. (8.29), we have 1 =1 R1C1 (2π × 10 MHz)

(8.108)

C1 = 0.796 pF.

(8.109)

and, with R1 = 20 k,

(In discrete design, such a small capacitor value may prove impractical.) For an input given by Vin = Vp cos ωt, −1 Vp sin ωt, R1C1 ω

(8.110)

dVout 1 = Vp . dt max R1C1

(8.111)

Vout = with a maximum slope of

Equating this result to 0.1 V/ns gives Vp = 1.59 V.

(8.112)

In other words, the input peak-to-peak swing at 1 MHz must remain below 3.18 V for the output to be free from slewing. Exercise

How do the above results change if the op amp provides a slew rate of 0.5 V/ns?

PROBLEMS 8.1. For a unity-gain op-amp buffer, determine output voltage if Vin = +2V and AV = 1200. 8.2. An op amp exhibits the following nonlinear characteristic: Vout = α tanh[β(Vin1 − Vin2 )].

(8.113)

Sketch this characteristic and determine the small-signal gain of the op amp in the vicinity of Vin1 − Vin2 ≈ 0.

8.3. A noninverting amplifier contains an op amp with open-loop gain of 1500. If the current provides nominal gain of 50, determine the gain error. 8.4. A noninverting amplifier has a nominal gain of 10. It has open-loop gain of 1000. Determine the gain error. *8.5. A noninverting amplifier employs an op amp with a finite output impedance, Rout .

354

Chapter 8 Operational Amplifier as a Black Box

Representing the op amp as depicted in Fig. 8.43, compute the closed-loop gain and output impedance. What happens if A0 → ∞? R out V in1

Vout 0.8A 0 –4 mV

A0

–2 mV

+2 mV

Vout

+4 mV

V in1 – V in2

A 0 (V in1 – V in2 ) V in2

Figure 8.46 Figure 8.43

*8.6. A noninverting amplifier incorporates an op amp having an input impedance of Rin . Modeling the op amp as shown in Fig. 8.44, determine the closed-loop gain and input impedance. What happens if A0 → ∞? Vout R in

V in1

8.9. The circuit of a noninverting op amp is designed to have nominal gain of 5.00, but R1 and R2 suffer from mismatch of 5%, i.e., R1 = (1 + 0.05)R2 . What will be the actual voltage gain? (Refer the log below). Vout

Vin

R1

A 0 (V in1 – V in2 )

R2

V in2

Figure 8.47 Figure 8.44

8.7. In the noninverting amplifier shown in Fig. 8.45, resistor R2 deviates from its nominal value by R. Calculate the gain error of the circuit if R/R2 1. V in1 A0 V in

V in2

8.10. For noninverting amplifier shown in Fig 8.48, find expression for Vout . Vout

Vin

R1

Vout

R2

R1 R2

Figure 8.45

*8.8. The input/output characteristic of an op amp can be approximated by the piecewiselinear behavior illustrated in Fig. 8.46, where the gain drops from A0 to 0.8A0 and eventually to zero as |Vin1 − Vin2 | increases. Suppose this op amp is used in a noninverting amplifier with a nominal gain of 5. Plot the closed-loop input/output characteristic of the circuit. (Note that the closed-loop gain experiences much less variation; i.e., the closed-loop circuit is much more linear.)

Figure 8.48

8.11. For Fig 8.49, calculate output voltage Vout . 20 k Vin 3V

10 k R1

X Y

R2 Vout

200 k R3

R4

Figure 8.49

20 k

Problems 8.12. The op amp used in an inverting amplifier exhibits a finite input impedance, Rin . Modeling the op amp as shown in Fig. 8.43, determine the closed-loop gain and input impedance. 8.13. Derive the expression for output voltage in terms of input voltage for the circuit shown in Fig. 8.50.

355

which output voltage switches from 0 to 5 V and 5 to −5 V. 1 μt 5V

R V

0V

Vout

1 kΩ

Figure 8.53

R2 M1

R1

Vout

Vin

8.17. The integrator of Fig. 8.53 is used to amplify a sinusoidal input by a factor of 10. If A0 = ∞ and R1C1 = 10 ns, compute the frequency of the sinusoid.

*8.18. Consider the integrator shown in Fig. 8.53 and suppose the op amp is modeled as Figure 8.50 shown in Fig. 8.43. Determine the transfer function Vout /Vin and compare the location 8.14. Assuming A0 = ∞, compute the closedof the pole with that given by Eq. (8.37). loop gain of the inverting amplifier shown *8.19. The op amp used in the integrator of Fig. in Fig. 8.51. Verify that the result reduces to 8.53 exhibits a finite output impedance and expected values if R1 → 0 or R3 → 0. is modeled as depicted in Fig. 8.44. Compute R3

the transfer function Vout /Vin and compare the location of the pole with that given by Eq. (8.37).

R1 R4

R2 Vout

V in

8.20. The differentiator shown in Fig 8.54 amplifies input by 15, at a frequency of 2 MHZ. If A0 =∞, determine the value of R1C 1 .

Figure 8.51

C1

8.15. Design an inverting amplifier of Fig 8.52 for a nominal gain of 6, gain error of 0.05%, and an input impedance of at least 8 k. R1

R2 Vin Figure 8.52

X Vout

Vin

R1 Vout

Figure 8.54

8.21. We wish to design the differentiator of Fig. 8.54 for a pole frequency of 100 MHz. If the values of R1 and C1 cannot be lower than 1 k and 1 nF, respectively, compute the required gain of the op amp.

*8.22. Suppose the op amp in Fig. 8.54 exhibits a finite input impedance and is modeled as shown in Fig. 8.43. Determine the trans8.16. For the circuit shown in Fig. 8.53, the outfer function Vout /Vin and compare the result put can swing from +5 V to −5 V. The input with Eq. (8.42). is a step waveform. Analyze for timings at

356

Chapter 8 Operational Amplifier as a Black Box

8.23. Calculate the transfer function of the circuit shown in Fig. 8.55 if A0 = ∞. What choice of component values reduces |Vout /Vin | to unity at all frequencies?

8.28. For Fig. 8.58, using ideal op-amp model, calculate the closed-loop gain vv0s . Also find i0 when vS = 1.2V. i =0 v2 2

R2 C1

i1 = 0 v1

C2

vs

Figure 8.55

V3

RF

R1 R2 X

V2

v0

10 kΩ

Figure 8.58

8.24. For Fig 8.56, if V1 = 0.8 V, V2 = 1.1 and and V3 = 0.5 V, R1 = R2 = R3 = 5 k RF = 10 k A0 = ∞, find Vout . The notation at the positive terminal of the operational amplifier is the symbol for ground or 0 V. V1

20 kΩ

0 2.5 kΩ v 0

Vout

A0

R1

V in

i0

8.29. Plot the current flowing through D1 in the precision rectifier of Fig. 8.22(b) as a function of time for a sinusoidal input. 8.30. Plot the current flowing through D1 in the precision rectifier of Fig. 8.23(a) as a function of time for a sinusoidal input. 8.31. For Fig 8.59, find v0 for input voltage vi = sin ωt.

Vout

R3

R V i = sin ω t 10 k

R 10 k v0

D

Figure 8.56 Figure 8.59

8.25. For Fig. 8.56, if V1 = V0 sinωt, V2 = V0 sin2ωt, V3 = V0 sin4ωt, R1 = R2 = R3 = R = 4 k, RF = 8 k, A0 = ∞, plot Vout as a function of time. 8.26. The voltage adder of Fig. 8.56 employs an op amp having a finite output impedance, Rout . Using the op amp model depicted in Fig. 8.44, compute Vout in terms of V2 and V3 . 8.27. Due to a manufacturing error, a parasitic resistance RP has appeared in the adder of Fig. 8.57. Calculate Vout in terms of V1 and V2 for A0 = ∞ and A0 < ∞. (Note that RP can also represent the input impedance of the op amp.) RF V1 V2

R2 R1

Figure 8.57

X A0 RP

Vout

8.32. For Fig. 8.60, find V i value at which V 0 will be zero, for the given values, of components and diode equation as ID = I0 (eqV/ηKT − 1) where V is forward voltages η = 2 for silicon. R = 200 k, IS = 1.5μA, KT/q = 26 mV. R Vi

Ii

V0 V0 V 1 = RIS

Figure 8.60

8.33. We wish to improve the speed of the rectifier shown in Fig. 8.22(b) by connecting a diode from node Y to ground. Explain how this can be accomplished. 8.34. Suppose Vin in Fig. 8.24 varies from −1 V to +1 V. Sketch Vout and VX as a function of Vin if the op amp is ideal. 8.35. Determine the small-signal voltage gain of the logarithmic amplifier depicted in

Problems Fig. 8.24 by differentiating both sides of Eq. (8.66) with respect to Vin . Plot the magnitude of the gain as a function of Vin and explain why the circuit is said to provide a “compressive” characteristic. *8.36. A student attempts to construct a noninverting logarithmic amplifier as illustrated in Fig. 8.61. Describe the operation of this circuit.

V in

Figure 8.61

8.37. For Fig. 8.62, analyze the function of a circuit and verify its function mathematically.

R2 A0

V in

Vout

8.42. For Fig. 8.66(a), calculate output voltage V 0 for the input offset voltage of 2 mV.

R

M1

Vin 1

R1

8.41. The integrator of Fig. 8.29(c) must operate with frequencies as low as 1 kHz while providing an output offset of less than 20 mV with an op amp offset of 3 mV. Determine the required values of R1 and R2 if C1 ≤ 100 pF.

Vout

Vin 2

8.40. For the inverting amplifier illustrated in Fig. 8.65, calculate Vout if the op amp exhibits an input offset of Vos . Assume A0 = ∞.

Figure 8.65

Q1

R1 X

357

2 kΩ R1

Vout

2000 k Ω R2 V0 (a)

Figure 8.62

8.38. For Fig. 8.63, analyze the functionality of circuit and derive expression for V out . Vin 2

R1

Vin

K2

R1 Vout

i 1 V sin 0 (b)

V0 sin - input offset voltage. X

M2 Vout

Vin 1

Figure 8.66

8.43. What will be the effect of an inverting op amp shown in Fig. 8.66(b) if the effect of input offset is considered.

Figure 8.63

8.39. For Fig. 8.64, analyze the current for input offset voltage and output voltage. V0 sin

V0 R2 R1

V0 sin - input offset voltage. Figure 8.64

i2

8.44. Suppose the input bias currents in Fig. 8.31 incur a small offset, i.e., IB1 = IB2 + I. Calculate Vout . 8.45. Explain the effect of output offset voltage on the output voltage of an op-amp integrator, when input voltage is a sine wave. 8.46. An inverting amplifier incorporates an op amp whose frequency response is given by Eq. (8.84). Determine the transfer function of the closed-loop circuit and compute the bandwidth.

358

Chapter 8 Operational Amplifier as a Black Box

**8.47. Figure 8.67 shows an integrator employing an op amp whose frequency response is given by A(s) =

A0 1+

s . ω0

(8.114)

Determine the transfer function of the overall integrator. Simplify the result if ω0 1/(R1C1 ).

Design Problems 8.50. Design the inverting amplifier of Fig. 8.7(a) for a nominal gain of 8 and a gain error of 0.1%. Assume Rout = 100 . 8.51. With a finite op amp gain, the step response of an integrator is a slow exponential rather than an ideal ramp. Design an integrator whose step response approximates V(t) = αt with an error less than 0.1% for the range 0 < V(t) < V0 (Fig. 8.68). Assume α = 10 V/μs, V0 =1 V, and the capacitor must remain below 20 pF.

C1

V0

ΔV ΔV = 0.1% lR

am

Vout

V in

V0

p

R1

Id

ea

A (s (

Vout

Figure 8.67 t

8.48. The unity-gain buffer of Fig. 8.3 must be designed to drive a 100 load with a gain error of 0.5%. Determine the required op amp gain if the op amp has an output resistance of 1 k. 8.49. A noninverting amplifier with a nominal gain of 4 senses a sinusoid having a peak amplitude of 0.5 V. If the op amp provides a slew rate of 1 V/ns, what is the highest input frequency for which no slewing occurs?

Figure 8.68

8.52. A voltage adder must realize the following function: Vout = α1 V1 + α2 V2 , where α1 = −0.5 and α2 = −1.5. Design the circuit if the worst-case error in α1 or α2 must remain below 0.5% and the input impedance seen by V1 or V2 must exceed 10 k. 8.53. Design a logarithmic amplifier that “compresses” an input range of [0.1 V 2 V] to an output range of [ − 0.5 V − 1 V].

SPICE PROBLEMS 8.1. Assuming an op amp gain of 1000 and IS = 10−17 A for D1 , plot the input/output characteristic of the precision rectifier shown in Fig. 8.69. V in V out 1 kΩ

Y

8.3. In the circuit of Fig. 8.70, each op amp provides a gain of 500. Apply a 10-MHz sinusoid at the input and plot the output as a function of time. What is the error in the output amplitude with respect to the input amplitude? 10 pF

D1

Figure 8.69

8.2. Repeat Problem 8.1 but assuming that the op amp suffers from an output resistance of 1 k.

1 kΩ

V in

Figure 8.70

10 pF 1 kΩ

Vout

Chapter

9

Cascode Stages and Current Mirrors

Following our study of basic bipolar and MOS amplifiers in previous chapters, we deal with two other important building blocks in this chapter. The “cascode”1 stage is a modified version of common-emitter or common-source topologies and proves useful in high-performance circuit design, and the “current mirror” is an interesting and versatile technique employed extensively in integrated circuits. Our study includes both bipolar and MOS implementations of each building block. Shown below is the outline of the chapter.

Cascode Stages • Cascode as Current Source

Current Mirrors

➤

• Bipolar Mirrors • MOS Mirrors

• Cascode as Amplifier

9.1

CASCODE STAGE 9.1.1 Cascode as a Current Source Recall from Chapters 5 and 7 that the use of current-source loads can markedly increase the voltage gain of amplifiers. We also know that a single transistor can operate as a current source but its output impedance is limited due to the Early effect (in bipolar devices) or channel-length modulation (in MOSFETs). How can we increase the output impedance of a transistor that acts as a current source? An important observation made in Chapters 5 and 7 forms the foundation for our

1 Coined in the vacuum-tube era, the term “cascode” is believed to be an abbreviation of “cascaded triodes.”

359

360

Chapter 9 Cascode Stages and Current Mirrors R out1 Vb

R out2 Vb

Q1 RE

Figure 9.1

M1 RS

Output impedance of degenerated bipolar and MOS devices.

study here: emitter or source degeneration “boosts” the impedance seen looking into the collector or drain, respectively. For the circuits shown in Fig. 9.1, we have Rout1 = [1 + gm(RE ||rπ )]rO + RE ||rπ = (1 + gmrO )(RE ||rπ ) + rO

(9.1) (9.2)

Rout2 = (1 + gmRS )rO + RS

(9.3)

= (1 + gmrO )RS + rO ,

(9.4)

observing that RE or RS can be increased to raise the output resistance. Unfortunately, however, the voltage drop across the degeneration resistor also increases proportionally, consuming voltage headroom and ultimately limiting the voltage swings provided by the circuit using such a current source. For example, if RE sustains 300 mV and Q 1 requires a minimum collector-emitter voltage of 500 mV, then the degenerated current source “consumes” a headroom of 800 mV. Bipolar Cascode In order to relax the trade-off between the output impedance and the voltage headroom, we can replace the degeneration resistor with a transistor. Depicted in Fig. 9.2(a) for the bipolar version, the idea is to introduce a high small-signal resistance (= rO2 ) in the emitter of Q 1 while consuming a headroom independent of the current. In this case, Q 2 requires a headroom of approximately 0.4 V to remain in soft saturation. This configuration is called the “cascode” stage.2 To emphasize that Q 1 and Q 2 play distinctly different roles here, we call Q 1 the cascode transistor and Q 2 the degeneration transistor. Note that IC 1 ≈ IC 2 if β1 1. R out V b1

Q1

V b2

Q2 (a)

Figure 9.2

R out Vb

Q1 r O2

(b)

(a) Cascode bipolar current source, (b) equivalent circuit.

Let us compute the output impedance of the bipolar cascode of Fig. 9.2(a). Since the base-emitter voltage of Q 2 is constant, this transistor simply operates as a small-signal resistance equal to rO2 [Fig. 9.2(b)]. In analogy with the resistively-degenerated counterpart 2

Or simply the “cascode.”

9.1 Cascode Stage

361

in Fig. 9.1, we have Rout = [1 + gm1 (rO2 ||rπ 1 )]rO1 + rO2 ||rπ 1 .

(9.5)

Since typically gm1 (rO2 ||rπ 1 ) 1, Rout ≈ (1 + gm1rO1 )(rO2 ||rπ 1 )

(9.6)

≈ gm1rO1 (rO2 ||rπ 1 ).

(9.7)

Note, however, that rO cannot generally be assumed much greater than rπ . Example 9.1

IfQ 1 andQ 2 in Fig. 9.2(a) are biased at a collector current of 1 mA, determine the output resistance. Assume β = 100 and VA = 5 V for both transistors.

Solution

Since Q 1 and Q 2 are identical and biased at the same current level, Eq. (9.7) can be simplified by noting that gm = IC /VT , rO = VA /IC , and rπ = βVT /IC :

Rout

VA2 βVT · IC 1 VA1 I IC 1 ≈ · · C2 βVT VT IC 1 VA2 + IC 2 IC 1 1 VA βVA VT ≈ · · , IC 1 VT VA + βVT

(9.8)

(9.9)

where IC = IC 1 = IC 2 and VA = VA1 = VA2 . At room temperature, VT ≈ 26 mV and hence Rout ≈ 328.9 k. (9.10) By comparison, the output resistance of Q 1 with no degeneration would be equal to rO1 = 5 k; i.e., “cascoding” has boosted Rout by a factor of 66 here. Note that rO2 and rπ 1 are comparable in this example. Exercise

What Early voltage is required for an output resistance of 500 k?

It is interesting to note that if rO2 becomes much greater than rπ 1 , then Rout1 approaches Rout,max ≈ gm1rO1rπ 1 ≈ β1rO1 .

(9.11) (9.12)

This is the maximum output impedance provided by a bipolar cascode. After all, even with rO2 = ∞ (Fig. 9.3) [or RE = ∞ in Eq. (9.1)], rπ 1 still appears from the emitter of Q 1 to ac ground, thereby limiting Rout to β1rO1 . Example 9.2

Suppose in Example 9.1, the Early voltage ofQ 2 is equal to 50 V.3 Compare the resulting output impedance of the cascode with the upper bound given by Eq. (9.12).

3 In integrated circuits, all bipolar transistors fabricated on the same wafer exhibit the same Early voltage. This example applies to discrete implementations.

362

Chapter 9 Cascode Stages and Current Mirrors R out Q1 r π1

Figure 9.3

Solution

Ideal

Cascode topology using an ideal current source.

Since gm1 = (26 )−1 , rπ1 = 2.6 k, rO1 = 5 k, and rO2 = 50 k, we have Rout ≈ gm1rO1 (rO2 ||rπ 1 )

(9.13)

≈ 475 k.

(9.14)

The upper bound is equal to 500 k, about 5% higher. Exercise

Repeat the above example if the Early voltage of Q 1 is 10 V.

Example 9.3

We wish to increase the output resistance of the bipolar cascode of Fig. 9.2(a) by a factor of two through the use of resistive degeneration in the emitter of Q 2 . Determine the required value of the degeneration resistor if Q 1 and Q 2 are identical.

Solution

As illustrated in Fig. 9.4, we replace Q 2 and RE with their equivalent resistance from Eq. (9.1): RoutA = [1 + gm2 (RE ||rπ 2 )]rO2 + RE ||rπ 2 .

(9.15)

It follows from Eq. (9.7) that Rout ≈ gm1rO1 (RoutA ||rπ 1 ).

(9.16)

We wish this value to be twice that given by Eq. (9.7): RoutA ||rπ 1 = 2(rO2 ||rπ 1 ).

(9.17)

R out R out V b1

V b2

Q1

Q2 RE

Figure 9.4

R outA

Vb

Q1 R outA

9.1 Cascode Stage

363

That is, RoutA =

2rO2rπ 1 . rπ 1 − rO2

(9.18)

In practice, rπ 1 is typically less than rO2 , and no positive value of RoutA exists! In other words, it is impossible to double the output impedance of the cascode by emitter degeneration. Exercise

Is there a solution if the output impedance must increase by a factor of 1.5?

What does the above result mean? Comparing the output resistances obtained in Examples 9.1 and 9.2, we recognize that even identical transistors yield an Rout (= 328.9 k) that is not far from the upper bound (= 500 k). More specifically, the ratio of (9.7) and (9.12) is equal to rO2 /(rO2 + rπ 1 ), a value greater than 0.5 if rO2 > rπ 1 . For completeness, Fig. 9.5 shows a pnp cascode, where Q 1 serves as the cascode device and Q 2 as the degeneration device. The output impedance is given by Eq. (9.5).

VCC V b2

Q2

V b1

Q1 R out

Figure 9.5

PNP cascode current source.

While we have arrived at the cascode as an extreme case of emitter degeneration, it is also possible to view the evolution as illustrated in Fig. 9.6. That is, since Q 2 provides only an output impedance of rO2 , we “stack” Q 1 on top of it to raise Rout .

R out R out = r O2 V b2

Figure 9.6

Q2

V b1

Q1

V b2

Q2

g m1 r O1 (r O2 r π 1 )

Evolution of cascode topology viewed as stacking Q 1 atop Q 2 .

364

Chapter 9 Cascode Stages and Current Mirrors

Example 9.4

Explain why the topologies depicted in Fig. 9.7 are not cascodes. R out

VCC

R out V b1

V b1

V b1

Q1

Q1

V b2

Q2

Q2

1 r g m2 O2

X

1 r g m2 O2

X

VCC

V b2

V b2

Q1 R out

(a)

Q1 R out

(b)

Figure 9.7 Solution

Unlike the cascode of Fig. 9.2(a), the circuits of Fig. 9.7 connect the emitter of Q 1 to the emitter of Q 2 . Transistor Q 2 now operates as a diode-connected device (rather than a current source), thereby presenting an impedance of (1/gm2 )||rO2 (rather than rO2 ) at node X. Given by Eq. (9.1), the output impedance, Rout , is therefore considerably lower: 1 1 Rout = 1 + gm1 ||rO2 ||rπ 1 rO1 + ||rO2 ||rπ 1 . (9.19) gm2 gm2 In fact, since 1/gm2 rO2 , rπ 1 and since gm1 ≈ gm2 (why?), gm1 1 rO1 + Rout ≈ 1 + gm2 gm2

(9.20)

≈ 2rO1 .

(9.21)

The same observations apply to the topology of Fig. 9.7(b). Exercise

Estimate the output impedance for a collector bias current of 1 mA and VA = 8 V. MOS Cascodes The similarity of Eqs. (9.1) and (9.3) for degenerated stages suggests that cascoding can also be realized with MOSFETs so as to increase the output impedance of a current source. Illustrated in Fig. 9.8, the idea is to replace the degeneration resistor with a MOS current source, thus presenting a small-signal resistance of rO2 from X to ground. Equation (9.3) can now be written as Rout = (1 + gm1rO2 )rO1 + rO2

(9.22)

≈ gm1rO1rO2 ,

(9.23)

where it is assumed gm1rO1rO2 rO1 , rO2 .

R out V b1

M1 X

V b2

Figure 9.8

R out Vb

M2

MOS cascode current source and its equivalent.

M1 r O2

9.1 Cascode Stage

365

Equation (9.23) is an extremely important result, implying that the output impedance is proportional to the intrinsic gain of the cascode device. Example 9.5

Design an NMOS cascode for an output impedance of 500 k and a current of 0.5 mA. For simplicity, assume M1 and M2 in Fig. 9.8 are identical (they need not be). Assume μnCox = 100 μA/V2 and λ = 0.1 V−1 .

Solution

We must determine W/L for both transistors such that gm1rO1rO2 = 500 k.

(9.24)

Since rO1 = rO2 = (λID )−1 = 20 k, we require that gm1 = (800 )−1 and hence W 1 2μnCox ID = . L 800 It follows that W = 15.6. L

(9.25)

(9.26)

We should also note that gm1rO1 = 25 1. Exercise

What is the output resistance if W/L = 32? Invoking the alternative view depicted in Fig. 9.6 for the MOS counterpart (Fig. 9.9), we recognize that stacking a MOSFET on top of a current source “boosts” the impedance by a factor of gm2rO2 (the intrinsic gain of the cascode transistor). This observation reveals an interesting point of contrast between bipolar and MOS cascodes: in the former, raising rO2 eventually leads to Rout,bip = βrO1 , whereas in the latter, Rout,MOS = gm1rO1rO2 increases with no bound.4 This is because in MOS devices, β and rπ are infinite (at low frequencies). R out R out = r O2

V b1

g m1 r O1 r O2

M1 X

V b2

Figure 9.9

V b2

M2

M2

MOS cascode viewed as stack of M1 atop M2 .

Figure 9.10 illustrates a PMOS cascode. The output resistance is given by Eq. (9.22). VDD V b2

M2 X

V b1

M1 R out

Figure 9.10 4

PMOS cascode current source.

In reality, other second-order effects limit the output impedance of MOS cascodes.

366

Chapter 9 Cascode Stages and Current Mirrors

Example 9.6

During manufacturing, a large parasitic resistor, RP , has appeared in a cascode as shown in Fig. 9.11. Determine the output resistance.

R out M1 V b1 V b2

RP M2

Figure 9.11 Solution

We observe that RP is in parallel with rO1 . It is therefore possible to rewrite Eq. (9.23) as Rout = gm1 (rO1 ||RP )rO2 .

(9.27)

If gm1 (rO1 ||RP ) is not much greater than unity, we return to the original equation, (9.22), substituting rO1 ||RP for rO1 : Rout = (1 + gm1rO2 )(rO1 ||RP ) + rO2 . Exercise

(9.28)

What value of RP degrades the output impedance by a factor of two?

9.1.2 Cascode as an Amplifier In addition to providing a high output impedance as a current source, the cascode topology can also serve as a high-gain amplifier. In fact, the output impedance and the gain of amplifiers are closely related. For our study below, we need to understand the concept of the transconductance for circuits. In Chapters 4 and 6, we defined the transconductance of a transistor as the change in the collector or drain current divided by the change in the base-emitter or gate-source voltage. This concept can be generalized to circuits as well. As illustrated in Fig. 9.12, the output voltage is set to zero by shorting the output node to ground, and the “short-circuit transconductance” of the circuit is defined as Gm =

i out . vin vout=0

(9.29)

The transconductance signifies the “strength” of a circuit in converting the input voltage to a current.5 Note the direction of iout in Fig. 9.12.

While omitted for simplicity in Chapters 4 and 6, the condition vout = 0 is also required for the transconductance of transistors. That is, the collector or drain must by shorted to ac ground.

5

9.1 Cascode Stage i out

Circuit

ac GND

v in

Figure 9.12

Example 9.7

367

Computation of transconductance for a circuit.

Calculate the transconductance of the CS stage shown in Fig. 9.13(a).

VDD

VDD

RD

RD

i out

v out v in

M1

v in

(a)

M1

ac GND

(b)

Figure 9.13

Solution

As depicted in Fig. 9.13(b), we short the output node to ac ground and, noting that RD carries no current (why?), write Gm =

iout vin

i D1 vGS1 = gm1 . =

(9.30) (9.31) (9.32)

Thus, in this case, the transconductance of the circuit is equal to that of the transistor. Exercise

How does Gm change if the width and bias current of the transistor are doubled?

Lemma

The voltage gain of a linear circuit can be expressed as Av = −GmRout ,

(9.33)

where Rout denotes the output resistance of the circuit (with the input voltage set to zero). Proof We know that a linear circuit can be replaced with its Norton equivalent [Fig. 9.14(a)]. Norton’s theorem states that iout is obtained by shorting the output to ground (vout = 0) and computing the short-circuit current [Fig. 9.14(b)]. We also relate iout to vin by the transconductance of the circuit, Gm = iout /vin . Thus, in Fig. 9.14(a), vout = −iout Rout = −Gmvin Rout

(9.34) (9.35)

368

Chapter 9 Cascode Stages and Current Mirrors

Vout

Vout i out

v in

R out

(a)

i out v in

(b)

Figure 9.14

(a) Norton equivalent of a circuit, (b) computation of short-circuit output current.

and hence vout = −GmRout . vin Example 9.8

(9.36)

Determine the voltage gain of the common-emitter stage shown in Fig. 9.15(a). VCC I1 v out v in

Q1

(a)

iX

i out v in

ac GND

Q1

(b)

Q1

vX

(c)

Figure 9.15

Solution

To calculate the short-circuit transconductance of the circuit, we place an ac short from the output to ground and find the current through it [Fig. 9.15(b)]. In this case, iout is simply equal to the collector current of Q 1 , gm1 vin , i.e., Gm =

iout vin

= gm1 .

(9.37) (9.38)

Note that rO does not carry a current in this test (why?). Next, we obtain the output resistance as depicted in Fig. 9.15(c): Rout =

vX iX

= rO1 .

(9.39) (9.40)

9.1 Cascode Stage

369

It follows that

Exercise

Av = −GmRout

(9.41)

= −gm1rO1 .

(9.42)

Suppose the transistor is degenerated by an emitter resistor equal to RE . The transconductance falls but the ouput resistance rises. Does the voltage gain increase or decrease?

The above lemma serves as an alternative method of gain calculation. It also indicates that the voltage gain of a circuit can be increased by raising the output impedance, as in cascodes. Bipolar Cascode Amplifier Recall from Chapter 4 that to maximize the voltage gain of a common-emitter stage, the collector load impedance must be maximized. In the limit, an ideal current source serving as the load [Fig. 9.16(a)] yields a voltage gain of Av = −gm1rO1 =−

(9.43)

VA . VT

(9.44)

In this case, the small-signal current, gm1 vin , produced by Q 1 flows through rO1 , thus generating an output voltage equal to −gm1 vinrO1 . Now, suppose we stack a transistor on top of Q 1 as shown in Fig. 9.16(b). We know from Section 9.1.1 that the circuit achieves a high output impedance and, from the above lemma, a voltage gain higher than that of a CE stage. VCC I1

VCC I1 v in

g Q1

v out

v m1 in

V b1

Q2

v in

Q1

v out r O1

(a)

(b)

Figure 9.16 (a) Flow of output current generated by a CE stage through rO1 , (b) use of cascode to increase the output impedance.

Let us determine the voltage gain of the bipolar cascode with the aid of the above lemma. As shown in Fig. 9.17(a), the short-circuit transconductance is equal to iout /vin . As a common-emitter stage,Q 1 still produces a collector current of gm1 vin , which subsequently flows through Q 2 and hence through the output short: iout = gm1 vin .

(9.45)

Gm = gm1 .

(9.46)

That is,

370

Chapter 9 Cascode Stages and Current Mirrors i out

i out

Q2

Q2

ac GND

Q1

g

v in

r O2 X Q1

v m1 in

v in

(a)

Figure 9.17

g

v m1 in

ac GND

r O1

(b)

(a) Short-circuit output current of a cascode, (b) detailed view of (a).

The reader may view Eq. (9.46) dubiously. After all, as shown in Fig. 9.17(b), the collector current of Q 1 must split between rO1 and the impedance seen looking into the emitter of Q 2 . We must therefore verify that only a negligible fraction of gm1 vin is “lost” in rO1 . Since the base and collector voltages of Q 2 are equal, this transistor can be viewed as a diode-connected device having an impedance of (1/gm2 )||rO2 . Dividing gm1 vin between this impedance and rO1 , we have iout = gm1 vin

rO1 ||rπ 2 . 1 rO1 ||rπ 2 + ||rO2 gm2

(9.47)

For typical transistors, 1/gm2 rO2 , rO1 , and hence iout ≈ gm1 vin .

(9.48)

That is, the approximation Gm = gm1 is reasonable. To obtain the overall voltage gain, we write from Eqs. (9.33) and (9.5), Av = −GmRout

(9.49)

= −gm1 {[1 + gm2 (rO1 ||rπ 2 )]rO2 + rO1 ||rπ 2 }

(9.50)

≈ −gm1 [gm2 (rO1 ||rπ 2 )rO2 + rO1 ||rπ 2 ].

(9.51)

Also, since Q 1 and Q 2 carry approximately equal bias currents, gm1 ≈ gm2 and rO1 ≈ rO2 : Av = −gm1rO1 [gm1 (rO1 ||rπ 2 ) + 1] ≈ −gm1rO1 gm1 (rO1 ||rπ 2 ).

(9.52) (9.53)

Compared to the simple CE stage of Fig. 9.16(a), the cascode amplifier exhibits a gain that is higher by a factor of gm1 (rO1 ||rπ 2 )—a relatively large value because rO1 and rπ 2 are much greater than 1/gm1 .

Example 9.9

The bipolar cascode of Fig. 9.16(b) is biased at a current of 1 mA. If VA = 5 V and β = 100 for both transistors, determine the voltage gain. Assume the load is an ideal current source.

9.1 Cascode Stage Solution

371

We have gm1 = (26 )−1 , rπ 1 ≈ rπ 2 ≈ 2600 , rO1 ≈ rO2 = 5 k. Thus, gm1 (rO1 ||rπ 2 ) = 65.8

(9.54)

|Av | = 12,654.

(9.55)

and from Eq. (9.53),

Cascoding thus raises the voltage gain by a factor of 65.8. Exercise

What Early voltage gives a gain of 5,000?

It is possible to view the cascode amplifier as a common-emitter stage followed by a common-base stage. Illustrated in Fig. 9.18, the idea is to consider the cascode device, Q 2 , as a common-base transistor that senses the small-signal current produced by Q 1 . This perspective may prove useful in some cases. VCC I1 v out CB Vb Stage

Q2

v in

Figure 9.18

Q1

CE Stage

Cascode amplifier as a cascade of a CE stage and a CB stage.

The high voltage gain of the cascode topology makes it attractive for many applications. But, in the circuit of Fig. 9.16(b), the load is assumed to be an ideal current source. An actual current source lowers the impedance seen at the output node and hence the voltage gain. For example, the circuit illustrated in Fig. 9.19(a) suffers from a low gain because the pnp current source introduces an impedance of only rO3 from the output node to ac ground, dropping the output impedance to Rout = rO3 ||{[1 + gm2 (rO1 ||rπ 2 )]rO2 + rO1 ||rπ 2 }

(9.56)

≈ rO3 ||[gm2rO2 (rO1 ||rπ 2 ) + rO1 ||rπ 2 ].

(9.57)

How should we realize the load current source to maintain a high gain? We know from Section 9.1.1 that cascoding also raises the output impedance of current sources, postulating that the circuit of Fig. 9.5 is a good candidate and arriving at the stage depicted in Fig. 9.19(b). The output impedance is now given by the parallel

372

Chapter 9 Cascode Stages and Current Mirrors VCC VCC V b2

VCC

Q3

r O3 v out

V b3

Q4

V b2

Q3 R op R on

v out

V b1

Q2

V b1

Q2

v in

Q1

v in

Q1

R out

V b1

Q2

v in

Q1

(a)

(b)

Figure 9.19 (a) Cascode with a simple current-source load, (b) use of cascode in the load to raise the voltage gain.

combination of those of the npn and pnp cascodes, Ron and Rop , respectively. Using Eq. (9.7), we have Ron ≈ gm2rO2 (rO1 ||rπ 2 )

(9.58)

Rop ≈ gm3rO3 (rO4 ||rπ 3 ).

(9.59)

Note that, since npn and pnp devices may display different Early voltages, rO1 (= rO2 ) may not be equal to rO3 (= rO4 ). Recognizing that the short-circuit transconductance, Gm, of the stage is still approximately equal to gm1 (why?), we express the voltage gain as Av = −gm1 (Ron ||Rop ) ≈ −gm1 {[gm2rO2 (rO1 ||rπ 2 )]||[gm3rO3 (rO4 ||rπ 3 )]}.

(9.60) (9.61)

This result represents the highest voltage gain that can be obtained in a cascode stage. For comparable values of Ron and Rop , this gain is about half of that expressed by Eq. (9.53).

Example 9.10

Suppose the circuit of Example 9.9 incorporates a cascode load using pnp transistors with VA = 4 V and β = 50. What is the voltage gain?

Solution

The load transistors carry a collector current of approximately 1 mA. Thus, Rop = gm3rO3 (rO4 ||rπ 3 )

(9.62)

= 151 k

(9.63)

Ron = 329 k.

(9.64)

and

9.1 Cascode Stage

373

It follows that |Av | = gm1 (Ron ||Rop )

(9.65)

= 3,981.

(9.66)

Compared to the ideal current source case, the gain has fallen by approximately a factor of 3 because the pnp devices suffer from a lower Early voltage and β. Exercise

Repeat the above example for a collector bias current of 0.5 mA.

It is important to take a step back and appreciate our analysis techniques. The cascode of Fig. 9.19(b) proves quite formidable if we attempt to replace each transistor with its small-signal model and solve the resulting circuit. Our gradual approach to constructing this stage reveals the role of each device, allowing straightforward calculation of the output impedance. Moreover, the lemma illustrated in Fig. 9.14 utilizes our knowledge of the output impedance to quickly provide the voltage gain of the stage. CMOS Cascode Amplifier The foregoing analysis of the bipolar cascode amplifier can readily be extended to the CMOS counterpart. Depicted in Fig. 9.20(a) with an ideal current-source load, this stage also provides a short-circuit transconductance Gm ≈ gm1 if 1/gm2 rO1 . The output resistance is given by Eq. (9.22), yielding a voltage gain of Av = −GmRout

(9.67)

≈ −gm1 [(1 + gm2rO2 )rO1 + rO2 ]

(9.68)

≈ −gm1rO1 gm2rO2 .

(9.69)

In other words, compared to a simple common-source stage, the voltage gain has risen by a factor of gm2rO2 (the intrinsic gain of the cascode device). Since β and rπ are infinite for MOS

VDD

VDD I1 v out V b1

V b2

M4

V b2

M3

R op

M2

V b1

M1

v in

X v in

M2 X

(a)

Figure 9.20

v out

R on

M1 (b)

(a) MOS cascode amplifier, (b) realization of load by a PMOS cascode.

374

Chapter 9 Cascode Stages and Current Mirrors devices (at low frequencies), we can also utilize Eq. (9.53) to arrive at Eq. (9.69). Note, however, that M1 and M2 need not exhibit equal transconductances or output resistances (their widths and lengths need not be the same) even though they carry equal currents (why?). As with the bipolar counterpart, the MOS cascode amplifier must incorporate a cascode PMOS current source so as to maintain a high voltage gain. Illustrated in Fig. 9.20(b), the circuit exhibits the following output impedance components: Ron ≈ gm2rO2rO1

(9.70)

Rop ≈ gm3rO3rO4 .

(9.71)

The voltage gain is therefore equal to Av ≈ −gm1 [(gm2rO2rO1 )||(gm3rO3rO4 )].

(9.72)

Example 9.11

The cascode amplifier of Fig. 9.20(b) incorporates the following device parameters: (W/L)1,2 = 30, (W/L)3,4 = 40, ID1 = · · · = ID4 = 0.5 mA. If μnCox = 100 μA/V2 , μ pC ox = 50 μA/V2 , λn = 0.1 V−1 and λ p = 0.15 V−1 , determine the voltage gain.

Solution

With the particular choice of device parameters here, gm1 = gm2 , rO1 = rO2 , gm3 = gm4 , and rO3 = rO4 . We have W ID1,2 (9.73) gm1,2 = 2μnCox L 1,2 = (577 )−1

(9.74)

gm3,4 = (707 )−1 .

(9.75)

and

Also, rO1,2 =

1 λn ID1,2

= 20 k

(9.76) (9.77)

and rO3,4 = 13.3 k.

(9.78)

Equations (9.70) and (9.71) thus respectively give Ron ≈ 693 k

(9.79)

Rop ≈ 250 k

(9.80)

Av = −gm1 (Ron ||Rop )

(9.81)

and

≈ −318. Exercise

(9.82)

Explain why a lower bias current results in a higher output impedance in the above example. Calculate the output impedance for a drain current of 0.25 mA.

9.2 Current Mirrors

9.2

375

CURRENT MIRRORS 9.2.1 Initial Thoughts The biasing techniques studied for bipolar and MOS amplifiers in Chapters 4 and 6 prove inadequate for high-performance microelectronic circuits. For example, the bias current of CE and CS stages is a function of the supply voltage—a serious issue because in practice, this voltage experiences some variation. The rechargeable battery in a cellphone or laptop computer, for example, gradually loses voltage as it is discharged, thereby mandating that the circuits operate properly across a range of supply voltages. Another critical issue in biasing relates to ambient temperature variations. A cellphone must maintain its performance at −20◦ C in Finland and +50◦ C in Saudi Arabia. To understand how temperature affects the biasing, consider the bipolar current source shown in Fig. 9.21(a), where R1 and R2 divide VCC down to the required VBE . That is, for a desired current I1 , we have R2 I1 VCC = VT ln , R1 + R 2 IS

(9.83)

where the base current is neglected. But, what happens if the temperature varies? The left-hand side remains constant if the resistors are made of the same material and hence vary by the same percentage. The right-hand side, however, contains two temperaturedependent parameters: VT = kT/q and IS . Thus, even if the base-emitter voltage remains constant with temperature, I1 does not. A similar situation arises in CMOS circuits. Illustrated in Fig. 9.21(b), a MOS current source biased by means of a resistive divider suffers from dependence on VDD and temperature. Here, we can write W 1 μnCox (VGS − VTH )2 2 L 2 1 W R2 = μnCox VDD − VTH . 2 L R1 + R 2

I1 =

(9.84)

(9.85)

Since both the mobility and the threshold voltage vary with temperature, I1 is not constant even if VGS is. In summary, the typical biasing schemes introduced in Chapters 4 and 6 fail to establish a constant collector or drain current if the supply voltage or the ambient temperature are subject to change. Fortunately, an elegant method of creating supply- and temperatureindependent voltages and currents exists and appears in almost all microelectronic systems. Called the “bandgap reference circuit” and employing several tens of devices, this scheme is studied in more advanced books [1].

VCC R1

VDD I1

R1

I1

Q1 R2

VBE (a)

Figure 9.21

R2

VGS

M1

(b)

Impractical biasing of (a) bipolar and (b) MOS current sources.

376

Chapter 9 Cascode Stages and Current Mirrors VCC I REF

I copy Current Mirror

Concept of current mirror.

Figure 9.22

The bandgap circuit by itself does not solve all of our problems! An integrated circuit may incorporate hundreds of current sources, e.g., as the load impedance of CE or CS stages to achieve a high gain. Unfortunately, the complexity of the bandgap prohibits its use for each current source in a large integrated circuit. Let us summarize our thoughts thus far. In order to avoid supply and temperature dependence, a bandgap reference can provide a “golden current” while requiring a few tens of devices. We must therefore seek a method of “copying” the golden current without duplicating the entire bandgap circuitry. Current mirrors serve this purpose. Figure 9.22 conceptually illustrates our goal here. The golden current generated by a bandgap reference is “read” by the current mirror and a copy having the same characteristics as those of IREF is produced. For example, Icopy = IREF or 2IREF .

9.2.2 Bipolar Current Mirror Since the current source generating Icopy in Fig. 9.22 must be implemented as a bipolar or MOS transistor, we surmise that the current mirror resembles the topology shown in Fig. 9.23(a), where Q 1 operates in the forward active region and the black box guarantees Icopy = IREF regardless of temperature or transistor characteristics. (The MOS counterpart is similar.) How should the black box of Fig. 9.23(a) be realized? The black box generates an output voltage, VX ( = VBE ), such that Q 1 carries a current equal to IREF : IS1 exp

VX = IREF , VT

(9.86)

where the Early effect is neglected. Thus, the black box satisfies the following relationship: VX = VT ln

VCC I REF X

(9.87)

VCC I copy

?

IREF . IS1

Q1

VCC

I REF

I copy

I REF V1

Q REF

Q REF

X

VBE (a)

(b)

Q 1 Current Mirror

(c)

Figure 9.23 (a) Conceptual illustration of current copying, (b) voltage proportional to natural logarithm of current, (c) bipolar current mirror.

9.2 Current Mirrors

377

We must therefore seek a circuit whose output voltage is proportional to the natural logarithm of its input, i.e., the inverse function of bipolar transistor characteristics. Fortunately, a single diode-connected device satisfies Eq. (9.87). Neglecting the base-current in Fig. 9.23(b), we have V1 = VT ln

IREF , IS,REF

(9.88)

where IS,REF denotes the reverse saturation current of QREF . In other words, V1 = VX if IS,REF = IS1 , i.e., if QREF is identical to Q 1 . Figure 9.23(c) consolidates our thoughts, displaying the current mirror circuitry. We say Q 1 “mirrors” or copies the current flowing through QREF . For now, we neglect the base currents. From one perspective, QREF takes the natural logarithm of IREF and Q 1 takes the exponential of VX , thereby yielding Icopy = IREF . From another perspective, since QREF and Q 1 have equal base-emitter voltages, we can write IREF = IS,REF exp Icopy = IS1 exp

VX VT

(9.89)

VX VT

(9.90)

IREF ,

(9.91)

and hence Icopy =

IS1 IS,REF

which reduces to Icopy = IREF if QREF and Q 1 are identical. This holds even though VT and IS vary with temperature. Note that VX does vary with temperature but in such a way that Icopy does not. Example 9.12

An electrical engineering student who is excited by the concept of the current mirror constructs the circuit but forgets to tie the base of QREF to its collector (Fig. 9.24). Explain what happens. VCC I REF Q REF

I copy ?

Q1

Figure 9.24

Solution

The circuit provides no path for the base currents of the transistors. More fundamentally, the base-emitter voltage of the devices is not defined. The lack of the base currents translates to Icopy = 0.

Exercise

What is the region of operation of QREF ?

378

Chapter 9 Cascode Stages and Current Mirrors

Example 9.13

Realizing the mistake in the above circuit, the student makes the modification shown in Fig. 9.25, hoping that the battery VX provides the base currents and defines the baseemitter voltage of QREF and Q 1 . Explain what happens. VCC

VCC I copy ?

I REF Q REF

Q1

I copy ?

I REF Q REF

Q1

VX

VX VX

Figure 9.25

Solution

While Q 1 now carries a finite current, the biasing of Q 1 is no different from that in Fig. 9.21; i.e., Icopy = IS1 exp

VX , VT

(9.92)

which is a function of temperature if VX is constant. The student has forgotten that a diode-connected device is necessary here to ensure that VX remains proportional to ln(IREF /IS,REF ). Exercise

Suppose VX is slightly greater than the necessary value, VT ln(IREF /IS,REF ). In what region does QREF operate?

We must now address two important questions. First, how do we make additional copies of IREF to feed different parts of an integrated circuit? Second, how do we obtain different values for these copies, e.g., 2IREF , 5IREF , etc.? Considering the topology in Fig. 9.22(c), we recognize that VX can serve as the base-emitter voltage of multiple transistors, thus arriving at the circuit shown in Fig. 9.26(a). The circuit is often drawn as in Fig. 9.26(b) for simplicity. Here, transistor Q j carries a current Icopy, j , given by VX , VT

(9.93)

IREF .

(9.94)

Icopy, j = IS, j exp which, along with Eq. (9.87), yields Icopy,j =

IS,j IS,REF

The key point here is that multiple copies of IREF can be generated with minimal additional complexity because IREF and QREF themselves need not be duplicated. Equation (9.94) readily answers the second question as well: If IS,j (∝ the emitter area of Q j ) is chosen to be n times IS,REF (∝ the emitter area of QREF ), then Icopy, j = nI REF . We say the copies are “scaled” with respect to IREF . Recall from Chapter 4 that this is equivalent to placing n unit transistors in parallel. Figure 9.26(c) depicts an example where Q 1 -Q 3 are identical to QREF , providing Icopy = 3IREF .

9.2 Current Mirrors

379

VCC I copy1

I REF Q REF

I copy2

Q1

Q2

I copy3

Q3

(a)

VCC

VCC I copy1

I REF Q1

I copy2 Q2

I copy3

I copy = 3 I REF

I REF

Q3

Q1

Q REF

Q2

Q3

Q REF (c)

(b)

Figure 9.26 (a) Multiple copies of a reference current, (b) simplified drawing of (a), (c) combining output currents to generate larger copies.

Example 9.14

A multistage amplifier incorporates two current sources of values 0.75 mA and 0.5 mA. Using a bandgap reference current of 0.25 mA, design the required current sources. Neglect the effect of the base current for now.

Solution

Figure 9.27 illustrates the circuit. Here, all transistors are identical to ensure proper scaling of IREF .

VCC I REF

0.75 mA

0.25 mA

Q1

Q2

Q3

Q REF

0.5 mA

Q4

Q5

Figure 9.27 Exercise

Repeat the above example if the bandgap reference current is 0.1 mA.

The use of multiple transistors in parallel provides an accurate means of scaling the reference in current mirrors. But, how do we create fractions of IREF ? This is accomplished by realizing QREF itself as multiple parallel transistors. Exemplified by the circuit in Fig. 9.28, the idea is to begin with a larger IS,REF (= 3IS here) so that a unit

380

Chapter 9 Cascode Stages and Current Mirrors VCC I REF

0.25 mA

I copy Q1

X Q REF1 Q REF2 Q REF3

Figure 9.28

Copying a fraction of a reference current.

transistor, Q 1 , can generate a smaller current. Repeating the expressions in Eqs. (9.89) and (9.90), we have IREF = 3IS exp

VX VT

(9.95)

VX VT

(9.96)

1 IREF . 3

(9.97)

Icopy = IS exp and hence Icopy =

Example 9.15

It is desired to generate two currents equal to 50 μA and 500 μA from a reference of 200 μA. Design the current mirror circuit.

Solution

To produce the smaller current, we must employ four unit transistors for QREF such that each carries 50 μA. A unit transistor thus generates 50 μA (Fig. 9.29). The current of 500 μA requires 10 unit transistors, denoted by 10AE for simplicity.

VCC I REF

0.2 mA

X

4A E

Q1

I copy1 AE

Q2

I copy2 10 A E

Figure 9.29 Exercise

Repeat the above example for a reference current of 150 μA.

Effect of Base Current We have thus far neglected the base current drawn from node X in Fig. 9.26(a) by all transistors, an effect leading to a significant error as the number

9.2 Current Mirrors

381

VCC I REF

AE

Figure 9.30

Q1

Q REF I copy

I copy

nβ

β

I copy nA E

Error due to base currents.

of copies (i.e., the total copied current) increases. The error arises because a fraction of IREF flows through the bases rather than through the collector of QREF . We analyze the error with the aid of the diagram shown in Fig. 9.30, where AE and nAE denote one unit transistor and n unit transistors, respectively. Our objective is to calculate Icopy , recognizing that QREF and Q 1 still have equal base-emitter voltages and hence carry currents with a ratio of n. Thus, the base currents of Q 1 and QREF can be expressed as IB1 = IB,REF =

Icopy β

(9.98)

Icopy 1 · . β n

(9.99)

Writing a KCL at X therefore yields IREF = IC,REF +

Icopy 1 Icopy · + , β n β

(9.100)

which, since IC,REF = Icopy /n, leads to Icopy =

nI REF . 1 1 + (n + 1) β

(9.101)

For a large β and moderate n, the second term in the denominator is much less than unity and Icopy ≈ nI REF . However, as the copied current (∝ n) increases, so does the error in Icopy . To suppress the above error, the bipolar current mirror can be modified as illustrated in Fig. 9.31. Here, emitter follower QF is interposed between the collector of QREF and node X, thereby reducing the effect of the base currents by a factor of β. More specifically,

VCC I REF

I B,F

P Q REF AE

Figure 9.31

I C,F QF X

I copy

I copy

nβ

β

Q1

I copy nA E

Addition of emitter follower to reduce error due to base currents.

382

Chapter 9 Cascode Stages and Current Mirrors assuming IC,F ≈ IE,F , we can repeat the above analysis by writing a KCL at X: IC,F = obtaining the base current of QF as IB,F

Icopy Icopy 1 + · , β β n

Icopy 1 . = 2 1+ β n

(9.102)

(9.103)

Another KCL at node P gives IREF = IB,F + IC,REF =

Icopy Icopy 1 1 + + 2 β n n

(9.104) (9.105)

and hence nI REF . 1 1 + 2 (n + 1) β ∗ That is, the error is lowered by a factor of β. Icopy =

(9.106)

Example 9.16

Compute the error in Icopy1 and Icopy2 in Fig. 9.29 before and after adding a follower.

Solution

Noting that Icopy1 , Icopy2 , and IC,REF (the total current flowing through four unit transistors) still retain their nominal ratios (why?), we write a KCL at X: IREF = IC,REF + = 4Icopy1 +

Icopy1 Icopy2 IC,REF + + β β β

(9.107)

10Icopy1 Icopy1 IC,REF + + . β β β

(9.108)

Thus, Icopy1 =

IREF 15 4+ β

Icopy2 =

10IREF . 15 4+ β

(9.109)

(9.110)

With the addition of emitter follower (Fig. 9.32), we have at X: Icopy1 Icopy2 IC,REF + + β β β

(9.111)

=

4Icopy1 Icopy1 10Icopy1 + + β β β

(9.112)

=

15Icopy1 . β

(9.113)

IC,F =

∗

In more advanced designs, a constant current is drawn from X.

9.2 Current Mirrors

I REF

383

VCC 0.2 mA

P

I copy1

QF Q 1

AE

X

I copy2

4A E

Q2

10 A E

Figure 9.32

A KCL at P therefore yields IREF = =

15Icopy1 + IC,REF β2

(9.114)

15Icopy1 + 4Icopy1 , β2

(9.115)

and hence

Exercise

Icopy1 =

IREF 15 4+ 2 β

Icopy2 =

10IREF . 15 4+ 2 β

(9.116)

(9.117)

Calculate Icopy1 if one of the four unit transistors is omitted, i.e., the reference transistor has an area of 3AE .

PNP Mirrors Consider the common-emitter stage shown in Fig. 9.33(a), where a current source serves as a load to achieve a high voltage gain. The current source can be realized as a pnp transistor operating in the active region [Fig. 9.33(b)]. We must therefore define the bias current of Q 2 properly. In analogy with the npn counterpart of Fig. 9.23(c), we form

Vb

I1

Q2

v out v in

Q1

(a)

VCC

VCC

VCC

Q REF

X

Q2

v out v in

Q1

(b)

v out I REF

v in

Q1

(c)

Figure 9.33 (a) CE stage with current-source load, (b) realization of current source by a pnp device, (c) proper biasing of Q 2 .

384

Chapter 9 Cascode Stages and Current Mirrors the pnp current mirror depicted in Fig. 9.33(c). For example, if QREF and Q 2 are identical and the base currents negligible, then Q 2 carries a current equal to IREF .

Example 9.17

Design the circuit of Fig. 9.33(c) for a voltage gain of 100 and a power budget of 2 mW. Assume VA,npn = 5 V, VA,pnp = 4 V, IREF = 100 μA, and VCC = 2.5 V.

Solution

From the power budget and VCC = 2.5 V, we obtain a total supply current of 800 μA, of which 100 μA is dedicated to IREF and QREF . Thus, Q 1 and Q 2 are biased at a current of 700 μA, requiring that the (emitter) area of Q 2 be 7 times that of QREF . (For example, QREF incorporates one unit device and Q 1 seven unit devices.) The voltage gain can be written as Av = −gm1 (rO1 ||rO2 ) =−

(9.118)

VA,npn VA,pnp 1 · VT VA,npn + VA,pnp

(9.119)

= −85.5.

(9.120)

What happened here?! We sought a gain of 100 but inevitably obtained a value of 85.5! This is because the gain of the stage is simply given by the Early voltages and VT , a fundamental constant of the technology and independent of the bias current. Thus, with the above choice of Early voltages, the circuit’s gain cannot reach 100. Exercise

What Early voltage is necessary for a voltage gain of 100?

We must now address an interesting problem. In the mirror of Fig. 9.23(c), it is assumed that the golden current flows from VCC to node X, whereas in Fig. 9.33(c) it flows from X to ground. How do we generate the latter from the former? It is possible to combine the npn and pnp mirrors for this purpose, as illustrated in Fig. 9.34. Assuming for simplicity that QREF1 , QM , QREF2 , and Q 2 are identical and neglecting the base currents, we observe that Q M draws a current of IREF from QREF2 , thereby forcing the same current through Q 2 and Q 1 . We can also create various scaling scenarios between QREF1 and QM and between Q REF2 and Q 2 . Note that the base currents introduce a cumulative error as IREF is copied onto IC,M , and IC,M onto IC 2 .

VCC I REF

Q REF2 I C,M

Q REF1

Figure 9.34

X1

X2 v in

QM

Generation of current for pnp devices.

Q2 v out Q1

9.2 Current Mirrors

385

Example 9.18

We wish to biasQ 1 andQ 2 in Fig. 9.34 at a collector current of 1 mA while IREF = 25 μA. Choose the scaling factors in the circuit so as to minimize the number of unit transistors.

Solution

For an overall scaling factor of 1 mA/25 μA = 40, we can choose either IC,M = 8IREF

(9.121)

|IC 2 | = 5IC,M

(9.122)

IC,M = 10IREF

(9.123)

|IC 2 | = 4IC,M .

(9.124)

or

(In each case, the npn and pnp scaling factors can be swapped.) In the former case, the four transistors in the current mirror circuitry require 15 units, and in the latter case, 16 units. Note that we have implicitly dismissed the case IC,M = 40IC,REF1 and IC 2 = IC,REF2 as it would necessitate 43 units. Exercise

Calculate the exact value of IC 2 if β = 50 for all transistors.

Example 9.19

An electrical engineering student purchases two nominally identical discrete bipolar transistors and constructs the current mirror shown in Fig. 9.23(c). Unfortunately, Icopy is 30% higher than IREF . Explain why.

Solution

It is possible that the two transistors were fabricated in different batches and hence underwent slightly different processing. Random variations during manufacturing may lead to changes in the device parameters and even the emitter area. As a result, the two transistors suffer from significant IS mismatch. This is why current mirrors are rarely used in discrete design.

Exercise

How much IS mismatch results in a 30% collector current mismatch?

9.2.3 MOS Current Mirror The developments in Section 9.2.2 can be applied to MOS current mirrors as well. In particular, drawing the MOS counterpart of Fig. 9.23(a) as in Fig. 9.35(a), we recognize that the black box must generate VX such that 1 W (VX − VTH1 )2 = IREF , (9.125) μnCox 2 L 1 where channel-length modulation is neglected. Thus, the black box must satisfy the following input (current)/output (voltage) characteristic:

2IREF

+ VTH1 . VX =

(9.126) W μnCox L 1

386

Chapter 9 Cascode Stages and Current Mirrors VDD I REF

VDD I copy1

?

X VGS

M1

VDD

I REF

I copy

I REF VX

M REF

(a)

M REF

(b)

X

M 1 Current Mirror

(c)

(a) Conceptual illustration of copying a current by an NMOS device, (b) generation of a voltage proportional to square root of current, (c) MOS current mirror.

Figure 9.35

That is, it must operate as a “square-root” circuit. From Chapter 6, we recall that a diode-connected MOSFET provides such a characteristic [Fig. 9.35(b)], thus arriving at the NMOS current mirror depicted in Fig. 9.35(c). As with the bipolar version, we can view the circuit’s operation from two perspectives: (1) MREF takes the square root of IREF and M1 squares the result; or (2) the drain currents of the two transistors can be expressed as W 1 ID,REF = μnCox (VX − VTH )2 (9.127) 2 L REF Icopy =

W 1 (VX − VTH )2 , μnCox 2 L 1

where the threshold voltages are assumed equal. It follows that W L Icopy = 1 IREF , W L REF

(9.128)

(9.129)

which reduces to Icopy = IREF if the two transistors are identical.

Example 9.20

The student working on the circuits in Examples 9.12 and 9.13 decides to try the MOS counterpart, thinking that the gate current is zero and hence leaving the gates floating (Fig. 9.36). Explain what happens.

VDD I copy ?

I REF M REF

X

Floating Node

Figure 9.36

M1

9.2 Current Mirrors

387

Solution

This circuit is not a current mirror because only a diode-connected device can establish Eq. (9.129) and hence a copy current independent of device parameters and temperature. Since the gates of MREF and M1 are floating, they can assume any voltage, e.g., an initial condition created at node X when the power supply is turned on. In other words, Icopy is very poorly defined.

Exercise

Is MREF always off in this circuit?

Generation of additional copies of IREF with different scaling factors also follows the principles shown in Fig. 9.26. The following example illustrates these concepts.

Example 9.21

An integrated circuit employs the source follower and the common-source stage shown in Fig. 9.37(a). Design a current mirror that produces I1 and I2 from a 0.3-mA reference. VDD V in1

VDD V in2

M1

M2

Vout1

Vout2

I1

0.2 mA

I2

0.5 mA (a)

VDD V in1

I REF W 3( ( L

M2

Vout1

Vout2

I1

0.3 mA

M REF

V in2

M1

VDD

VDD

I2

M I1 2(

M I2

W ( L

5(

W ( L

(b)

Figure 9.37

Solution

Following the methods depicted in Figs. 9.28 and 9.29, we select an aspect ratio of 3(W/L) for the diode-connected device, 2(W/L) for MI1 , and 5(W/L) for MI2 . Figure 9.37(b) shows the overall circuit.

Exercise

Repeat the above example if IREF = 0.8 mA.

Since MOS devices draw a negligible gate current,6 MOS mirrors need not resort to the technique shown in Fig. 9.31. On the other hand, channel-length modulation in the 6

◦

In deep-submicron CMOS technologies, the gate oxide thickness is reduced to less than 30 A, leading to “tunneling” and hence noticeable gate current. This effect is beyond the scope of this book.

388

Chapter 9 Cascode Stages and Current Mirrors CS Stage

VDD

Follower

Vout1 VDD

V in1

Vout2 V in2

I REF CS Stage VDD

Follower

M REF V in3

V in4 Vout3

Figure 9.38

Vout4

NMOS and PMOS current mirrors in a typical circuit.

current-source transistors does lead to additional errors. Investigated in Problem 9.43, this effect mandates circuit modifications that are described in more advanced texts [1]. The idea of combining NMOS and PMOS current mirrors follows the bipolar counterpart depicted in Fig. 9.34. The circuit of Fig. 9.38 exemplifies these ideas.

PROBLEMS 9.1. Determine output resistance (Rout ) of CC/ CB cascade circuit as shown in Fig. 9.39(a). R out

*9.3. Due to a manufacturing error, a parasitic resistor RP has appeared in the cascode circuits of Fig. 9.40. Determine the output resistance in each case.

Q2 R Q1

D

i1 R out V (a) Figure 9.39

9.2. In Fig. 9.39(b) show how o/p conductance is considerably reduced compared to that of single stage. Assume go for Q 1 ,Q 2 equal.

S D S (b)

Q2

Q1

9.4. Repeat Example 9.1 for the circuit shown in Fig. 9.41, assuming I1 is ideal and equal to 0.5 mA, i.e., IC 1 = 0.5 mA while IC 2 = 1 mA. 9.5. Suppose the circuit of Fig. 9.41 is realized as shown in Fig. 9.42, where Q 3 plays the role of I1 . Assuming VA1 = VA2 = VA,n and VA3 = VA, p , determine the output impedance of the circuit.

Problems R out V b1

Q1

R out

R out Q1

V b1

V b1

V b2

R out V b1

Q1

RP

Q2

(a)

V b2

Q2

V b2

(b)

Q1 RP

Q2

RP

389

RP

V b2

Q2

(c)

(d)

Figure 9.40

R out V b1

Q1

V b2

Q2

R out

VCC I1

Figure 9.41

V b1

Q1

V b2

Q2

VCC V b3

Q3

Figure 9.42

*9.6. While constructing a cascode stage, a student adventurously swaps the collector and base terminals of the degeneration transistor, arriving at the circuit shown in Fig. 9.43.

R out V b1

Q1

V b2

Q2

V bn

Qn

R out V b1 V b2

Q1

Q2

Figure 9.44

Figure 9.43

(a) Assuming both transistors operate in **9.8. Determine the output impedance of each circuit shown in Fig. 9.45. Assume β 1. the active region, determine the output Explain which ones are considered cascode impedance of the circuit. stages. (b) Compare the result with that of a cas* 9.9. The pnp cascode depicted in Fig. 9.46 must code stage for a given bias current (IC 1 ) provide a bias current of 0.5 mA to a circuit. and explain why this is generally not a −16 If I = 10 and β = 100, good idea. S *9.7. Excited by the output impedance “boosting” capability of cascodes, a student decides to extend the idea as illustrated in Fig. 9.44. What is the maximum output impedance that the student can achieve? Assume the transistors are identical.

(a) Calculate the required value of Vb2 . (b) Noting that VX = Vb1 + |VBE1 |, determine the maximum allowable value of Vb1 such that Q 2 experiences a base-collector forward bias of only 200 mV.

390

Chapter 9 Cascode Stages and Current Mirrors R out

R out R out

R out V b1

V b1 V b2

V b1

Q1 V b2

Q2

RB

(a)

Q1

Q2

(b)

VCC V b2

Q2

V b1

Q1

V b2

RP

Q2

(c)

VCC

RE

V b1

RB

Q2

RB

Q1

Q1

(d)

VCC

R out

Q2

I1

Vb

Q1

V b2

Q1

V b2

Q2

I1

R out

R out (e)

(g)

(f)

Figure 9.45

VCC = 2.5 V V b2

Q2

V b1

Q1

X

9.12. Design an NMOS-based cascode circuit as shown in Fig. 9.48 for the following specifications: Rout

Circuit

Vb1

0.5 mA

Vb2

Figure 9.46

9.10. Explain diode connected MOS (both NMOS and PMOS) as current sources. Fig. 9.47 shows NMOS current. Draw similarly PMOS current and explain. Vin I REF ID

M1 X I1 M2

I out

Vout

Figure 9.48

9.13. For Fig. 9.49, VG1 provides dc bias current of 75 μA. Find the value of VG2 that gives minimum o/p voltage. Also find voltage gain Vout /Vin .

RD = 25 k Ω

V G2

VDD Rout

Vout

M 2 12/1

X Figure 9.47

9.11. Explain PMOS as a cascaded current source, using circuit diagram and characteristic CMOS.

M 1 15/1

Vin V G1 Figure 9.49

Problems R out

R out

R out V b1

M1

V b1

RG M2 (a)

M1

V b1

M1 M3

M2

V b2

M2

(b)

391

R out V b3

V b1

M1 M2

(c)

(d)

Figure 9.50

**9.14. Compute the output resistance of the circuits depicted in Fig. 9.50. Assume all of the transistors operate in saturation and gmrO 1.

VDD

V b3

M3 I

9.15. For circuit of Fig. 9.51, find voltage gain, output resistance. Take W = 21 , λ = 0.05 for all L transistors, ID = 125 μA.

Vout

V b2

M2

V in

M1

Figure 9.51

Take

Kn = 100 μA/V 2 . K p = 50 μA/V 2 . 9.16. For Fig. 9.51, determine Vmax and Vmin output of cascode amplifier.

**9.17. Determine the output impedance of the stages shown in Fig. 9.52. Assume all of the transistors operate in saturation and of gmrO 1.

R out

R out VDD

V b1

RG

M1

V b1

M1

M2

V b2

M2

(a)

(b)

R out

VDD

V b3

M3

V b2

M2

V b1

M1 R out (c)

Figure 9.52

M3

V b1

M1

V b2

M2

V b3

M3 (d)

V b3

392

Chapter 9 Cascode Stages and Current Mirrors VDD Vb

V in

M2

Vb

(a)

V in

Vout Vb

Q1

RE (d)

VDD

VCC

RE V in

RE

M2

Vout

V in

Q2

Vout

V b1

M1

RS

Q1

(c)

VDD M2

Q2

RE

RE

M1

V in

Q2

M1

(b)

V b2

VCC

Vout Vout

M1

V in

Vb

M2

Vout V in

VCC

VDD

Vout

V b1

RC

RS

(e)

(f)

(g)

Figure 9.53

9.18. Compute the short-circuit transconductance and the voltage gain of each of the stages in Fig. 9.53. Assume λ > 0 and VA < ∞. *9.19. Prove that Eq. (9.53) reduces to Av ≈

−βVA2 , VT (VA + βVT )

(9.130)

a quantity independent of the bias current. 9.20. For Fig. 9.54, biased at 2 mA, and if VCC = 6 V, β = 125 for Q 1 and Q 2 , find voltage gain. Load is considered as ideal current source. VCC I1 Vb1

Q2

Vout

λ p = 0.14 V−1 . 0.6 mA, λn = 0.1 V−1 , 2 μnC ox = 100 μA/V , μ pC ox = 50 MA/V2 .

Vb2

VDD M4

Vb2

M3

ROP

Vout

RON

Vb1

M2 X

Vin

M1

Figure 9.55

**9.22. Calculate the voltage gain of each stage illustrated in Fig. 9.56.

*9.23. Due to a manufacturing error, a bipolar cascode amplifier has been configured as shown in Fig. 9.57. Determine the voltage gain of the circuit. Figure 9.54 9.24. Writing gm = 2μnCox (W/L)ID and rO = 1/(λID ), express Eq. (9.72) in terms of the 9.21. For Fig. 9.55, determine voltage gain. The device parameters and plot the result as a given specifications are, (W/L)1,2 = 40, function of ID . (W/L)3,4 = 50, ID1 = ID2 = ID3 = ID4 = Vin

Q1

Problems VCC

VCC

I1

VCC

I1

V b1

Q1

Q1

V b1

RP

RP V in

V in

Q2

(a)

VCC

I1

I1

Vout

Vout

Vout V b1

Q1

V in

Q2

Q2

Vout

RE

(b)

393

V b1

Q1

V in

Q2

(c)

VCC V b3

Q3

(d)

Figure 9.56

9.27. In the cascode stage of Fig. 9.20(b), (W/L)1 = · · · = (W/L)4 = 20/0.18. If μnCox = 100 μA/V2 , and μ pCox = 50 μA/V2 , λn = 0.1 V−1 , and λ p = 0.15 V−1 , calculate the bias current such that the circuit achieves a voltage gain of 500.

VCC Q4 V b2

Q3 v out

V b1

Q2

v in

Q1

9.28. Due to a manufacturing error, a CMOS cascode amplifier has been configured as shown in Fig. 9.58. Calculate the voltage gain of the circuit.

Figure 9.57 VDD

9.25. The MOS cascode of Fig. 9.20(a) must provide a voltage gain of 200 with a bias current of 1 mA. If μnCox = 100 μA/V2 and λ = 0.1 V−1 for both transistors, determine the required value of (W/L)1 = (W/L)2 .

V

V b4

M4

V b3

M3

V b2

M2

Vout

in

*9.26. The MOS cascode of Fig. 9.20(a) is designed V b1 M1 for a given voltage gain, Av . Using Eq. (9.79) and the result obtained in Problem 9.28, exFigure 9.58 plain what happens if the widths of the transistors are increased by a factor of N while the transistor lengths and bias currents re- **9.29. Determine the voltage gain of each circuit in Fig. 9.59. Assume gmrO 1. main unchanged. VDD

VDD

V b4

M4

V b4

M4

V b3

M3

V b3

M3

M2

V in

M5

Vout

V b2

RP M1

(a)

Figure 9.59

VDD V in

M4

V b4

M4

V b3

M3

V b3

M3

Vout V b2 V in

M1

(b)

Vout V b2

M2 RP

VDD

V b4

Vout

M2

V b1

M1

(c)

V in

M5

V b2

M2

V b1

M1

(d)

394

Chapter 9 Cascode Stages and Current Mirrors

*9.30. From Eq. (9.83), determine the sensitivity of *9.34. Repeat Problem 9.33 for the circuit shown I1 to VCC , defined as ∂I1 /∂VCC . Explain inin Fig. 9.62, but assuming that I1 is twice its tuitively why this sensitivity is proportional nominal value. to the transconductance of Q 1 . 9.31. The parameters μnCox and VTH in Eq. (9.85) also vary with the fabrication process. (Integrated circuits fabricated in different batches exhibit slightly different parameters.) Determine the sensitivity of I1 to VTH and explain why this issue becomes more serious at low supply voltages.

VCC I REF Q REF

R1

V REF

Figure 9.62

9.35. Derive expression for output resistance of current mirror of Fig. 9.62 (use small signal model). * 9.36. Repeat Problem 9.35 for the circuit shown in Fig. 9.63, but assuming I1 is 10% less than its nominal value.

IX Q2

V1

Q1 RP

9.32. Having learned about the logarithmic function of the circuit in Fig. 9.23(b), a student remembers the logarithmic amplifier studied in Chapter 8 and constructs the circuit depicted in Fig. 9.60. Explain what happens.

Q1

I1

VCC I REF

I1

Figure 9.60 Q REF

9.33. Find output current IC 2 for Fig. 9.61 for β = 75, Early voltage VEA = 50V.

IREF

VCC 10 V 50 k Ω

R

9.37. Taking base currents into account, determine the value of Icopy in each circuit depicted in Fig. 9.64. Normalize the error to the nominal value of Icopy .

IC2

Q1 VCE1

IB1

IB2

Q1

Figure 9.63

VCC 10 V

IC1

RP

9.38. Determine the error in Icopy1 and Icopy2 for the circuit as shown in Fig. 9.65.

Q2 VCE2

9.39. Determine Icopy1 and Icopy2 error values for Fig. 9.66.

Figure 9.61 VCC

VCC

I REF Q1 AE

I copy 5A E

Q REF (a)

Figure 9.64

VCC

I REF Q1

I copy AE

5A E

Q REF (b)

I REF Q1 2A E

I copy 3A E

Q REF (c)

Q2

I2 5A E

Problems

395

VCC IREF

0.2 mA X

2AE

VCC

I copy1

IREF

Q 1 AE

0.2 mA

P

QF X

Icopy 2

Q1

Icopy1 AE

Icopy2

Q2 6AE

2AE

Figure 9.65

6AE

Figure 9.66

9.40. Refer to Fig. 9.67. What should be (W/L)1 to generate I REF of 2 mA? Take VDD = 3 V VTh1 = 0.4 V kn = 20 μA/V2 R = 1 k. VDD

(b) Determine the error in Icopy1 with respect to IREF if VDS1 is equal to VGS − VTH (so that M1 resides at the edge of saturation). Design Problems

I REF R

IO

Q1

Q2

In the following problems, unless otherwise stated, assume IS,n = IS, p = 6 × 10−16 A, VA,n = VA, p = 5 V, βn = 100, β p = 50, μnCox = 100 μA/V2 , μ pCox = 50 μA/V2 , VTH,n = 0.4 V, and VTH, p = −0.5 V, where the subscripts n and p refer to n-type (npn or NMOS) and p-type (pnp or PMOS) devices, respectively.

Figure 9.67

9.41. For Fig. 9.67, what should be the ratio (W/L)2 to generate output current I0 = 10 mA? 9.42. For Fig. 9.68, design the circuit to obtain source current I5 = 12 mA.

9.44. Assuming a bias current of 1 mA, design the degenerated current source of Fig. 9.69(a) such that RE sustains a voltage approximately equal to the minimum required collector-emitter voltage of Q 2 in Fig. 9.69(b) (≈ 0.5 V). Compare the output impedances of the two circuits. R out

R

IREF

Q4 I4 I2

Q1

Q2

Q5 I5

Vb

Q1 RE

I3 Q3

Figure 9.68

**9.43. Consider the MOS current mirror shown in Fig. 9.35(c) and assume M1 and M2 are identical but λ = 0. (a) How should VDS1 be chosen so that Icopy1 is exactly equal to IREF ?

(a)

R out V b1

Q1

V b2

Q2 (b)

Figure 9.69

9.45. We wish to design the MOS cascode of Fig. 9.70 for an output impedance of 200 k and a bias current of 0.5 mA. (a) Determine (W/L)1 = (W/L)2 if λ = 0.1 V−1 . (b) Calculate the required value of Vb2 .

396

Chapter 9 Cascode Stages and Current Mirrors R out V b1

M1

V b2

M2

and λ p = 2λn = 0.2 V−1 . Determine the required dc levels of Vin and Vb3 . For simplicity, assume Vb1 = Vb2 = 0.9 V.

Figure 9.70

9.46. The bipolar cascode amplifier of Fig. 9.71 must be designed for a voltage gain of 500. Use Eq. (9.53) and assume β = 100. (a) What is the minimum required value of VA ? (b) For a bias current of 0.5 mA, calculate the required bias component in Vin . (c) Compute the value of Vb1 such that Q 1 sustains a collector-emitter voltage of 500 mV. VCC I1

VDD

V b3

M4

V b2

M3

V b1

M2

V in

M1

Figure 9.73

9.49. The current mirror shown in Fig. 9.74 must deliver I1 = 0.5 mA to a circuit with a total power budget of 2 mW. Assuming VA = ∞ and β 1, determine the required value of IREF and the relative sizes of QREF and Q 1 . VCC = 2.5 V

Vout

V b1

Q2

V in

Q1

Vout

Circuit

I REF I1 Q REF

Q1

Figure 9.71

9.47. Design the cascode amplifier shown in Fig. 9.72 for a power budget of 2 mW. Select Vb1 and Vb2 such that Q 1 and Q 4 sustain a base-collector forward bias of 200 mV. What voltage gain is achieved? VCC = 2.5 V V b3

Q4

V b2

Q3 Q2

V in

Q1

9.50. In the circuit of Fig. 9.75, Q 2 operates as an emitter follower. Design the circuit for a power budget of 3 mW and an output impedance of 50 . Assume VA = ∞ and β 1. VCC = 2.5 V V in

Vout V b1

Figure 9.74

Q2

I REF Q REF

Vout Q1

Figure 9.75 Figure 9.72

9.48. Design the CMOS cascode amplifier of Fig. 9.73 for a voltage gain of 200 and a power budget of 2 mW with VDD = 1.8 V. Assume (W/L)1 = · · · = (W/L)4 = 20/0.18

9.51. In the circuit of Fig. 9.76, Q 2 operates as a common-base stage. Design the circuit for an output impedance of 500 , a voltage gain of 20, and a power budget of 3 mW. Assume VA = ∞ and β 1.

Spice Problems VCC = 2.5 V RC I REF

Vout Vb

Q2 V in

Q REF

397

9.54. The source follower of Fig. 9.79 must achieve a voltage gain of 0.85 and an output impedance of 100 . Assuming (W/L)2 = 10/0.18, λn = 0.1 V−1 , and λ p = 0.2 V−1 , design the circuit.

Q1

VDD = 1.8 V

Figure 9.76

I REF

V in

M1 Vout

9.52. Figure 9.77 shows an arrangement where M1 and M2 serve as current sources for circuits 1 and 2. Design the circuit for a power budget of 3 mW. VDD = 1.8 V Circuit 1

Circuit 2

I REF 0.5 mA

M REF

1 mA

M1

M2

Figure 9.77

M REF

M2

Figure 9.79

9.55. The common-gate stage of Fig. 9.80 employs the current source M3 as the load to achieve a high voltage gain. For simplicity, neglect channel-length modulation in M1 . Assuming (W/L)3 = 40/0.18, λn = 0.1 V−1 , and λ p = 0.2 V−1 , design the circuit for a voltage gain of 20, an input impedance of 50 , and a power budget of 13 mW. (You may not need all of the power budget.)

9.53. The common-source stage depicted in Fig. 9.78 must be designed for a voltage gain of 20 and a power budget of 2 mW. Assuming (W/L)1 = 20/0.18, λn = 0.1 V−1 , and λ p = 0.2 V−1 , design the circuit.

VDD = 1.8 V M4

M3 Vout

VDD = 1.8 V M REF I REF

V in

M2

I REF

M1

M REF

Figure 9.78

Vb

M1 V in M5

M2

Figure 9.80

SPICE PROBLEMS In the following problems, use the MOS device models given in Appendix A. For bipolar transistors, assume IS,npn = 5 × 10−16 A, βnpn = 100, VA,npn = 5 V, IS,pnp = 8 × 10−16 A, βpnp = 50, VA,pnp = 3.5 V.

9.1. In the circuit of Fig. 9.81, we wish to suppress the error due to the base currents by means of resistor RP . (a) Tying the collector of Q 2 to VCC , select the value of RP so as to minimize the error between I1 and IREF .

398

Chapter 9 Cascode Stages and Current Mirrors (b) What is the change in the error if the β of both transistors varies by ±3%? (c) What is the change in the error if RP changes by ±10%? VCC = 2.5 V I REF

1 mA

Q REF

RP

I1 Q1

Figure 9.81

9.2. Repeat Problem 9.1 for the circuit shown in Fig. 9.82. Which circuit exhibits less sensitivity to variations in β and RP ? VCC = 2.5 V I REF

1 mA

Q REF

VDD = 1.8 V I out

0.5 mA

Vb

I1 Q1

RP

9.3. Figure 9.83 depicts a cascode current source whose value is defined by the mirror arrangement, M1 -M2 . Assume W/L = 5 μm/ 0.18 μm for M1 -M3 . (a) Select the value of Vb so that Iout is precisely equal to 0.5 mA. (b) Determine the change in Iout if Vb varies by ±100 mV. Explain the cause of this change. (c) Using both hand analysis and SPICE simulations, determine the output impedance of the cascode and compare the results.

M3 M2

M1

Figure 9.83

Figure 9.82

REFERENCE 1. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.

Chapter

10

Differential Amplifiers

The elegant concept of “differential” signals and amplifiers was invented in the 1940s and first utilized in vacuum-tube circuits. Since then, differential circuits have found increasingly wider usage in microelectronics and serve as a robust, high-performance design paradigm in many of today’s systems. This chapter describes bipolar and MOS differential amplifiers and formulates their large-signal and small-signal properties. The concepts are outlined below.

General Considerations • Differential Signals • Differential Pair

10.1

➤

Bipolar Differential Pair • Qualitative Analysis

➤

MOS Differential Pair • Qualitative Analysis

• Large-Signal Analysis

• Large-Signal Analysis

• Small-Signal Analysis

• Small-Signal Analysis

Other Concepts

➤

• Cascode Pair • Common-Mode Rejection • Pair with Active Load

GENERAL CONSIDERATIONS 10.1.1 Initial Thoughts We have already seen that op amps have two inputs, a point of contrast to the amplifiers studied in previous chapters. In order to further understand the need for differential circuits, let us first consider an example.

Example 10.1

Having learned the design of rectifiers and basic amplifier stages, an electrical engineering student constructs the circuit shown in Fig. 10.1(a) to amplify the signal produced by a microphone. Unfortunately, upon applying the result to a speaker, the student observes that the amplifier output contains a strong “humming” noise, i.e., a steady low-frequency component. Explain what happens.

399

400

Chapter 10 Differential Amplifiers

Solution

Recall from Chapter 3 that the current drawn from the rectified output creates a ripple waveform at twice the ac line frequency (50 or 60 Hz) [Fig. 10.1(b)]. Examining the output of the common-emitter stage, we can identify two components: (1) the amplified version of the microphone signal and (2) the ripple waveform present on VCC . For the latter, we can write Vout = VCC − RC IC ,

(10.1)

noting that Vout simply “tracks” VCC and hence contains the ripple in its entirety. The “hum” originates from the ripple. Figure 10.1(c) depicts the overall output in the presence of both the signal and the ripple. Illustrated in Fig. 10.1(d), this phenomenon is summarized as the “supply noise goes to the output with a gain of unity.” (A MOS implementation would suffer from the same problem.)

VCC To Bias

110 V 60 Hz

RC Vout Q1

C1 (a)

VCC Voice Signal

VCC

Ripple

Vout Signal

t (b)

t (c)

(d)

Figure 10.1 (a) CE stage powered by a rectifier, (b) ripple on supply voltage, (c) effect at output, (d) ripple and signal paths to output.

Exercise

What is the hum frequency for a full-wave rectifier or a half-wave rectifier?

How should we suppress the hum in the above example? We can increase C1 , thus lowering the ripple amplitude, but the required capacitor value may become prohibitively large if many circuits draw current from the rectifier. Alternatively, we can modify the amplifier topology such that the output is insensitive to VCC . How is that possible? Equation (10.1) implies that a change in VCC directly appears in Vout , fundamentally because both Vout and VCC are measured with respect to ground and differ by RC IC . But what if Vout is not “referenced” to ground?! More specifically, what if Vout is measured with respect to another point that itself experiences the supply ripple to the same extent? It is thus possible to eliminate the ripple from the “net” output. While rather abstract, the above conjecture can be readily implemented. Figure 10.2(a) illustrates the core concept. The CE stage is duplicated on the right, and the output is now measured between nodes X and Y rather than from X to ground. What happens if VCC contains ripple? Both VX and VY rise and fall by the same amount and hence the difference between VX and VY remains free from the ripple.

10.1 General Considerations VCC

VCC

Ripple

Ripple

R C1 To Bias

v in

R C1

R C2 X

Vout

Q1

Y

R C2 X

Y

Q1

Q2

To Bias

Q2

(a)

Figure 10.2

401

A1

(b)

Use of two CE stages to remove effect of ripple.

In fact, denoting the ripple by vr , we express the small-signal voltages at these nodes as vX = Av vin + vr

(10.2)

vY = vr .

(10.3)

vX − vY = Av vin .

(10.4)

That is,

Note that Q 2 carries no signal, simply serving as a constant current source. The above development serves as the foundation for differential amplifiers: the symmetric CE stages provide two output nodes whose voltage difference remains free from the supply ripple.

10.1.2 Differential Signals Let us return to the circuit of Fig. 10.2(a) and recall that the duplicate stage consisting of Q 2 and RC 2 remains “idle,” thereby “wasting” current. We may therefore wonder if this stage can provide signal amplification in addition to establishing a reference point for Vout . In our first attempt, we directly apply the input signal to the base of Q 2 [Fig. 10.3(a)]. Unfortunately, the signal components at X and Y are in phase, canceling each other as they appear in vX − vY : vX = Av vin + vr

(10.5)

vY = Av vin + vr

(10.6)

⇒ vX − vY = 0.

(10.7)

For the signal components to enhance each other at the output, we can invert one of the input phases as shown in Fig. 10.3(b), obtaining vX = Av vin + vr

(10.8)

vY = −Av vin + vr

(10.9)

vX − vY = 2Av vin .

(10.10)

and hence

402

Chapter 10 Differential Amplifiers Vr

VCC

R C1 To Bias

VCC R C1

R C2 X

Y

Q1

Q2

To Bias + v in

R C2 X

Y

Q1

Q2

– v in

V in (a)

(b)

(c)

Figure 10.3 (a) Application of one input signal to two CE stages, (b) use of differential input signals, (c) generation of differential phases from one signal.

Compared to the circuit of Fig. 10.2(a), this topology provides twice the output swing by exploiting the amplification capability of the duplicate stage. The reader may wonder how −vin can be generated. Illustrated in Fig. 10.3(c), a simple approach is to utilize a transformer to convert the microphone signal to two components bearing a phase difference of 180◦ . Our thought process has led us to the specific waveforms in Fig. 10.3(b): the circuit senses two inputs that vary by equal and opposite amounts and generates two outputs that behave in a similar fashion. These waveforms are examples of “differential” signals and stand in contrast to “single-ended” signals—the type to which we are accustomed from basic circuits and previous chapters of this book. More specifically, a single-ended signal is one measured with respect to the common ground [Fig. 10.4(a)] and “carried by one line,” whereas a differential signal is measured between two nodes that have equal and opposite swings [Fig. 10.4(b)] and is thus “carried by two lines.” Figure 10.4(c) summarizes the foregoing development. Here, V1 and V2 vary by equal and opposite amounts and have the same average (dc) level, VCM , with respect to ground: V1 = V0 sin ωt + VCM

(10.11)

V2 = −V0 sin ωt + VCM.

(10.12)

Since each of V1 and V2 has a peak-to-peak swing of 2V0 , we say the “differential swing” is 4V0 . We may also say V1 and V2 are differential signals to emphasize that they vary by equal and opposite amounts around a fixed level, VCM . The dc voltage that is common to both V1 and V2 [VCM in Fig. 10.4(c)] is called the “common-mode (CM) level.” That is, in the absence of differential signals, the two nodes remain at a potential equal to VCM with respect to the global ground. For example, in the transformer of Fig. 10.3(c), +vin and −vin display a CM level of zero because the center tap of the transformer is grounded. Example 10.2

How can the transformer of Fig. 10.3(c) produce an output CM level equal to +2 V?

10.1 General Considerations

403

VCC

Vin

Vout

Q1

(a)

VCC

Q1

Q2

V1 Output Differential Signal

VCM

2V0

V2

Input Differential Signal

t (c)

(b)

Figure 10.4

(a) Single-ended signals, (b) differential signals, (c) illustration of common-

mode level.

Solution

The center tap can simply be tied to a voltage equal to +2 V (Fig. 10.5).

v in1 v in1 2V

v in2

+2 V

v in2 t

Figure 10.5

Exercise

Does the CM level change if the inputs of the amplifier draw a bias current?

Example 10.3

Determine the common-mode level at the output of the circuit shown in Fig. 10.3(b).

Solution

In the absence of signals, VX = VY = VCC − RC IC (with respect to ground), where RC = RC 1 = RC 2 and IC denotes the bias current ofQ 1 andQ 2 . Thus, VCM = VCC − RC IC . Interestingly, the ripple affects VCM but not the differential output.

Exercise

If a resistor of value R1 is inserted between VCC and the top terminals of RC 1 and RC 2 , what is the output CM level?

404

Chapter 10 Differential Amplifiers Our observations regarding supply ripple and the use of the “duplicate stage” provide sufficient justification for studying differential signals. But, how about the common-mode level? What is the significance of VCM = VCC − RC IC in the above example? Why is it interesting that the ripple appears in VCM but not in the differential output? We will answer these important questions in the following sections. 10.1.3 Differential Pair Before formally introducing the differential pair, we must recognize that the circuit of Fig. 10.4(b) senses two inputs and can therefore serve as A1 in Fig. 10.2(b). This observation leads to the differential pair. While sensing and producing differential signals, the circuit of Fig. 10.4(b) suffers from some drawbacks. Fortunately, a simple modification yields an elegant, versatile topology. Illustrated in Fig. 10.6(a), the (bipolar) “differential pair”1 is similar to the circuit of Fig. 10.4(b), except that the emitters of Q 1 and Q 2 are tied to a constant current source rather than to ground. We call IEE the “tail current source.” The MOS counterpart is shown in Fig. 10.6(b). In both cases, the sum of the transistor currents is equal to the tail current. Our objective is to analyze the large-signal and small-signal behavior of these circuits and demonstrate their advantages over the “single-ended” stages studied in previous chapters. VCC RC

RD

RC

X V in1

VDD

Y Q1

Q2

RD

X Vin2

V in1

Y M2

M1

I SS

I EE (a)

Figure 10.6

Vin2

(b)

(a) Bipolar and (b) MOS differential pairs.

For each differential pair, we begin with a qualitative, intuitive analysis and subsequently formulate the large-signal and small-signal behavior. We also assume each circuit is perfectly symmetric, i.e., the transistors are identical and so are the resistors.

10.2

BIPOLAR DIFFERENTIAL PAIR 10.2.1 Qualitative Analysis It is instructive to first examine the bias conditions of the circuit. Recall from Section 10.1.2 that in the absence of signals, differential nodes reside at the common-mode level. We therefore draw the pair as shown in Fig. 10.7, with the two inputs tied to VCM to indicate no signal exists at the input. By virtue of symmetry, VBE1 = VBE2 IC 1 = IC 2 = 1

(10.13) IEE , 2

Also called the “emitter-coupled pair” or the “long-tailed pair.”

(10.14)

10.2 Bipolar Differential Pair

405

VCC R C1

R C2

X

Y Q1

Q2

V CM I EE

Figure 10.7

R C1 = R C2 = R C

Response of differential pair to input CM change.

where the collector and emitter currents are assumed equal. We say the circuit is in “equilibrium.” Thus, the voltage drop across each load resistor is equal to RC IEE /2 and hence IEE . (10.15) 2 In other words, if the two input voltages are equal, so are the two outputs. We say a zero differential input produces a zero differential output. The circuit also “rejects” the effect of supply ripple: if VCC experiences a change, the differential output, VX − VY , does not. Are Q 1 and Q 2 in the active region? To avoid saturation, the collector voltages must not fall below the base voltages: VX = VY = VCC − RC

VCC − RC

IEE ≥ VCM , 2

(10.16)

revealing that VCM cannot be arbitrarily high.

Example 10.4

A bipolar differential pair employs a load resistance of 1 k and a tail current of 1 mA. How close to VCC can VCM be chosen?

Solution

Equation 10.16 gives IEE 2

(10.17)

≥ 0.5 V.

(10.18)

VCC − VCM ≥ RC

That is, VCM must remain below VCC by at least 0.5 V. Exercise

What value of RC allows the input CM level to approach VCC if the transistors can tolerate a base-collector forward bias of 400 mV?

Now, let us vary VCM in Fig. 10.7 by a small amount and determine the circuit’s response. Interestingly, Eqs. (10.13)–(10.15) remain unchanged, thereby suggesting that neither the collector current nor the collector voltage of the transistors is affected. We say the circuit

406

Chapter 10 Differential Amplifiers VCC R C I EE 2

Upper Limit of VCM to Avoid Saturation

VX , VY

VCM1 VCM2

Figure 10.8

Effect of VCM1 and VCM2 at output.

does not respond to changes in the input common-mode level, or the circuit “rejects” input CM variations. Figure 10.8 summarizes these results. The “common-mode rejection” capability of the differential pair distinctly sets it apart from our original circuit in Fig. 10.4(b). In the latter, if the base voltage of Q 1 and Q 2 changes, so do their collector currents and voltages (why?). The reader may recognize that it is the tail current source in the differential pair that guarantees constant collector currents and hence rejection of the input CM level. With our treatment of the common-mode response, we now turn to the more interesting case of differential response. We hold one input constant, vary the other, and examine the currents flowing in the two transistors. While not exactly differential, such input signals provide a simple, intuitive starting point. Recall that IC 1 + IC 2 = IEE . Consider the circuit shown in Fig. 10.9(a), where the two transistors are drawn with a vertical offset to emphasize thatQ 1 senses a more positive base voltage. Since the difference between the base voltages of Q 1 and Q 2 is so large, we postulate that Q 1 “hogs” all of the tail current, thereby turning Q 2 off. That is, IC 1 = IEE

(10.19)

IC 2 = 0,

(10.20)

VX = VCC − RC IEE

(10.21)

VY = VCC .

(10.22)

and hence

VCC = 2.5 V RC

RC

RC

RC

Vout

X V in1 = +2 V

VCC = 2.5 V

Vout Y

Q1 Q2 P

X Vin2 = +1 V

V in1 = +1 V

Vin2 = +2 V

Q1 P

I EE (a)

Y Q2

I EE (b)

Response of bipolar differential pair to (a) large positive input difference and (b) large negative input difference.

Figure 10.9

10.2 Bipolar Differential Pair

407

But, how can we prove that Q 1 indeed absorbs all of IEE ? Let us assume that it is not so; i.e., IC 1 < IEE and IC 2 = 0. If Q 2 carries an appreciable current, then its base-emitter voltage must reach a typical value of, say, 0.8 V. With its base held at +1 V, the device therefore requires an emitter voltage of VP ≈ 0.2 V. However, this means that Q 1 sustains a base-emitter voltage of Vin1 − VP = +2 V − 0.2 V = 1.8 V!! Since with VBE = 1.8 V, a typical transistor carries an enormous current, and since IC 1 cannot exceed IEE , we conclude that the conditions VBE1 = 1.8 V and VP ≈ 0.2 V cannot occur. In fact, with a typical baseemitter voltage of 0.8 V, Q 1 holds node P at approximately +1.2 V, ensuring that Q 2 remains off. Symmetry of the circuit implies that swapping the base voltages of Q 1 and Q 2 reverses the situation [Fig. 10.9(b)], giving IC 2 = IEE

(10.23)

IC 1 = 0,

(10.24)

VY = VCC − RC IEE

(10.25)

VX = VCC .

(10.26)

and hence

The above experiments reveal that, as the difference between the two inputs departs from zero, the differential pair “steers” the tail current from one transistor to the other. In fact, based on Eqs. (10.14), (10.19), and (10.23), we can sketch the collector currents of Q 1 and Q 2 as a function of the input difference [Fig. 10.10(a)]. We have not yet formulated these characteristics but we do observe that the collector current of each transistor goes from 0 to IEE if |Vin1 − Vin2 | becomes sufficiently large. It is also important to note that VX and VY vary differentially in response to Vin1 − Vin2 . From Eqs. (10.15), (10.21), and (10.25), we can sketch the input/output characteristics of the circuit as shown in Fig. 10.10(b). That is, a nonzero differential input yields a nonzero differential output—a behavior in sharp contrast to the CM response. Since VX and VY are differential, we can define a common-mode level for them. Given by VCC − RC IEE /2, this quantity is called the “output CM level.”

Q2 Q1

Q1

Q1

Q2

Q2 I EE

I C2

I EE

0 (a)

Figure 10.10

VY

2

I C1

VCC I EE VCC – R C 2 VCC – R C I EE

VX

V in1 – V in2

V in1 – V in2

(b)

Variation of (a) collector currents and (b) output voltages as a function of input.

408

Chapter 10 Differential Amplifiers

Example 10.5

A bipolar differential pair employs a tail current of 0.5 mA and a collector resistance of 1 k. What is the maximum allowable base voltage if the differential input is large enough to completely steer the tail current? Assume VCC = 2.5 V.

Solution

If IEE is completely steered, the transistor carrying the current lowers its collector voltage to VCC − RC IEE = 2 V. Thus, the base voltage must remain below this value so as to avoid saturation.

Exercise

Repeat the above example if the tail current is raised to 1 mA. In the last step of our qualitative analysis, we “zoom in” around Vin1 − Vin2 = 0 (the equilibrium condition) and study the circuit’s behavior for a small input difference. As illustrated in Fig. 10.11(a), the base voltage of Q 1 is raised from VCM by V while that of Q 2 is lowered from VCM by the same amount. We surmise that IC 1 increases slightly and, since IC 1 + IC 2 = IEE , IC 2 decreases by the same amount: IEE + I 2 IEE − I. = 2

IC 1 =

(10.27)

IC 2

(10.28)

How is I related to V? If the emitters of Q 1 and Q 2 were directly tied to ground, then I would simply be equal to gmV. In the differential pair, however, node P is free to rise or fall. We must therefore compute the change in VP . Suppose, as shown in Fig. 10.11(b), VP rises by VP . As a result, the net increase in VBE1 is equal to V − VP and hence IC 1 = gm(V − VP ).

(10.29)

Similarly, the net decrease in VBE2 is equal to V + VP , yielding IC 2 = −gm(V + VP ).

(10.30)

But recall from Eqs. (10.27) and (10.28) that IC 1 must be equal to −IC 2 , dictating that gm(V − VP ) = gm(V + VP )

(10.31)

VCC RC

VCM

+ ΔV

RC

X

Y Q1

Q2

P

VCM

– ΔV

VCM

+ ΔV

X

Y

Q1

ΔVP

P

I EE (a)

Figure 10.11

change at P.

VCM

Q2 I EE

(b)

(a) Differential pair sensing small, differential input changes, (b) hypothetical

– ΔV

10.2 Bipolar Differential Pair

409

and hence VP = 0.

(10.32)

Interestingly, the tail voltage remains constant if the two inputs vary differentially and by a small amount—an observation critical to the small-signal analysis of the circuit. The reader may wonder why Eq. (10.32) does not hold if V is large. Which one of the above equations is violated? For a large differential input, Q 1 and Q 2 carry significantly different currents, thus exhibiting unequal transconductances and prohibiting the omission of gm’s from the two sides of Eq. (10.31). With VP = 0 in Fig. 10.11(a), we can rewrite Eqs. (10.29) and (10.30) respectively as IC 1 = gmV

(10.33)

IC 2 = −gmV

(10.34)

VX = −gmVRC

(10.35)

VY = gmVRC .

(10.36)

and

The differential output therefore goes from 0 to VX − VY = −2gmVRC .

(10.37)

We define the small-signal differential gain of the circuit as Av = =

Change in Differential Output Change in Differential Input

(10.38)

−2gmVRC 2V

(10.39)

= −gmRC .

(10.40)

(Note that the change in the differential input is equal to 2V.) This expression is similar to that of the common-emitter stage.

Example 10.6

Design a bipolar differential pair for a gain of 10 and a power budget of 1 mW with a supply voltage of 2 V.

Solution

With VCC = 2 V, the power budget translates to a tail current of 0.5 mA. Each transistor thus carries a current of 0.25 mA near equilibrium, providing a transconductance of 0.25 mA/26 mV = (104 )−1 . It follows that |Av | gm

(10.41)

= 1040 .

(10.42)

RC =

Exercise

Redesign the circuit for a power budget of 0.5 mW and compare the results.

410

Chapter 10 Differential Amplifiers

Example 10.7

Compare the power dissipation of a bipolar differential pair with that of a CE stage if both circuits are designed for equal voltage gains, collector resistances, and supply voltages.

Solution

The gain of the differential pair is written from Eq. (10.40) as |AV,diff | = gm1,2 RC ,

(10.43)

where gm1,2 denotes the transconductance of each of the two transistors. For a CE stage |AV,CE | = gmRC .

(10.44)

gm1,2 RC = gmRC

(10.45)

IEE IC = , 2VT VT

(10.46)

Thus,

and hence

where IEE /2 is the bias current of each transistor in the differential pair, and IC represents the bias current of the CE stage. In other words, IEE = 2IC ,

(10.47)

indicating that the differential pair consumes twice as much power. This is one of the drawbacks of differential circuits. Exercise

If both circuits are designed for the same power budget, equal collector resistances, and equal supply voltages, compare their voltage gains.

10.2.2 Large-Signal Analysis Having obtained insight into the operation of the bipolar differential pair, we now quantify its large-signal behavior, aiming to formulate the input/output characteristic of the circuit (the sketches in Fig. 10.10). Not having seen any large-signal analysis in the previous chapters, the reader may naturally wonder why we are suddenly interested in this aspect of the differential pair. Our interest arises from (a) the need to understand the circuit’s limitations in serving as a linear amplifier, and (b) the application of the differential pair as a (nonlinear) current-steering circuit. In order to derive the relationship between the differential input and output of the circuit, we first note from Fig. 10.12 that Vout1 = VCC − RC IC 1

(10.48)

Vout2 = VCC − RC IC 2

(10.49)

Vout = Vout1 − Vout2

(10.50)

and hence = −RC (IC 1 − IC 2 ).

(10.51)

We must therefore compute IC 1 and IC 2 in terms of the input difference. Assuming α = 1 and VA = ∞, and recalling from Chapter 4 that VBE = VT ln (IC /IS ), we write a KVL around

10.2 Bipolar Differential Pair

411

VCC RC

RC

V out1

Vout

V in1

Q1

Vout2 Q2

Vin2

P I EE

Figure 10.12

Bipolar differential pair for large-signal analysis.

the input network, Vin1 − VBE1 = VP = Vin2 − VBE2 ,

(10.52)

obtaining Vin1 − Vin2 = VBE1 − VBE2

(10.53)

= VT ln

IC 1 IC 2 − VT ln IS1 IS2

(10.54)

= VT ln

IC 1 . IC 2

(10.55)

Also, a KCL at node P gives IC 1 + IC 2 = IEE .

(10.56)

Equations (10.55) and (10.56) contain two unknowns. Substituting for IC 1 from Eq. (10.55) in Eq. (10.56) yields IC 2 exp

Vin1 − Vin2 + IC 2 = IEE VT

(10.57)

and, therefore, IC 2 =

IEE . Vin1 − Vin2 1 + exp VT

(10.58)

The symmetry of the circuit with respect to Vin1 and Vin2 and with respect to IC 1 and IC 2 suggests that IC 1 exhibits the same behavior as Eq. (10.58) but with the roles of Vin1 and Vin2 exchanged: IC 1 =

IEE Vin2 − Vin1 1 + exp VT

Vin1 − Vin2 VT . = Vin1 − Vin2 1 + exp VT

(10.59)

IEE exp

(10.60)

Alternatively, the reader can substitute for IC 2 from Eq. (10.58) in Eq. (10.56) to obtain IC 1 .

412

Chapter 10 Differential Amplifiers Equations (10.58) and (10.60) play a crucial role in our quantitative understanding of the differential pair’s operation. In particular, if Vin1 − Vin2 is very negative, then exp(Vin1 − Vin2 )/VT → 0 and IC 1 → 0

(10.61)

IC 2 → IEE ,

(10.62)

as predicted by our qualitative analysis [Fig. 10.9(b)]. Similarly, if Vin1 − Vin2 is very positive, exp(Vin1 − Vin2 )/VT → ∞ and IC 1 → IEE

(10.63)

IC 2 → 0.

(10.64)

What is meant by “very” negative or positive? For example, can we say IC 1 ≈ 0 and IC 2 ≈ IEE if Vin1 − Vin2 = −10VT ? Since exp(−10) ≈ 4.54 × 10−5 , IC 1 ≈

IEE × 4.54 × 10−5 1 + 4.54 × 10−5

(10.65)

≈ 4.54 × 10−5 IEE

(10.66)

IEE 1 + 4.54 × 10−5

(10.67)

and IC 2 ≈

≈ IEE (1 − 4.54 × 10−5 ).

(10.68)

In other words, Q 1 carries only 0.0045% of the tail current; and IEE can be considered steered completely to Q 2 .

Example 10.8

Determine the differential input voltage that steers 98% of the tail current to one transistor.

Solution

We require that IC 1 = 0.02IEE ≈ IEE exp

(10.69) Vin1 − Vin2 VT

(10.70)

and hence Vin1 − Vin2 ≈ −3.91VT .

(10.71)

We often say a differential input of 4VT is sufficient to turn one side of the bipolar pair nearly off. Note that this value remains independent of IEE and IS . Exercise

What differential input is necessary to steer 90% of the tail current?

10.2 Bipolar Differential Pair

413

For the output voltages in Fig. 10.12, we have Vout1 = VCC − RC IC 1

(10.72)

Vin1 − Vin2 IEE exp VT = VCC − RC Vin1 − Vin2 1 + exp VT

(10.73)

and Vout2 = VCC − RC IC 2

(10.74)

IEE . = VCC − RC Vin1 − Vin2 1 + exp VT

(10.75)

Of particular importance is the output differential voltage: Vout1 − Vout2 = −RC (IC 1 − IC 2 )

(10.76)

Vin1 − Vin2 VT = RC IEE Vin1 − Vin2 1 + exp VT 1 − exp

= −RC IEE tanh

Vin1 − Vin2 . 2VT

(10.77)

(10.78)

Figure 10.13 summarizes the results, indicating that the differential output voltage begins from a “saturated” value of +RC IEE for a very negative differential input, gradually becomes a linear function of Vin1 − Vin2 for relatively small values of |Vin1 − Vin2 |, and reaches a saturated level of −RC IEE as Vin1 − Vin2 becomes very positive. From Example 10.8, we recognize that even a differential input of 4VT ≈ 104 mV “switches” the differential pair, thereby concluding that |Vin1 − Vin2 | must remain well below this value for linear operation. I EE I C2

I EE 2

I C1

V in1 – V in2

VCC I EE VCC – R C 2 VCC – R C I EE

V out1 V out2

V in1 – V in2

+ R C I EE

V out1 – V out2

V in1 – V in2

– R C I EE

Figure 10.13

Variation of currents and voltages as a function of input.

414

Chapter 10 Differential Amplifiers

Example 10.9

Sketch the output waveforms of the bipolar differential pair in Fig. 10.14(a) in response to the sinusoidal inputs shown in Figs. 10.14(b) and (c). Assume Q 1 and Q 2 remain in the forward active region.

Solution

For the sinusoids depicted in Fig. 10.14(b), the circuit operates linearly because the maximum differential input is equal to ±2 mV. The outputs are therefore sinusoids having a peak amplitude of 1 mV × gmRC [Fig. 10.14(d)]. On the other hand, the sinusoids in Fig. 10.14(c) force a maximum input difference of ±200 mV, turning Q 1 or Q 2 off. For example, as Vin1 approaches 50 mV above VCM and Vin2 reaches 50 mV below VCM (at t = t1 ), Q 1 absorbs most of the tail current, thus producing Vout1 ≈ VCC − RC IEE

(10.79)

Vout2 ≈ VCC .

(10.80)

Thereafter, the outputs remain saturated until |Vin1 − Vin2 | falls to less than 100 mV. The result is sketched in Fig. 10.14(e). We say the circuit operates as a “limiter” in this case, playing a role similar to the diode limiters studied in Chapter 3.

Vin1 VCC RC

Q2

VCM

Vin2

Vout2 Q1

100 mV 1 mV

VCM

RC

V out1 V in1

Vin1

Vin2

Vin2 t1

t

P

(b)

I EE

Vout2

Vout2 (a)

t (c)

VCC

1 mV x g m R C

VCM

VCC – R C

Vout1 Vout1 t (d)

t1

I EE 2

VCC – R C I EE t

(e)

Figure 10.14 Exercise

What happens to the above results if the tail current is halved?

10.2.3 Small-Signal Analysis Our brief investigation of the differential pair in Fig. 10.11 revealed that, for small differential inputs, the tail node maintains a constant voltage (and hence is called a “virtual ground”). We also obtained a voltage gain equal to gmRC . We now study the small-signal behavior of the circuit in greater detail. As explained in previous chapters, the definition of “small signals” is somewhat arbitrary, but the requirement is that the input signals not influence the bias currents of Q 1 and Q 2 appreciably. In other words, the two transistors

10.2 Bipolar Differential Pair

RC v in1

r π1

vπ 1

415

RC g

m1

g

vπ 1

m2

vπ 2

vπ 2

r π2

v in2

vπ 2

r π2

v in2

P (a) RC v in1

r π1

vπ 1

RC g

m1

g

vπ 1

m2

vπ 2

(b)

VCC RC V in1

RC

Q1

Q2

Vin2

(c)

(a) Small-signal model of bipolar pair, (b) simplified small-signal model, (c) simplied diagram.

Figure 10.15

must exhibit approximately equal transconductances—the same condition required for node P to appear as virtual ground. In practice, an input difference of less than 10 mV is considered “small” for most applications. Assuming perfect symmetry, an ideal tail current source, and VA = ∞, we construct the small-signal model of the circuit as shown in Fig. 10.15(a). Here, vin1 and vin2 represent small changes in each input and must satisfy vin1 = −vin2 for differential operation. Note that the tail current source is replaced with an open circuit. As with the foregoing largesignal analysis, let us write a KVL around the input network and a KCL at node P: vin1 − vπ 1 = vP = vin2 − vπ 2

(10.81)

vπ 1 vπ 2 + gm1 vπ 1 + + gm2 vπ 2 = 0. rπ 1 rπ 2

(10.82)

With rπ 1 = rπ 2 and gm1 = gm2 , Eq. (10.82) yields vπ 1 = −vπ 2

(10.83)

and since vin1 = −vin2 , Eq. (10.81) translates to 2vin1 = 2vπ 1 .

(10.84)

vP = vin1 − vπ 1

(10.85)

That is,

= 0. Thus, the small-signal model confirms the prediction made by Eq. (10.32).

(10.86)

416

Chapter 10 Differential Amplifiers The virtual-ground nature of node P for differential small-signal inputs simplifies the analysis considerably. Since vP = 0, this node can be shorted to ac ground, reducing the differential pair of Fig. 10.15(a) to two “half circuits” [Fig. 10.15(b)]. With each half resembling a common-emitter stage, we can write vout1 = −gmRC vin1

(10.87)

vout2 = −gmRC vin2 .

(10.88)

It follows that the differential voltage gain of the differential pair is equal to vout1 − vout2 = −gmRC , vin1 − vin2

(10.89)

the same as that expressed by Eq. (10.40). For simplicity, we may draw the two half circuits as in Fig. 10.15(c), with the understanding that the incremental inputs are small and differential. Also, since the two halves are identical, we may draw only one half.

Example 10.10

Compute the differential gain of the circuit shown in Fig. 10.16(a), where ideal current sources are used as loads to maximize the gain.

VCC v out V in1

Vout Q1

Q2

Vin2

v in1

r O1

v in2

r O2

Q2

Q1 P I EE (a)

(b)

Figure 10.16 Solution

With ideal current sources, the Early effect in Q 1 and Q 2 cannot be neglected, and the half circuits must be visualized as depicted in Fig. 10.16(b). Thus, vout1 = −gmrO vin1

(10.90)

vout2 = −gmrO vin2

(10.91)

vout1 − vout2 = −gmrO . vin1 − vin2

(10.92)

and hence

Exercise

Calculate the gain for VA = 5 V.

10.2 Bipolar Differential Pair

417

Example 10.11

Figure 10.17(a) illustrates an implementation of the topology shown in Fig. 10.16(a). Calculate the differential voltage gain.

Solution

Noting that each pnp device introduces a resistance of rOP at the output nodes and drawing the half circuit as in Fig. 10.17(b), we have vout1 − vout2 = −gm(rON ||rOP ), vin1 − vin2

(10.93)

where rON denotes the output impedance of the npn transistors. VCC Vb

V in1

Q3

Q4 Vout Q1

Q2

Q3

Vin2

v out

v in1

P I EE

Q1

(a)

(b)

Figure 10.17 Exercise

Calculate the gain if Q 3 and Q 4 are configured as diode-connected devices. We must emphasize that the differential voltage gain is defined as the difference between the outputs divided by the difference between the inputs. As such, this gain is equal to the single-ended gain of each half circuit. We now make an observation that proves useful in the analysis of differential circuits. As noted above, the symmetry of the circuit (gm1 = gm2 ) establishes a virtual ground at node P in Fig. 10.12 if the incremental inputs are small and differential. This property holds for any other node that appears on the axis of symmetry. For example, the two resistors shown in Fig. 10.18 create a virtual ground at X if (1) R1 = R2 and (2) nodes A and B vary by equal and opposite amounts.2 Additional examples make this concept clearer. We assume perfect symmetry in each case. ΔV A

R1

R2 X

B

ΔV

Figure 10.18

Example 10.12

Determine the differential gain of the circuit in Fig. 10.19(a) if VA < ∞ and the circuit is symmetric.

Solution

Drawing one of the half circuits as shown in Fig. 10.19(b), we express the total resistance seen at the collector of Q 1 as Rout = rO1 ||rO3 ||R1 . 2

Since the resistors are linear, the signals need not be small in this case.

(10.94)

418

Chapter 10 Differential Amplifiers

Vb

VCC Q3

Q4 Vout R1

V in1

Q1

Q3

R2 V in1

Vin2

Q2

Vout R1

Q1 P I EE (a)

(b)

Figure 10.19

Thus, the voltage gain is equal to Av = −gm1 (rO1 ||rO3 ||R1 ).

(10.95)

Exercise

Repeat the above example if R1 = R2 .

Example 10.13

Calculate the differential gain of the circuit illustrated in Fig. 10.20(a) if VA < ∞.

VCC

X

Q3 R1

Q4 R2

R1 v out1

Vout V in1

Q1

X

Q3

Q2

Vin2

v in1 Q1

P I EE (a)

(b)

Figure 10.20

Solution

For small differential inputs and outputs, VX remains constant, leading to the conceptual half circuit shown in Fig. 10.20(b)—the same as that in the above example. This is because Q 3 and Q 4 experience a constant base-emitter voltage in both cases, thereby serving as current sources and exhibiting only an output resistance. It follows that Av = −gm1 (rO1 ||rO3 ||R1 ).

Exercise

(10.96)

Calculate the gain if VA = 4 V for all transistors, R1 = R2 = 10 k, and IEE = 1 mA.

10.2 Bipolar Differential Pair Example 10.14

419

Determine the gain of the degenerated differential pairs shown in Figs. 10.21(a) and (b). Assume VA = ∞. VCC RC

RC

RC Vout

X V in1

VCC

Y

Q1

Q2 RE P

RC Vout

X Vin2

RE I EE

V in1

Q1

I EE

(b)

RC

RC v out

Q1

Vin2

Q2 RE

I EE

(a)

v in1

Y

v out RE

v in1

RE

2

Q1

(c)

(d)

Figure 10.21 Solution

In the topology of Fig. 10.21(a), node P is a virtual ground, yielding the half circuit depicted in Fig. 10.21(c). From Chapter 5, we have RC Av = − . (10.97) 1 RE + gm In the circuit of Fig. 10.21(b), the line of symmetry passes through the “midpoint” of RE . In other words, if RE is regarded as two RE /2 units in series, then the node between the units acts as a virtual ground [Fig. 10.21(d)]. It follows that Av = −

RC . RE 1 + 2 gm

(10.98)

The two circuits provide equal gains if the pair in Fig. 10.21(b) incorporates a total degeneration resistance of 2RE . Exercise

Design each circuit for a gain of 5 and power consumption of 2 mW. Assume VCC = 2.5 V, VA = ∞, and RE = 2/gm.

I/O Impedances For a differential pair, we can define the input impedance as illustrated in Fig. 10.22(a). From the equivalent circuit in Fig. 10.22(b), we have vπ 1 vπ 2 = iX = − . (10.99) rπ 1 rπ 2

420

Chapter 10 Differential Amplifiers VCC RC iX

RC Q1

iX

Q2

r π1

RC

RC g

vπ 1

m1

g

vπ 1

m2

vπ 2

iX vπ 2

r π2

P vX

I EE

vX

(a) Figure 10.22

(b)

(a) Method for calculation of differential input impedance, (b) equivalent circuit

of (a).

Also, vX = vπ 1 − vπ 2

(10.100)

= 2rπ 1 iX .

(10.101)

vX = 2rπ 1 , iX

(10.102)

It follows that

as if the two base-emitter junctions appear in series. The above quantity is called the “differential input impedance” of the circuit. It is also possible to define a “single-ended input impedance” with the aid of a half circuit (Fig. 10.23), obtaining vX = rπ 1 . iX

(10.103)

This result provides no new information with respect to that in Eq. (10.102) but proves useful in some calculations. VCC RC iX

Q1

vX

Figure 10.23

Calculation of single-ended input impedance.

In a manner similar to the foregoing development, the reader can show that the differential and single-ended output impedances are equal to 2RC and RC , respectively.

10.3

MOS DIFFERENTIAL PAIR Most of the principles studied in the previous section for the bipolar differential pair apply directly to the MOS counterpart as well. For this reason, our treatment of the MOS circuit in this section is more concise. We continue to assume perfect symmetry.

10.3 MOS Differential Pair

421

VDD RD

RD

X

Y M1

M2

V CM I SS

Figure 10.24

Response of MOS differential pair to input CM variation.

10.3.1 Qualitative Analysis Figure 10.24(a) depicts the MOS pair with the two inputs tied to VCM , yielding ID1 = ID2 =

ISS 2

(10.104)

and VX = VY = VDD − RD

ISS . 2

(10.105)

That is, a zero differential input gives a zero differential output. Note that the output CM level is equal to VDD − RD ISS /2. For our subsequent derivations, it is useful to compute the “equilibrium overdrive voltage” of M1 and M2 , (VGS − VTH )equil. . We assume λ = 0 and hence ID = (1/2)μnCox (W/L)(VGS − VTH )2 . Carrying a current of ISS /2, each device exhibits an overdrive of ISS . (10.106) (VGS − VTH )equil. = W μnC ox L As expected, a greater tail current or a smaller W/L translates to a larger equilibrium overdrive. To guarantee that M1 and M2 operate in saturation, we require that their drain voltages not fall below VCM − VTH : ISS (10.107) > VCM − VTH . 2 It can also be observed that a change in VCM cannot alter ID1 = ID2 = ISS/2, leaving VX and VY undisturbed. The circuit thus rejects input CM variations. VDD − RD

Example 10.15

A MOS differential pair is driven with an input CM level of 1.6 V. If ISS = 0.5 mA, VTH = 0.5 V, and VDD = 1.8 V, what is the maximum allowable load resistance?

Solution

From Eq. (10.107), we have RD < 2

VDD − VCM + VTH ISS

< 2.8 k.

(10.108) (10.109)

422

Chapter 10 Differential Amplifiers We may suspect that this limitation in turn constrains the voltage gain of the circuit, as explained later.

Exercise

What is the maximum tail current if the load resistance is 5 k?

Figure 10.25 illustrates the response of the MOS pair to large differential inputs. If Vin1 is well above Vin2 [Fig. 10.25(a)], then M1 carries the entire tail current, generating VX = VDD − RD ISS

(10.110)

VY = VDD .

(10.111)

Similarly, if Vin2 is well above Vin1 [Fig. 10.25(b)], then VX = VDD

(10.112)

VY = VDD − RD ISS .

(10.113)

The circuit therefore steers the tail current from one side to the other, producing a differential output in response to a differential input. Figure 10.25(c) sketches the characteristics of the circuit. Let us now examine the circuit’s behavior for a small input difference. Depicted in Fig. 10.26(a), such a scenario maintains VP constant because Eqs. (10.27)–(10.32) apply to this case equally well. It follows that ID1 = gmV

(10.114)

ID2 = −gmV

(10.115)

VDD RD

VDD RD

RD

RD

Vout

Vout

X V in1

Y Y

M1 M2

X V in1

Vin2

M2

I SS

I SS

(a)

(b)

I SS I D2

VY

2 0

VDD I SS VDD – R D 2 VDD – R D I SS

VX

I SS

I D1

Vin2

M1

V in1 – V in2

V in1 – V in2

(c)

(a) Response of MOS differential pair to very positive input, (b) response of MOS differential pair to very negative input, (c) qualitative plots of currents and voltages.

Figure 10.25

10.3 MOS Differential Pair

423

VDD RD

VCM

+ ΔV

RD

X

Y M1

M2

VCM

– ΔV

P I SS

Figure 10.26

Response of MOS pair to small differential inputs.

and VX − VY = −2gmRD V.

(10.116)

As expected, the differential voltage gain is given by Av = −gmRD ,

(10.117)

similar to that of a common-source stage.

Example 10.16

Design an NMOS differential pair for a voltage gain of 5 and a power budget of 2 mW subject to the condition that the stage following the differential pair requires an input CM level of at least 1.6 V. Assume μnCox = 100 μA/V2 , λ = 0, and VDD = 1.8 V.

Solution

From the power budget and the supply voltage, we have ISS = 1.11 mA.

(10.118)

The output CM level (in the absence of signals) is equal to ISS . (10.119) 2 For VCM,out = 1.6 V, each resistor must sustain a voltage drop of no more than 200 mV, thereby assuming a maximum value of VCM,out = VDD − RD

RD = 360 .

(10.120)

Setting gmRD = 5, we must choose the transistor dimensions such that gm = 5/(360 ). Since each transistor carries a drain current of ISS /2, W ISS gm = 2μnCox , (10.121) L 2 and hence W = 1738. (10.122) L The large aspect ratio arises from the small drop allowed across the load resistors. Exercise

If the aspect ratio must remain below 200, what voltage gain can be achieved?

424

Chapter 10 Differential Amplifiers

Example 10.17

What is the maximum allowable input CM level in the previous example if VTH = 0.4 V?

Solution

We rewrite Eq. (10.107) as ISS + VTH 2 < VCM,out + VTH .

VCM,in < VDD − RD

(10.123) (10.124)

This is conceptually illustrated in Fig. 10.27. Thus, VCM,in < 2 V.

(10.125)

Interestingly, the input CM level can comfortably remain at VDD . In contrast to Example 10.5, the constraint on the load resistor in this case arises from the output CM level requirement.

VDD RD

RD

X

Y M1

V CM,in

M2

V TH

V CM,in

V CM,out

I SS

Figure 10.27 Exercise

Does the above result hold if VTH = 0.2 V?

Example 10.18

The common-source stage and the differential pair shown in Fig. 10.28 incorporate equal load resistors. If the two circuits are designed for the same voltage gain and the same supply voltage, discuss the choice of (a) transistor dimensions for a given power budget, (b) power dissipation for given transistor dimensions.

VDD

VDD R

R V in1 v in

Figure 10.28

M1

R M1

M2 I SS

Vin2

10.3 MOS Differential Pair

425

Solution

(a) For the two circuits to consume the same amount of power ID1 = ISS = 2ID2 = 2ID3 ; i.e., each transistor in the differential pair carries a current equal to half of the drain current of the CS transistor. Equation (10.121) therefore requires that the differential pair transistors be twice as wide as the CS device to obtain the same voltage gain. (b) If the transistors in both circuits have the same dimensions, then the tail current of the differential pair must be twice the bias current of the CS stage for M1 -M3 to have the same transconductance, doubling the power consumption.

Exercise

Discuss the above results if the CS stage and the differential pair incorporate equal source degeneration resistors.

10.3.2 Large-Signal Analysis As with the large-signal analysis of the bipolar pair, our objective here is to derive the input/output characteristics of the MOS pair as the differential input varies from very negative to very positive values. From Fig. 10.29, we have Vout = Vout1 − Vout2

(10.126)

= −RD (ID1 − ID2 ).

(10.127)

To obtain ID1 − ID2 , we neglect channel-length modulation and write a KVL around the input network and a KCL at the tail node: Vin1 − VGS1 = Vin2 − VGS2 ID1 + ID2 = ISS .

(10.128) (10.129)

2

Since ID = (1/2)μnCox (W/L)(VGS − VTH ) , VGS = VTH

+

2ID μnCox

W L

.

(10.130)

Substituting for VGS1 and VGS2 in Eq. (10.128), we have Vin1 − Vin2 = VGS1 − VGS2 2 ( ID1 − ID2 ). = W μnCox L VDD RD

RD Vout

V out1 V in1

M1

Vout2 M2 I SS

Figure 10.29

MOS differential pair for large-signal analysis.

Vin2

(10.131) (10.132)

426

Chapter 10 Differential Amplifiers Squaring both sides yields (Vin1 − Vin2 )2 =

=

We now find

√ ID1 ID2 ,

2 W μnCox L 2 W μnCox L

(ID1 + ID2 − 2 ID1 ID2 )

(10.133)

(ISS − 2 ID1 ID2 ).

(10.134)

W 4 ID1 ID2 = 2ISS − μnCox (Vin1 − Vin2 )2 , L

(10.135)

square the result again, 2 W 2 = 2ISS − μnCox (Vin1 − Vin2 ) , L

16ID1 ID2

(10.136)

and substitute ISS − ID1 for ID2 , 2 W 16ID1 (ISS − ID1 ) = 2ISS − μnCox (Vin1 − Vin2 )2 . L

(10.137)

It follows that

2 16ID1

and hence ID1

W − 16ISS ID1 + 2ISS − μnCox (Vin1 − Vin2 )2 L

2 =0

2 W ISS 1 2 2 = 4ISS − μnCox (Vin1 − Vin2 ) − 2ISS . ± 2 4 L

(10.138)

(10.139)

In Problem 10.44, we show that only the solution with the sum of the two terms is acceptable: Vin1 − Vin2 W W ISS 2 ID1 = (10.140) + 4ISS − μnCox (Vin1 − Vin2 ) . μnCox 2 4 L L The symmetry of the circuit also implies that W W Vin2 − Vin1 ISS 2 ID2 = + 4ISS − μnCox (Vin2 − Vin1 ) . μnCox 2 4 L L

(10.141)

That is, ID1 − ID2

W 1 = μnCox (Vin1 − Vin2 ) 2 L

4ISS − (Vin1 − Vin2 )2 . W μnCox L

Equations (10.140)–(10.142) form the foundation of our understanding of the MOS differential pair.

10.3 MOS Differential Pair

427

Let us now examine Eq. (10.142) closely. As expected from the characteristics in Fig. 10.25(c), the right-hand side is an odd (symmetric) function of Vin1 − Vin2 , dropping to zero for a zero input difference. But, can the difference under the square root vanish, too? That would suggest that ID1 − ID2 falls to zero as (Vin1 − Vin2 )2 reaches 4ISS /(μnCox W/L), an effect not predicted by our qualitative sketches in Fig. 10.25(c). Furthermore, it appears that the argument of the square root becomes negative as (Vin1 − Vin2 )2 exceeds this value! How should these results be interpreted? Edge of Conduction +

Figure 10.30

VTH

~0

I SS

M1

M2 –

–

+ VGS2

I SS

MOS differential pair with one device off.

Implicit in our foregoing derivations is the assumption both transistors are on. However, as |Vin1 − Vin2 | rises, at some point M1 or M2 turns off, violating the above equations. We must therefore determine the input difference that places one of the transistors at the edge of conduction. This can be accomplished by equating Eqs. (10.140), (10.141), or (10.142) to ISS , but this leads to lengthy algebra. Instead, we recognize from Fig. 10.30 that if, for example, M1 approaches the edge of conduction, then its gate-source voltage falls to a value equal to VTH . Also, the gate-source voltage of M2 must be sufficiently large to accommodate a drain current of ISS : VGS1 = VTH VGS2 = VTH

+

It follows from Eq. (10.128) that |Vin1 − Vin2 |max

(10.142) 2ISS . W μnCox L

=

2ISS , W μnCox L

(10.143)

(10.144)

where |Vin1 − Vin2 |max denotes the input difference that places one transistor at the edge of conduction. Equation (10.145) is invalid for input differences greater than this value. Indeed, substituting from Eq. (10.145) in (10.142) also yields |ID1 − ID2 | = ISS . We also note that |Vin1 − Vin2 |max can be related to the equilibrium overdrive [Eq. (10.106)] as follows: √ |Vin1 − Vin2 |max = 2(VGS − VTH )equil. . (10.145) The above findings are very important and stand in contrast to the behavior of the bipolar differential pair and Eq. (10.78): the MOS pair steers all of the tail current3 for |Vin1 − Vin2 |max whereas the bipolar counterpart only approaches this condition for a finite 3 In reality, MOS devices carry a small current for VGS = VTH , making these observations only an approximate illustration.

428

Chapter 10 Differential Amplifiers I SS I D2

I SS 2

I D1 – ΔV in,max

I D1 – I

0 (a)

V in1 – V in2

+ I SS

D2

– ΔV in,max

+ ΔV in,max

+ ΔV in,max 0

V in1 – V in2

– I SS (b)

V out1 – V out2

+ R D I SS – ΔV in,max 0

+ ΔV in,max

V in1 – V in2

– R D I SS (c)

Variation of (a) drain currents, (b) the difference between drain currents, and (c) differential output voltage as a function of input.

Figure 10.31

input difference. Equation (10.146) provides a great deal of intuition into the operation of the MOS pair. Specifically, we plot ID1 and ID2 as in Fig. 10.31(a), where Vin = Vin1 − Vin2 , arriving at the differential characteristics in Figs. 10.31(b) and (c). The circuit thus behaves linearly for small values of Vin and becomes completely nonlinear for Vin > Vin,max . In other words, Vin,max serves as an absolute bound on the input signal levels that have any effect on the output. Example 10.19

Solution

Examine the input/output characteristic of a MOS differential pair if (a) the tail current is doubled, or (b) the transistor aspect ratio is doubled. √ (a) Equation (10.145) suggests that doubling ISS increases Vin,max by a factor of 2. Thus, the characteristic of Fig. 10.31(c) expands horizontally. Furthermore, since ISS RD doubles, the characteristic expands vertically as well. Figure 10.32(a) illustrates the result, displaying a greater slope. √ (b) Doubling W/L lowers Vin,max by a factor of 2 while maintaining ISS RD constant. The characteristic therefore contracts horizontally [Fig. 10.32(b)], exhibiting a larger slope in the vicinity of Vin = 0.

Exercise

Repeat the above example if (a) the tail current is halved, or (b) the transistor aspect ratio is halved.

Example 10.20

Design an NMOS differential pair for a power budget of 3 mW and Vin,max = 500 mV. Assume μnCox = 100 μA/V2 and VDD = 1.8 V.

10.3 MOS Differential Pair

429

Vout1 – V out2 +2R D I SS + R D I SS + ΔV in,max – 2 ΔV in,max

– ΔV in,max

+ 2 ΔV in,max

V in1 – V in2

– R D I SS –2R D I SS (a)

V out1 – V out2 + R D I SS + ΔV in,max

– ΔV in,max

2 – ΔV in,max

V in1 – V in2 + ΔV in,max

2 – R D I SS (b)

Figure 10.32

Solution

The tail current must not exceed 3 mW/1.8 V = 1.67 mA. From Eq. (10.145), we write W 2ISS = 2 L μnCox Vin,max = 133.6.

(10.146) (10.147)

The value of the load resistors is determined by the required voltage gain. Exercise

How does the above design change if the power budget is raised to 5 mW?

10.3.3 Small-Signal Analysis The small-signal analysis of the MOS differential pair proceeds in a manner similar to that in Section 10.2.3 for the bipolar counterpart. The definition of “small” signals in this case can be seen from Eq. (10.142); if |Vin1 − Vin2 |

4ISS , W μnCox L

(10.148)

430

Chapter 10 Differential Amplifiers then ID1 − ID2

W 1 ≈ μnCox (Vin1 − Vin2 ) 2 L =

μnCox

4ISS W μnCox L

(10.149)

W ISS (Vin1 − Vin2 ). L

(10.150)

Now, the differential inputs and outputs are linearly proportional, and the circuit operates linearly. We now use the small-signal model to prove that the tail node remains constant in the presence of small differential inputs. If λ = 0, the circuit reduces to that shown in Fig. 10.33(a), yielding vin1 − v1 = vin2 − v2

(10.151)

gm1 v1 + gm2 v2 = 0.

(10.152)

Assuming perfect symmetry, we have from Eq. (10.153) v1 = −v2

(10.153)

and for differential inputs, we require vin1 = −vin2 . Thus, Eq. (10.152) translates to vin1 = v1

(10.154)

vP = vin1 − v1

(10.155)

and hence

=0

(10.156)

Alternatively, we can simply utilize Eqs. (10.81)–(10.86) with the observation that vπ /rπ = 0 for a MOSFET, arriving at the same result.

RD v in1

RD g

v1

g

v m1 1

v m2 2

v2

v in2

v2

v in2

P (a) RC v in1

v1

RC g

g

v m1 1

v m2 2

(b)

Figure 10.33

(a) Small-signal model of MOS differential pair, (b) simplified circuit.

10.3 MOS Differential Pair

431

With node P acting as a virtual ground, the concept of half circuit applies, leading to the simplified topology in Fig. 10.33(b). Here, vout1 = −gmRD vin1

(10.157)

vout2 = −gmRD vin2 ,

(10.158)

vout1 − vout2 = −gmRD . vin1 − vin2

(10.159)

and, therefore,

Example 10.21

Solution

Prove that Eq. (10.151) can also yield the differential voltage gain. Since Vout1 − Vout2 = −RD (ID1 − ID2 ) and since gm = μnCox (W/L)ISS (why?), we have from Eq. (10.151) W Vout1 − Vout2 = −RD μnCox ISS (Vin1 − Vin2 ) (10.160) L = −gmRD (Vin1 − Vin2 ).

(10.161)

This is, of course, to be expected. After all, small-signal operation simply means approximating the input/output characteristic [Eq. (10.142)] with a straight line [Eq. (10.151)] around an operating point (equilibrium). Exercise

Using the equation gm = 2ID/(VGS − VTH ), express the above result in terms of the equilibrium overdrive voltage.

As with the bipolar circuits studied in Examples 10.10 and 10.14, the analysis of MOS differential topologies is greatly simplified if virtual grounds can be identified. The following examples reinforce this concept. Example 10.22

Determine the voltage gain of the circuit shown in Fig. 10.34(a). Assume λ = 0.

VDD M4

M3 V in1

Vout M2

M1

M3 Vin2

v in1

v out1 M1

I SS (a)

Figure 10.34

(b)

432

Chapter 10 Differential Amplifiers

Solution

Drawing the half circuit as in Fig. 10.34(b), we note that the total resistance seen at the drain of M1 is equal to (1/gm3 )||rO3 ||rO1 . The voltage gain is therefore equal to

1 Av = −gm1 (10.162) ||rO3 ||rO1 . gm3

Exercise

Repeat the above example if a resistance of value R1 is inserted in series with the sources of M3 and M4 .

Example 10.23

Assuming λ = 0, compute the voltage gain of the circuit illustrated in Fig. 10.35(a). VDD

Vout M1 V in1

M2 M3

Vin2

M4 Q

P

v in1

I SS2

I SS1

v out1

M1 M3

(a)

(b)

Figure 10.35

Solution

Identifying both nodes P and Q as virtual grounds, we construct the half circuit shown in Fig. 10.35(b), and write gm1 Av = − . (10.163) gm3

Exercise

Repeat the above example if λ = 0.

Example 10.24

Assuming λ = 0, calculate the voltage gain of the topology shown in Fig. 10.36(a). VDD

R DD

Vout

2

V in1

M1

R DD R SS

M2

Vin2

v in1

v out1 M1 R SS 2

(a)

Figure 10.36

(b)

10.4 Cascode Differential Amplifiers Solution

433

Grounding the midpoint of RSS and RDD , we obtain the half circuit in Fig. 10.36(b), where

Av = −

RDD 2 RSS 1 + 2 gm

.

(10.164)

Exercise

Repeat the above example if the load current sources are replaced with diode-connected PMOS devices.

10.4

CASCODE DIFFERENTIAL AMPLIFIERS Recall from Chapter 9 that cascode stages provide a substantially higher voltage gain than simple CE and CS stages do. Noting that the differential gain of differential pairs is equal to the single-ended gain of their corresponding half circuits, we surmise that cascoding boosts the gain of differential pairs as well. We begin our study with the structure depicted in Fig. 10.37(a), whereQ 3 andQ 4 serve as cascode devices and I1 and I2 are ideal. Recognizing that the bases of Q 3 and Q 4 are at ac ground, we construct the half circuit shown in Fig. 10.37(b). Equation (9.51) readily gives the gain as Av = −gm1 [gm3 (rO1 ||rπ 3 )rO3 + rO1 ||rπ 3 ],

(10.165)

confirming that a differential cascode achieves a much higher gain. The developments in Chapter 9 also suggest the use of pnp cascodes for current sources I1 and I2 in Fig. 10.37(a). Illustrated in Fig. 10.38(a), the resulting configuration can be analyzed with the aid of its half circuit, Fig. 10.38(b). Utilizing Eq. (9.61), we express the voltage gain as Av ≈ −gm1 [gm3rO3 (rO1 ||rπ 3 )]||[gm5rO5 (rO7 ||rπ 5 )].

(10.166)

VCC I1

I2 Vout

Q3

Q4

Vb V in1

Q1

Q2

Vin2 v in1

Q1

I EE (a)

Figure 10.37

v out1

Q3

(b)

(a) Bipolar cascode differential pair, (b) half circuit of (a).

434

Chapter 10 Differential Amplifiers VCC V b3 Q7

Q8

Q5

Q6 Vout

Q7

Q3

Q4

Q5

V b2

V b1 V in1

Q1

Vin2

Q2

v in1

Q1

I EE (a)

Figure 10.38

v out1

Q3

(b)

(a) Bipolar cascode differential pair with cascode loads, (b) half circuit of (a).

Called a “telescopic cascode,” the topology of Fig. 10.38(b) exemplifies the internal circuit of some operational amplifiers.

Example 10.25

Due to a manufacturing defect, a parasitic resistance has appeared between nodes A and B in the circuit of Fig. 10.39(a). Determine the voltage gain of the circuit.

VCC V b3 Q7 A

Q8

B

R1

V b2 Q5

Q6 Vout

Q7

Q3

Q4

Q5

V b1 V in1

2

v out1

Q3 Q1

Q2

Vin2 v in1

Q1

I EE (a)

Figure 10.39

R1

(b)

10.4 Cascode Differential Amplifiers Solution

435

The symmetry of the circuit implies that the midpoint of R1 is a virtual ground, leading to the half circuit shown in Fig. 10.39(b). Thus, R1/2 appears in parallel with rO7 , lowering the output impedance of the pnp cascode. Since the value of R1 is not given, we cannot make approximations and must return to the original expression for the cascode output impedance, Eq. (9.1):

R1 R1 Rop = 1 + gm5 rO7 ||rπ 5 || rO5 + rO7 ||rπ 5 || . 2 2

(10.167)

The resistance seen looking down into the npn cascode remains unchanged and approximately equal to gm3rO3 (rO1 ||rπ 3 ). The voltage gain is therefore equal to Av = −gm1 [gm3rO3 (rO1 ||rπ 3 )]||Rop . Exercise

(10.168)

If β = 50 and VA = 4 V for all transistors and IEE = 1 mA, what value of R1 degrades the gain by a factor of two?

VDD

M3

Vout

V b1 V in1

M4 M2

M1

Vin2 v in1

M1

I SS (a)

Figure 10.40

v out1

M3

(b)

(a) MOS cascode differential pair, (b) half circuit of (a).

We now turn our attention to differential MOS cascodes. Following the above developments for bipolar counterparts, we consider the simplified topology of Fig. 10.40(a) and draw the half circuit as depicted in Fig. 10.40(b). From Eq. (9.69), Av ≈ −gm3rO3 gm1rO1 .

(10.169)

Illustrated in Fig. 10.41(a), the complete CMOS telescopic cascode amplifier incorporates PMOS cascades as load current sources, yielding the half circuit shown in Fig. 10.41(b). It follows from Eq. (9.72) that the voltage gain is given by Av ≈ −gm1 [(gm3rO3rO1 )||(gm5rO5rO7 )].

(10.170)

436

Chapter 10 Differential Amplifiers

V b3 V b2

M7

VDD

M8

M7 M5 M3

M6 Vout

M5

V b1

M4

V in1

M2

M1

Vin2 v in1

I SS (a)

Figure 10.41

v out1

M3

M1

(b)

(a) MOS telescopic cascode amplifier, (b) half circuit of (a).

Example 10.26

Due to a manufacturing defect, two equal parasitic resistances, R1 and R2 , have appeared as shown in Fig. 10.42(a). Compute the voltage gain of the circuit.

Solution

Noting that R1 and R2 appear in parallel with rO5 and rO6 , respectively, we draw the half circuit as depicted in Fig. 10.42(b). Without the value of R1 given, we must resort to the original expression for the output impedance, Eq. (9.3): R p = [1 + gm5 (rO5 ||R1 )]rO7 + rO5 ||R1 .

(10.171)

The resistance seen looking into the drain of the NMOS cascode can still be approximated as Rn ≈ gm3rO3rO1 . (10.172) The voltage gain is then simply equal to Av = −gm1 (R p ||Rn ).

V b3 V b2

M7

M5

M8

R2

R1

M7

M6

Vb2 M5

V b1 V in1

VDD

Vout

M3

M3

M4 M2

M1

(10.173)

v out1

Vin2 v in1

M1

I SS (a)

R1

(b)

Figure 10.42 Exercise

Repeat the above example if in addition to R1 and R2 , a resistor of value R3 appears between the sources of M3 and M4 .

10.5 Common-Mode Rejection

10.5

437

COMMON-MODE REJECTION In our study of bipolar and MOS differential pairs, we have observed that these circuits produce no change in the output if the input CM level changes. The common-mode rejection property of differential circuits plays a critical role in today’s electronic systems. As the reader may have guessed, in practice the CM rejection is not infinitely high. In this section, we examine the CM rejection in the presence of nonidealities. The first nonideality relates to the output impedance of the tail current source. Consider the topology shown in Fig. 10.43(a), where REE denotes the output impedance of IEE . What happens if the input CM level changes by a small amount? The symmetry requires that Q 1 and Q 2 still carry equal currents and Vout1 = Vout2 . But, since the base voltages of bothQ 1 andQ 2 rise, so does VP . In fact, noting that Vout1 = Vout2 , we can place a short circuit between the output nodes, reducing the topology to that shown in Fig. 10.43(b). That is, as far as node P is concerned, Q 1 and Q 2 operate as an emitter follower. As VP increases, so does the current through REE and hence the collector currents ofQ 1 andQ 2 . Consequently, the output common-mode level falls. The change in the output CM level can be computed by noting that the stage in Fig. 10.43(b) resembles a degenerated CE stage. That is, from Chapter 5, Vout,CM =− Vin,CM

=−

RC 2

(10.174)

1 2gm

REE + RC

−1 2REE + gm

,

(10.175)

where the term 2gm represents the transconductance of the parallel combination of Q 1 and Q 2 . This quantity is called the “common-mode gain.” These observations apply to the MOS counterpart equally well. An alternative approach to arriving at Eq. (10.175) is outlined in Problem 10.65. In summary, if the tail current exhibits a finite output impedance, the differential pair produces an output CM change in response to an input CM change. The reader

VCC RC V out1

Vout2 Q1

V CM

P

VCC

RC 2

RC

Vout

Q2

I EE

Q2

V CM R EE

(a)

Q1 P I EE

R EE

(b)

(a) CM response of differential pair in the presence of finite tail impedance, (b) simplified circuit of (a).

Figure 10.43

438

Chapter 10 Differential Amplifiers VCC RC

RC

Vout1 A

Vout2 Q1

V in1

V CM

P

VA

VB

VB

B

Q2

V in2

I EE

A

R EE

Vout1

Vout1

Vout2

Vout2

Vout1 –Vout2

Vout1 –Vout2

t (a)

(b)

t (c)

(a) Differential pair sensing input CM noise, (b) effect of CM noise at output with REE = ∞, (c) effect of CM noise at the output with REE = ∞.

Figure 10.44

may naturally wonder whether this is a serious issue. After all, so long as the quantity of interest is the difference between the outputs, a change in the output CM level introduces no corruption. Figure 10.44(a) illustrates such a situation. Here, two differential inputs, Vin1 and Vin2 , experience some common-mode noise, Vin,CM . As a result, the base voltages ofQ 1 and Q 2 with respect to ground appear as shown in Fig. 10.44(b). With an ideal tail current source, the input CM variation would have no effect at the output, leading to the output waveforms shown in Fig. 10.44(b). On the other hand, with REE < ∞, the single-ended outputs are corrupted, but not the differential output [Fig. 10.44(c)]. In summary, the above study indicates that, in the presence of input CM noise, a finite CM gain does not corrupt the differential output and hence proves benign.4 However, if the circuit suffers from asymmetries and a finite tail current source impedance, then the differential output is corrupted. During manufacturing, random “mismatches” appear between the two sides of the differential pair; for example, the transistors or the load resistors may display slightly different dimensions. Consequently, the change in the tail current due to an input CM variation may affect the differential output. As an example of the effect of asymmetries, we consider the simple case of load resistor mismatch. Depicted in Fig. 10.45(a) for a MOS pair,5 this imperfection leads to a difference between Vout1 and Vout2 . We must compute the change in ID1 and ID2 and multiply the result by RD and RD + RD .

4 5

Interestingly, older literature has considered this effect troublesome. We have chosen a MOS pair here to show that the treatment is the same for both technologies.

10.5 Common-Mode Rejection

439

VDD R D + ΔR D

RD V out1

ΔV

Vout2 M1

V CM

P

M2

I SS

Figure 10.45

R SS

MOS pair with asymmetric loads.

How do we determine the change in ID1 and ID2 ? Neglecting channel-length modulation, we first observe that ID1 =

W 1 μnCox (VGS1 − VTH )2 2 L

(10.176)

W 1 (10.177) μnCox (VGS2 − VTH )2 , 2 L concluding that ID1 must be equal to ID2 because VGS1 = VGS2 and hence VGS1 = VGS2 . In other words, the load resistor mismatch does not impact the symmetry of currents carried by M1 and M2 .6 Writing ID1 = ID2 = ID and VGS1 = VGS2 = VGS , we recognize that both ID1 and ID2 flow through RSS , creating a voltage change of 2ID RSS across it. Thus, ID2 =

VCM = VGS + 2ID RSS and, since VGS = ID/gm,

VCM = ID

That is, ID =

1 + 2RSS . gm

VCM . 1 + 2RSS gm

(10.178)

(10.179)

(10.180)

Produced by each transistor, this current change flows through both RD and RD + RD , thereby generating a differential output change of Vout = Vout1 − Vout2 = ID RD − ID (RD + RD )

(10.182)

= −ID · RD

(10.183)

=−

6

But with λ = 0, it would.

(10.181)

VCM RD . 1 + 2RSS gm

(10.184)

440

Chapter 10 Differential Amplifiers It follows that

Vout RD . V = 1 CM + 2RSS gm

(10.185)

(This result can also be obtained through small-signal analysis.) We say the circuit exhibits “common mode to differential mode (DM) conversion” and denote the above gain by ACM−DM . In practice, we strive to minimize this corruption by maximizing the output impedance of the tail current source. For example, a bipolar current source may employ emitter degeneration and a MOS current source may incorporate a relatively long transistor. It is therefore reasonable to assume RSS 1/gm and RD . 2RSS

ACM−DM ≈

Example 10.27

(10.186)

Determine ACM−DM for the circuit shown in Fig. 10.46. Assume VA = ∞ for Q 1 and Q 2 .

VCC R C + ΔR C

RC V out1

Vout2 Q1

V CM

P

Q2 R out3

Vb

Q3 R1

Figure 10.46 Solution

Recall from Chapter 5 that emitter degeneration raises the output impedance to Rout3 = [1 + gm3 (R1 ||rπ 3 )]rO3 + R1 ||rπ 3 .

(10.187)

Replacing this value for RSS in Eq. (10.186) yields ACM−DM =

Exercise

RC . 1 + 2{[1 + gm3 (R1 ||rπ 3 )]rO3 + R1 ||rπ 3 } gm1

(10.188)

Calculate the above result if R1 → ∞.

The mismatches between the transistors in a differential pair also lead to CM-DM conversion. This effect is beyond the scope of this book [1].

10.6 Differential Pair with Active Load

441

While undesirable, CM-DM conversion cannot be simply quantified by ACM−DM . If the circuit provides a large differential gain, ADM , then the relative corruption at the output is small. We therefore define the “common-mode rejection ratio” (CMRR) as CMRR =

ADM ACM−DM

.

(10.189)

Representing the ratio of “good” to “bad,” CMRR serves as a measure of how much wanted signal and how much unwanted corruption appear at the output if the input consists of a differential component and common-mode noise.

Example 10.28

Calculate the CMRR of the circuit in Fig. 10.46.

Solution

For small mismatches (e.g., 1%), RC RC , and the differential gain is equal to gm1 RC . Thus,

gm1 RC 1 CMRR = + 2[1 + gm3 (R1 ||rπ 3 )]rO3 + 2(R1 ||rπ 3 ) . (10.190) RC gm1

Exercise

Determine the CMRR if R1 → ∞.

10.6

DIFFERENTIAL PAIR WITH ACTIVE LOAD In this section, we study an interesting combination of differential pairs and current mirrors that proves useful in many applications. To arrive at the circuit, let us first address a problem encountered in some cases. Recall that the op amps used in Chapter 8 have a differential input but a single-ended output [Fig. 10.47(a)]. Thus, the internal circuits of such op amps must incorporate a stage

VCC RC

RC

X

V in1 V in2

Y

V in1 Vout

(a)

V in2

(b)

(a) Circuit with differential input and single-ended output, (b) possible implementation of (a).

Figure 10.47

Vout

442

Chapter 10 Differential Amplifiers that “converts” a differential input to a single-ended output. We may naturally consider the topology shown in Fig. 10.47(b) as a candidate for this task. Here, the output is sensed at node Y with respect to ground rather than with respect to node X.7 Unfortunately, the voltage gain is now halved because the signal swing at node X is not used. We now introduce a topology that serves the task of “differential to single-ended” conversion while resolving the above issues. Shown in Fig. 10.48, the circuit employs a symmetric differential pair, Q 1 -Q 2 , along with a current-mirror load, Q 3 -Q 4 . (Transistors Q 3 and Q 4 are also identical.) The output is sensed with respect to ground.

VCC Q3

Q4

N V in1

Q1

Q2

Vin2 Vout

I EE

Figure 10.48

Differential pair with active load.

10.6.1 Qualitative Analysis It is instructive to first decompose the circuit of Fig. 10.48 into two sections: the input differential pair and the current-mirror load. As depicted in Fig. 10.49(a) (along with a fictitious load RL ), Q 1 and Q 2 produce equal and opposite changes in their collector currents in response to a differential change at the input, creating a voltage change of IRL across RL . Now consider the circuit in Fig. 10.49(b) and suppose the current drawn from Q 3 increases from IEE/2 to IEE/2 + I. What happens? First, since the small-signal impedance seen at node N is approximately equal to 1/gm3 , VN changes by I/gm3 (for small I). Second, by virtue of current mirror action, the collector current of Q 4 also increases by I. As a result, the voltage across RL changes by IRL . ΔI R L I EE 2

VCM

+ ΔV

I EE

+ ΔI

2

Q1

Q2

P

– ΔI

VCC

RL

Q3

Vb VCM

Q4

N – ΔV

I EE 2

ΔI R L

+ ΔI

RL

I EE (a)

(b)

(a) Response of input pair to input change, (b) response of active load to current change.

Figure 10.49

7

In practice, additional stages precede this stage so as to provide a high gain.

10.6 Differential Pair with Active Load

443

VCC Q3

I EE 2

VCM

Q4

N

I C4

+ ΔI

I EE

+ ΔV

2

Q1

– ΔI

VCM

Q2

RL

Vout

– ΔV

P I EE

Figure 10.50

Detailed operation of pair with active load.

In order to understand the detailed operation of the circuit, we apply small, differential changes at the input and follow the signals to the output (Fig. 10.50). The load resistor, RL , is added to augment our intuition but it is not necessary for the actual operation. With the input voltage changes shown here, we note that IC 1 increases by some amount I and IC 2 decreases by the same amount. Ignoring the role of Q 3 and Q 4 for the moment, we observe that the fall in IC 2 translates to a rise in Vout because Q 2 draws less current from RL . The output change can therefore be an amplified version of V. Let us now determine how the change in IC 1 travels through Q 3 and Q 4 . Neglecting the base currents of these two transistors, we recognize that the change in IC 3 is also equal to I. This change is copied into IC 4 by virtue of the current mirror action. In other words, in response to the differential input shown in Fig. 10.50, IC 1 , |IC 3 |, and |IC 4 | increase by I. Since Q 4 “injects” a greater current into the output node, Vout rises. In summary, the circuit of Fig. 10.50 contains two signal paths, one through Q 1 and Q 2 and another through Q 1 , Q 3 and Q 4 [Fig. 10.51(a)]. For a differential input change, each path experiences a current change, which translates to a voltage change at the output node. The key point here is that the two paths enhance each other at the output; in the above example, each path forces Vout to increase. Our initial examination of Q 3 and Q 4 in Fig. 10.50 indicates an interesting difference with respect to current mirrors studied in Chapter 9: here Q 3 and Q 4 carry signals in

VCC Q3

Q4 Path 1

N V in1

Q1

Path 2

Q2

I EE

Figure 10.51

Signal paths in pair with active load.

Vin2 Vout

444

Chapter 10 Differential Amplifiers VCC Vb

Q3

V in1

Q4 Vout Q1

Q2

Vin2

P I EE (a)

Figure 10.52

Differential pair with current-source loads.

addition to bias currents. This also stands in contrast to the current-source loads in Fig. 10.52, where the base-emitter voltage of the load transistors remains constant and independent of signals. Called an “active load” to distinguish it from the load transistors in Fig. 10.52, the combination of Q 3 and Q 4 plays a critical role in the operation of the circuit. The foregoing analysis directly applies to the CMOS counterpart, shown in Fig. 10.53. Specifically, in response to a small, differential input, ID1 rises to ISS/2 + I and ID2 falls to ISS/2 − I. The change in ID2 tends to raise Vout . Also, the change in ID1 and ID3 is copied into ID4 , increasing |ID4 | and raising Vout . (In this circuit, too, the current mirror transistors are identical.) VDD M3 + ΔV

M4

M1

M2

– ΔV

RL

Vout

I SS

Figure 10.53

MOS differential pair with active load.

10.6.2 Quantitative Analysis The existence of the signal paths in the differential to single-ended converter circuit suggests that the voltage gain of the circuit must be greater than that of a differential topology in which only one output node is sensed with respect to ground [e.g., Fig. 10.47(b)]. To confirm this conjecture, we wish to determine the small-signal single-ended output, vout , divided by the small-signal differential input, vin1 − vin2 . We deal with a CMOS implementation here (Fig. 10.54) to demonstrate that both CMOS and bipolar versions are treated identically. The circuit of Fig. 10.54 presents a quandary. While the transistors themselves are symmetric and the input signals are small and differential, the circuit is asymmetric. With the diode-connected device, M3 , creating a low impedance at node A, we expect a relatively small voltage swing—on the order of the input swing—at this node. On the other hand, transistors M2 and M4 provide a high impedance and hence a large voltage swing at the output node. (After all, the circuit serves as an amplifier.) The asymmetry resulting from the very different voltage swings at the drains of M1 and M2 disallows grounding node P for small-signal analysis. We present two approaches to solving this circuit.

10.6 Differential Pair with Active Load VDD M4

M3 A V in1

445

Vout Vin2

M2

M1 P

I SS

Figure 10.54

MOS pair for small-signal analysis.

Approach I Without a half circuit available, the analysis can be performed through the use of a complete small-signal model of the amplifier. Referring to the equivalent circuit shown in Fig. 10.55, where the dashed boxes indicate each transistor, we perform the analysis in two steps. In the first step, we note that iX and i Y must add up to zero at node P −1 and hence iX = −i Y . Also, vA = −iX (gmP ||rOP ) and −i Y =

vout + gmP vA rOP

=

vout − gmP iX rOP

(10.191)

1 rOP g

(10.192)

mP

= iX .

(10.193)

Thus, vout

iX =

rOP 1 + gmP

. 1 rOP g

(10.194)

mP

M3

M4

r OP

1 g mP

A

v in1

v1

vA iX g

v mN 1

v mP A

r OP v out

iY r ON r ON

M1

Figure 10.55

g

P

g

v mN 2

v2

v in2

M2

Small-signal equivalent circuit of differential pair with active load.

In the second step, we write a KVL around the loop consisting of all four transistors. The current through rON of M1 is equal to iX − gmN v1 and that through rON of M2 equal to i Y − gmN v2 . It follows that −vA + (iX − gmN v1 )rON − (i Y − gmN v2 )rON + vout = 0.

(10.195)

Since v1 − v2 = vin1 − vin2 and iX = −i Y , −vA + 2iX rON − gmN rON (vin1 − vin2 ) + vout = 0.

(10.196)

446

Chapter 10 Differential Amplifiers Substituting for vA and iX from above, we have

vout vout 1

rOP + 2rON 1 1 gmP rOP rOP rOP 1 + gmP rOP 1 + gmP gmP gmP + vout = gmN rON (vin1 − vin2 ).

(10.197)

Solving for vout yields

1 rOP rOP 1 + gmP gmP = gmN rON . 2rON + 2rOP

vout vin1 − vin2

(10.198)

This is the exact expression for the gain. If gmP rOP 1, then vout = gmN (rON ||rOP ). vin1 − vin2

(10.199)

The gain is indepedent of gmP and equal to that of the fully-differential circuit. In other words, the use of the active load has restored the gain. Approach II∗ In this approach, we decompose the circuit into sections that more easily lend themselves to analysis by inspection. As illustrated in Fig. 10.56(a), we first seek a Thevenin equivalent for the section consisting of vin1 , vin2 , M1 and M2 , assuming vin1 and vin2 are differential. Recall that vThev is the voltage between A and B in the “open-circuit condition” [Fig. 10.56(b)]. Under this condition, the circuit is symmetric, resembling the VDD M3

M4

A

B

v in1

M2

M1

v out v in2

v Thev

R Thev

P I SS

(a)

iX

v Thev A v in1

M2

P

iX

M1

B M1

vX

v in2

v1

M2 r O1 r O2 P

I SS (b)

Figure 10.56

pair.

v2

I SS (c)

(a) Thevenin equivalent, (b) Thevenin voltage, and (c) Thevenin resistance of input

10.6 Differential Pair with Active Load

447

topology of Fig. 10.16(a). Equation (10.92) thus yields vThev = −gmN rON (vin1 − vin2 ),

(10.200)

where the subscript N refers to NMOS devices. To determine the Thevenin resistance, we set the inputs to zero and apply a voltage between the output terminals [Fig. 10.56(c)]. Noting that M1 and M2 have equal gate-source voltages (v1 = v2 ) and writing a KVL around the “output” loop, we have (iX − gm1 v1 )rO1 + (iX + gm2 v2 )rO2 = vX

(10.201)

RThev = 2rON .

(10.202)

and hence

The reader is encouraged to obtain this result using half circuits as well. Having reduced the input sources and transistors to a Thevenin equivalent, we now compute the gain of the overall amplifier. Figure 10.57 depicts the simplified circuit, where the diode-connected transistor M3 is replaced with (1/gm3 )||rO3 and the output impedance of M4 is drawn explicitly. The objective is to calculate vout in terms of vThev . Since the voltage at node E with respect to ground is equal to vout + vThev , we can view vA as a divided version of vE : 1 rO3 g m3 vA = (vout + vThev ). (10.203) 1 rO3 + RThev gm3 Given by gm4 vA , the small-signal drain current of M4 must satisfy KCL at the output node: vout vout + vThev + = 0, (10.204) gm4 vA + 1 rO4 rO3 + RThev gm3

r O3

A

Figure 10.57

VDD

1 g m3

M4 R Thev v Thev

B

E

v out r O4

Simplified circuit for calculation of voltage gain.

where the last term on the left-hand side represents the current flowing through RThev . It follows from Eqs. (10.204) and (10.205) that ⎛ ⎞ 1 r O3 ⎜ ⎟ 1 g ⎜gm4 ⎟ (vout + vThev ) + vout = 0. m3 + (10.205) ⎝ ⎠ 1 1 rO4 rO3 + RThev rO3 + RThev gm3 gm3 ∗

This section can be skipped in a first reading.

448

Chapter 10 Differential Amplifiers Recognizing that 1/gm3 rO3 , and 1/gm3 RThev and assuming gm3 = gm4 = gmp and rO3 = rO4 = rOP , we reduce Eq. (10.206) to 2 RThev

(vout + vThev ) +

vout = 0. rOP

Equations (10.201) and (10.207) therefore give

1 gmN rON (vin1 − vin2 ) 1 = + vout rON rOP rON

(10.206)

(10.207)

and hence vout = gmN (rON ||rOP ). vin1 − vin2

(10.208)

The gain is independent of gmp . Interestingly, the gain of this circuit is the same as the differential gain of the topology in Fig. 10.51(b). In other words, the path through the active load restores the gain even though the output is single-ended. Example 10.29

In our earlier observations, we surmised that the voltage swing at node A in Fig. 10.56 is much less than that at the output. Prove this point.

Solution

As depicted in Fig. 10.58, KCL at the output node indicates that the total current drawn by M2 must be equal to −vout/rO4 − gm4 vA . This current flows through M1 and hence through M3 , generating

1 vA = −(vout /rO4 + gm4 vA ) rO3 . (10.209) gm3

r O3

VDD

1 g m3

M4

A – v in

r O4 v out

M2

M1

+v in

P I SS

Figure 10.58

That is, vA ≈ −

vout , 2gmP rOP

revealing that vA is indeed much less that vout . Exercise

Calculate the voltage gain from the differential input to node A.

(10.210)

Problems

449

PROBLEMS 10.1. To calculate the effect of ripple at the output of the circuit in Fig. 10.1, we can assume VCC is a small-signal “input” and determine the (small-signal) gain from VCC to Vout . Compute this gain, assuming VA < ∞.

10.4. Repeat Problem 10.3 for the circuit depicted in Fig. 10.61. Also, plot the voltage at node P as a function of time. 10.5. Repeat Problem 10.3 for the topology shown in Fig. 10.62. 10.6. Repeat Problem 10.3 for the topology shown in Fig. 10.63.

10.2. Repeat Problem 10.1 for the stages shown in Fig. 10.59. Assume VA < ∞ and λ > 0.

10.7. Determine common-mode level voltage for Fig. 10.64. RC 1 = RC 2 = 1 k, Q1 and Q2 are identical; VCC = 5 V, IC = 2 mA; (a) In absence of signals (b) In presence of signals with Vin1 = Vin2 .

10.3. Find output voltages at X and Y for circuits in Fig. 10.60 for I1 = I0 cos ωt + I0 , I2 = −I0 cos ωt + I0 . Determine peak-topeak voltages and common-mode level. VCC

VDD

RC Vout V in

V in

Vout

Vb

Q1

VCC

RD V in

Q1

Vout RS

I EE

RS

(a)

M1

Vout

M1

I EE

VDD V in

(b)

(c)

(d)

Figure 10.59

VCC RC

RC X

VCC RC

RC

Y

X

VCC

Y

X

I1

I2

I1

I2

R1

R1

R1

R1

IT

VCC

RC

RC

R1

Y

I1

I2

R1

R1

P

RC

RP

RC Y

X I1

(a)

(b)

(c)

Figure 10.60

Figure 10.61 VCC VCC

RC X I1

Figure 10.62

I2

RC

I1 X

I2

RC 1

Y

RC

Y

VCC

I2 RC Vb

Figure 10.63

RC2

X Vin1

Y Q1

Figure 10.64

Q2

Vin 2

450

Chapter 10 Differential Amplifiers RC V1

RC RC

V2

P

RC

V1

RC V2

(a)

P

V1

RC V2

R1 (b)

P I1

(c)

Figure 10.65

* 10.8. Assuming V1 = V0 cos ωt + V0 and V2 = Gm? At what value of Vin1 − Vin2 does Gm −V0 cos ωt + V0 , plot VP as a function of drop by a factor of two with respect to its time for the circuits shown in Fig. 10.65. maximum value? Assume IT is constant. *10.16. With the aid of Eq. (10.78), we can compute the small-signal voltage gain of the 10.9. In Fig. 10.7, IEE experiences a change of bipolar differential pair: I. How do VX , VY , and VX − VY change? 10.10. Consider the circuit of Fig. 10.9(a) and assume IEE = 1 mA. What is the maximum allowable value of RC ifQ 1 must remain in the active region?

Av =

∂(Vout1 − Vout2 ) . ∂(Vin1 − Vin2 )

(10.213)

Determine the gain and compute its value if Vin1 − Vin2 contains a dc component of 30 mV.

10.11. In the circuit of Fig. 10.9(b), RC = 500 . What is the maximum allowable value of IEE if Q 2 must remain in the active region? **10.17. In Example 10.9, RC = 500 , IEE = 1 mA, and VCC = 2.5 V. Assume 10.12. What happens to the characteristics depicted in Fig. 10.10 if (a) IEE is halved, (b) VCC rises by V, or (c) RC is halved? 10.13. In the circuit of Fig. 10.12, the small-signal transconductance of Q 2 falls as Vin1 − Vin2 rises because IC 2 decreases. Using Eq. (10.58), determine the input difference at which the transconductance of Q 2 drops by a factor of 2.

Vin1 = V0 sin ωt + VCM

(10.214)

Vin2 = −V0 sin ωt + VCM ,

(10.215)

where VCM = 1 V denotes the input common-mode level. (a) If V0 = 2 mV, plot the output waveforms (as a function of time). (b) If V0 = 50 mV, determine the time t1 at which one transistor carries 95% of the tail current. Plot the output waveforms.

10.14. Suppose the input differential signal applied to a bipolar differential pair must not change the transconductance (and hence the bias current) of each transis- **10.18. The study in Example 10.9 suggests that a tor by more than 10%. From Eq. (10.58), differential pair can convert a sinusoid to determine the maximum allowable input. a square wave. Using the circuit parameters given in Problem 10.17, plot the out*10.15. It is possible to define a differential put waveforms if V0 = 80 mV or 160 mV. transconductance for the bipolar differenExplain why the output square wave betial pair of Fig. 10.12: comes “sharper” as the input amplitude ∂(IC 1 − IC 2 ) increases. Gm = . (10.212) ∂(Vin1 − Vin2 ) 10.19. Repeat the small-signal analysis of Fig. 10.15 for the circuit shown in Fig. 10.66. From Eqs. (10.58) and (10.60), compute (First, prove that P is still a virtual Gm and plot the result as a function of ground.) Vin1 − Vin2 . What is the maximum value of

Problems

10.21. For Fig. 10.67 with all the data same as Problem 10.20, calculate the commonmode voltage gain, and determine CMKR.

VCC RC

RC Vout

V in1

Q1 P I EE

10.22. All transistors in Fig. 10.68 are having β = 90, Ri = 25 = hie, at IC = 1.2 mA circuit has CMRR 120. Determine differential gain and common-mode gain of circuit.

Vin2

Q2

R EE

5V

Figure 10.66

10.20. For Fig. 10.67, RC = 40 k, RE = 8 k, rS = 9 k, β = 2200, R0 = 400 k (for transistor) and resistances (rbb + rπ ) in model = 45 k. Find differential voltage gain.

RC

I c1

I c2

V01 Q1

rS Vin1

IE

Vout Q1

Vin1

Q2

3 mA RE

RC V02

Q2

Figure 10.68

**10.23. Assuming perfect symmetry and VA < ∞, compute the differential voltage gain of each stage depicted in Fig. 10.69.

VCC

VCC Q4

RC

R2

Q1

Q2

RC Vout

Vout V in1

R

–5 V rS Vin2

RE

Q3

V in1

Vin2

I EE

Q2

P I EE

(a)

Vin2

R2

R1 Q1

P

(b)

VCC R1 Q3 V in1

Vout

Q1

(c)

Figure 10.69

VCC

R2

R2

R1 Q4 Q2

P I EE

Vin2

Q3

Figure 10.67

R1

RC

1k 1k

VCC RC

451

Q3 Vin2

V in1

Q4 Vout Q1

Q2 P I EE (d)

Vin2

452

Chapter 10 Differential Amplifiers

*10.24. Consider the differential pair illustrated in Fig. 10.70. Assuming perfect symmetry and VA = ∞, (a) Determine the voltage gain. (b) Under what condition does the gain become independent of the tail currents? This is an example of a very linear circuit because the gain does not vary with the input or output signal levels.

Q3

VCC

Vin2

10.30. An adventurous student constructs the circuit shown in Fig. 10.72 and calls it a “differential amplifier” because ID ∝ (Vin1 − Vin2 ). Explain which aspects of our differential signals and amplifiers this circuit violates.

RC Vout

V in1

Q1

Q2 RE

I EE

10.28. For a NMOS differential pair providing voltage gain of 7, and RD (drain resistance) of 400 , (W/L) ratio of 1400, λ = 0, and VDD = 2 V, find minimum common-mode input voltage level. 10.29. What will be the maximum allowable input common-mode input voltage for VTh = 0.38 V?

Q4

RC

What is the minimum allowable supply voltage if the transistors must remain in saturation? Assume VTH,n = 0.5 V.

VDD

I EE

RD Vout

Figure 10.70

10.25. Assuming perfect symmetry and VA < ∞, compute the differential voltage gain of each stage depicted in Fig. 10.71. You may need to compute the gain as Av = −GmRout in some cases. 10.26. Consider the MOS differential pair of Fig. 10.24. What happens to the tail node voltage if (a) the width of M1 and M2 is doubled, (b) ISS is doubled, (c) the gate oxide thickness is doubled? 10.27. In the MOS differential pair of Fig. 10.24, VCM = 1 V, ISS = 1 mA, and RD = 1 k.

V in1

M1

Figure 10.72

10.31. NMOS differential amplifier biased at 0.5 mA, transistors with (W/L) ratio of 40, Kn = 100 μA/V2 , VA = 12 V, RD = 10 k, find (VGS − Vt ), gm, r0 and differential voltage gain. 10.32. Examine Eq. (10.134) for the following cases: (a) ID1 = 0, (b) ID1 = ISS/2, and (c) ID1 = ISS . Explain the significance of these cases.

VCC RC

VCC RC

RC

RC

Vout V in1

Q1

RE R SS (a)

Figure 10.71

Vout Q2

RE P

Vin2

Vin2

V in1

Q1

R2

R1 RE P

RE R SS (b)

Q2

Vin2

Problems 10.33. Prove that the right-hand side of Eq. (10.139) is always negative if the solution with the negative sign is considered.

453

oxide thickness of the transistor is doubled, (b) the threshold voltage is halved, (c) ISS and W/L are halved.

10.34. From Eq. (10.142), determine the value *10.39. Assuming that the mobility of carriers falls of Vin1 − Vin2 such that ID1 − I√ at high temperatures, explain what hapD2 = ISS . pens to the characteristics of Fig. 10.31 as Verify that is result is equal to 2 times the temperature rises. the equilibrium overdrive voltage. 10.35. From Eq. (10.142), compute the smallsignal transconductance of a MOS differential pair, defined as ∂(ID1 − ID2 ) Gm = . (10.216) ∂(Vin1 − Vin2 )

10.40. For Fig. 10.74, find voltage gain assuming λ3 = λ1 = 0.01 V−1 and Id3 = Id4 = 1 mA all gm ’s = 0.1 mS. VDD

Plot the result as a function of Vin1 − Vin2 and determine its maximum value.

M3

Vout

**10.36. Suppose a new type of MOS transistor has been invented that exhibits the following I-V characteristic: ID = γ (VGS − VTH )3 ,

Vin 1

RD Vout

V in1

T1

T2

Vin2

Vin 2

M2

ISS

where γ is a proportionality factor. Figure 10.73 shows a differential pair employing such transistors.

RD

M1

(10.217)

VDD

M4

Figure 10.74

10.41. Calculate voltage gain of circuit in Fig. 10.75 for given data Kn = μm C ox = 100 μA/v2 ; biasing VGS 1 = VGS 2 = 1.1 V, VTh = 0.4 V. VDD (5 V)

I SS

Vout Figure 10.73

(a) What similarities exist between this circuit and the standard MOS differential pair? (b) Calculate the equilibrium overdrive voltage of T1 and T2 . (c) At what value of Vin1 − Vin2 does one transistor turn off? *10.37. Using the result obtained in Problem 10.35, calculate the value of Vin1 − Vin2 at which the transconductance drops by a factor of 2. *10.38. Explain what happens to the characteristics shown in Fig. 10.31 if (a) the gate

Vin 1

M1 5/1

M3 3/1

M4 M2 3/1 5/1

Q

Vin 2

P

ISS 1 1.5 mA

ISS 2 1 mA

Figure 10.75

10.42. For Fig. 10.76, draw small-signal model when common-mode signal is applied to V 1 and V 2 . Determine small-signal parameters. V ref provides bias current of 2.5 mA to nFET current source transistors when biased in saturation.

VT = 0.4 V, VA = 50 V, Kn = 40 mA/V2

454

Chapter 10 Differential Amplifiers VCC

VDD

M5

W/L = 3 /1

W/L = 3 /1

M3

M4

W/L = 2/1 M1

V1

2 /1 M2

Vout Q3

Q4

Vb

V2

V in1

Q1

Vin2

Q2 I EE

Vref

M6

W/L = 2 /1 Figure 10.78

*10.47. Calculate the voltage gain of the degenerated pair depicted in Fig. 10.79. (Hint: Av = −GmRout .)

Figure 10.76

10.43. The cascode differential pair of Fig. 10.37(a) must achieve a voltage gain of 4000. If Q 1 –Q 4 are identical and β = 100, what is the minimum required Early voltage? 10.44. For Fig. 10.42 (a), find the voltage gain if R1 = R2 = 5 k gm5 = 0.01 S, all o/p resistances of transistors (r0 ) = 300 k, gm3 = 0.01 S.

VCC

Vout Q3

Q4

Vb V in1

Q1 RS

10.45. Repeat Problem 10.44 for the circuit shown in Fig. 10.77. Figure 10.79

VCC

Vout Q3

Q4

Vb V in1

RP Q1

RP Q2

Vin2

Q2

Vb

*10.48. Realizing that the circuit of Fig. 10.78 suffers from a low gain, the student makes the modification shown in Fig. 10.80. Calculate the voltage gain of this topology. VCC

Vin2

I EE

Q3

Q4

Vb Vout

Figure 10.77 V in1

**10.46. A student has mistakenly used pnp cascode transistors in a differential pair as illustrated in Fig. 10.78. Calculate the voltage gain of the circuit. (Hint: Av = −GmRout .)

Q1

Q2 I EE

Figure 10.80

Vin2

Problems **10.49. The telescopic cascode of Fig. 10.38 is to operate as an op amp having an openloop gain of 800. If Q 1 -Q 4 are identical and so are Q 5 -Q 8 , determine the minimum allowable Early voltage. Assume βn = 2β p = 100 and VA,n = 2VA, p . 10.50. For Fig. 10.81, MOSFET differential amplifier with Cascode active load, determine differential mode voltage gain.

V b3 V b2

M7

M8

M5

455

VDD

M6 Vout

M3 V b1

M4

V in1

M1

Vin2

M2

VTN = 0.4 V, kn = 100 μA/v 2

λN = 0.02 V−1 (W/L)n = 15 VTP = −0.4 V, K p = 50 μA/v 2 λP = 0.02 V−1 . VDD = 5 V IQ = 250 μA VDD

V1

M5

M6

M3

M4

M1

R 01 R 02 M2

Vout V2

I SS

Figure 10.82

10.53. Consider the circuit of Fig. 10.43(a) and replace REE with two parallel resistors equal to 2REE places on the two sides of the current source. Now draw a vertical line of symmetry through the circuit and decompose it to two common-mode half circuits, each having a degeneration resistor equal to 2REE . Prove that Eq. (10.175) still holds. 10.54. The bipolar differential pair depicted in Fig. 10.83 must exhibit a common-mode gain of less than 0.01. Assuming VA = ∞ for Q 1 and Q 2 but VA < ∞ for Q 3 , prove that RC IC < 0.02(VA + VT ).

IQ

VCC RC

Figure 10.81

(10.218)

v out1

RC v out2

Q1 Q2 **10.51. A student adventurously modifies a v CM CMOS telescopic cascode as shown in Fig. 10.82, where the PMOS cascode tranI EE Vb sistors are replaced with NMOS devices. Q3 Assuming λ > 0, compute the voltage gain of the circuit. (Hint: the impedance seen Figure 10.83 looking into the source of M5 or M6 is not equal to 1/gm||rO .) *10.55. Compute the common-mode gain of the MOS differential pair shown in Fig. 10.84. 10.52. The MOS telescopic cascode of Fig. Assume λ = 0 for M1 and M2 but λ = 0 for 10.41(a) is designed for a voltage gain M3 . Prove of 200 with a tail current of 1 mA. If μnCox = 100 μA/V2 , μ pCox = 50 μA/V2 , −RD ISS ACM = , (10.219) λn = 0.1 V−1 , and λ p = 0.2 V−1 , determine 2 + (V − V ) GS TH eq. (W/L)1 = · · · = (W/L)8 . λ

456

Chapter 10 Differential Amplifiers where (VGS − VTH )eq. denotes the equilibrium overdrive of M1 and M2 .

10.57. Repeat Problem 10.56 for the circuits shown in Fig. 10.86.

VDD RD

*10.58. Compute the common-mode rejection ratio of the stages illustrated in Fig. 10.86 and compare the results. For simplicity, neglect channel-length modulation in M1 and M2 but not in other transistors.

RD

X V in1

Y

Vb

Vin2

M2

M1

10.56. For Fig. 10.75, determine common-mode voltage gain, different mode gain and CMRR ratio.

M3

10.59. Explain how voltage gain is further improved in Fig. 10.87 compared to Fig. 10.81 in Problem 10.50.

Figure 10.84

VDD V b1

M3

V in1

VDD V b3

M4 Vout

V b1 M2

M1 V b2

M5

V b3

M6

Vin2

M6

M5 M3

V in1

M4 Vout

V b2

(a)

Vin2

M2

M1

M7 (b)

Figure 10.85

VDD

VDD R D + ΔR D

RD Vout 1 Vin1

VDD

Vout 2 M1

P

M2

Vin 2

Vout1

Vout2 M1

P

M2

M3

(a) Figure 10.86

M5

M6

M3

M4

Vin2

Vbias V1

V b1

M8

RD + ΔRD

RD

V in 1

M7

V b2

M3

V b3

M4

M1

M2

IQ

(b) Figure 10.87

Vout V2

Problems 10.60. Analyze Fig. 10.88 BJT differential amplifier with active load for common-mode signal.

Q3 I 0c Q1

Vin1

Q5

Q2

Q4 I 0c 1

i0

Vin 2

10.63. Figure 10.91 shows bipolar differential amplifier with active load. Analyze the circuit for differential mode signal gain.

Q4

Q3

Vout

i0

Isc

VE

2ic REE

457

V i 1 = Vdd 2

Q 1 gm2 Vid 2

Vout Vi2 = Vdd 2

Q2

RL

REE

Figure 10.88

Figure 10.91 10.61. Neglecting channel-length modulation, compute the small-signal gains vout/i 1 and vout/i 2 in Fig. 10.89. **10.64. Determine the output impedance of the circuit shown in Fig. 10.54. Assume VDD gmrO 1. M3

M4

Vout I1

RL

I2

Figure 10.89

**10.62. Consider the circuit of Fig. 10.90, where the inputs are tied to a common-mode level. Assume M1 and M2 are identical and so are M3 and M4 . (a) Neglecting channel-length modulation, calculate the voltage at node N. (b) Invoking symmetry, determine the voltage at node Y. (c) What happens to the results obtained in (a) and (b) if VDD changes by a small amount V?

Design Problems 10.65. The bipolar differential pair of Fig. 10.6(a) must operate with an input common-mode level of 1.2 V without driving the transistors into saturation. Design the circuit for maximum voltage gain and a power budget of 3 mW. Assume VCC = 2.5 V. 10.66. The differential pair depicted in Fig. 10.92 must provide a gain of 5 and a power budget of 4 mW. Moreover, the gain of the circuit must change by less than 2% if the collector current of either transistor changes by 10%. Assuming VCC = 2.5 V and VA = ∞, design the circuit. (Hint: a 10% change in IC leads to a 10% change in gm.)

VDD M3 N

RC

Y M1

VCM I SS

Figure 10.90

VCC

M4

P

M2

RC Vout

V in1

Q1 I EE

Figure 10.92

Vin2

Q2 RE

I EE

458

Chapter 10 Differential Amplifiers

10.67. Design the circuit of Fig. 10.93 for a gain of 50 and a power budget of 1 mW. Assume VA,n = 6 V and VCC = 2.5 V.

VDD

VCC Vb

V b1

Q4

Q3 V in1

μnCox = 100 μA/V2 , μ pCox = 100 μA/V2 , and VDD = 1.8 V.

Vout Q1

M4

M3

V in1

Vout Vin2

M2

M1

Vin2

Q2

V b2

M5

I EE

Figure 10.95 Figure 10.93

10.68. Design the circuit of Fig. 10.94 for a gain of 100 and a power budget of 1 mW. Assume VA,n = 10 V, VA, p = 5 V, and VCC = 2.5 V. Also, R1 = R2 . VCC Q3

Q4 R1

R2

Vout V in1

Q1

Q2

Vin2

P

10.71. Design the telescopic cascode of Fig. 10.38(a) for a voltage gain of 2000. Assume Q 1 -Q 4 are identical and so are Q 5 -Q 8 . Also, βn = 100, β p = 50, VA,n = 5 V, VCC = 2.5 V, and the power budget is 2 mW. 10.72. The differential pair of Fig. 10.96 must achieve a CMRR of 60 dB (= 1000). Assume a power budget of 2 mW, a nominal differential voltage gain of 5, and neglecting channel-length modulation in M1 and M2 , compute the minimum required λ for M3 . Assume (W/L)1,2 = 10/0.18, μnCox = 100 μA/V2 , VDD = 1.8 V, and R/R = 2%.

I EE VDD

Figure 10.94

10.69. Design the MOS differential pair of Fig. 10.29 for an equilibrium overdrive voltage of 100 mV and a power budget of 2 mW. Select the value of RD to place the transistor at the edge of triode region for an input common-mode level of 1 V. Assume λ = 0, μnCox = 100 μA/V2 , VTH,n = 0.5 V, and VDD = 1.8 V. What is the voltage gain of the resulting design? 10.70. The differential pair depicted in Fig. 10.95 must provide a gain of 40. Assuming the same (equilibrium) overdrive for all of the transistors and a power dissipation of 2 mW, design the circuit. Assume λn = 0.1 V−1 , λ p = 0.2 V−1 ,

R D + ΔR D

RD v out1 V in1

v out2 M1

V b1

P

M2

Vin2

M3

Figure 10.96

10.73. Design the circuit of Fig. 10.54 for a voltage gain of 20 and a power budget of 1 mW with VDD = 1.8 V. Assume M1 operates at the edge of saturation if the input common-mode level is 1 V. Also, μnCox = 2μ pCox = 100 μA/V2 , VTH,n = 0.5 V, VTH, p = −0.4 V, λn = 0.5λ p = 0.1 V−1 .

Spice Problems

459

SPICE PROBLEMS In the following problems, use the MOS device models given in Appendix A. For bipolar transistors, assume IS,npn = 5 × 10−16 A, βnpn = 100, VA,npn = 5 V, IS,pnp = 8 × 10−16 A, βpnp = 50, VA,pnp = 3.5 V. 10.1. Consider the differential amplifier shown in Fig. 10.97, where the input CM level is equal to 1.2 V. (a) Adjust the value of Vb so as to set the output CM level to 1.5 V. (b) Determine the small-signal differential gain of the circuit. (Hint: to provide differential inputs, use an independent voltage source for one side and a voltage-dependent voltage source for the other.) (c) What happens to the output CM level and the gain if Vb varies by ±10 mV? VCC = 2.5 V Vb

Q4 Vout

V in1

Q1

Q2

1 mA

I EE

Vin2

(b) Determine the small-signal differential gain of the circuit. (c) Plot the differential input/output characteristic. VDD = 1.8 V M7 1 kΩ

M4

M3 V in1

Vout M1

M6

M5

Figure 10.98

10.3. Consider the circuit illustrated in Fig. 10.99. Assume a small dc drop across R1 and R2 . (a) Select the input CM level to place Q 1 and Q 2 at the edge of saturation. (b) Select the value of R1 (= R2 ) such that these resistors reduce the differential gain by no more than 20%.

VCC =2.5 V Q3

Figure 10.97

Q4 R1

10.2. The differential amplifier depicted in Fig. 10.98 employs two current mirrors to establish the bias for the input and load devices. Assume W/L = 10 μm/0.18 μm for M1 -M6 . The input CM level is equal to 1.2 V. (a) Select (W/L)7 so as to set the output CM level to 1.5 V. (Assume L7 = 0.18 μm.)

Vin2

M2

R2

Vout V in1

Q1

Q2

1 mA

I EE

Vin2

Figure 10.99

REFERENCE 1. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.

Chapter

11

Frequency Response

The need for operating circuits at increasingly higher speeds has always challenged designers. From radar and television systems in the 1940s to gigahertz microprocessors today, the demand to push circuits to higher frequencies has required a solid understanding of their speed limitations. In this chapter, we study the effects that limit the speed of transistors and circuits, identifying topologies that better lend themselves to high-frequency operation. We also develop skills for deriving transfer functions of circuits, a critical task in the study of stability and frequency compensation (12). We assume bipolar transistors remain in the active mode and MOSFETs in the saturation region. The outline is shown below.

Fundamental Concepts • Bode’s Rules • Association of Poles with Nodes • Miller’s Theorem

High-Frequency Models of Transistors

➤ • Bipolar Model

➤

Frequency Response of Circuits • CE/CS Stages

• MOS Model

• CB/CG Stages

• Transit Frequency

• Followers • Cascode Stage • Differential Pair

11.1

FUNDAMENTAL CONCEPTS 11.1.1 General Considerations What do we mean by “frequency response?” Illustrated in Fig. 11.1(a), the idea is to apply a sinusoid at the input of the circuit and observe the output while the input frequency is varied. As exemplified by Fig. 11.1(a), the circuit may exhibit a high gain at low frequencies but a “roll-off” as the frequency increases. We plot the magnitude of the gain as in Fig. 11.1(b) to represent the circuit’s behavior at all frequencies of interest. We may loosely call f1 the useful bandwidth of the circuit. Before investigating the cause of this roll-off,

460

11.1 Fundamental Concepts

Av

Roll-Off

f1 (a)

Figure 11.1

461

f

(b)

(a) Conceptual test of frequency response, (b) gain roll-off with frequency.

we must ask: why is frequency response important? The following examples illustrate the issue.

Example 11.1

Explain why people’s voices over the phone sound different from their voices in faceto-face conversation.

Solution

The human voice contains frequency components from 20 Hz to 20 kHz [Fig. 11.2(a)]. Thus, circuits processing the voice must accommodate this frequency range. Unfortunately, the phone system suffers from a limited bandwidth, exhibiting the frequency response shown in Fig. 11.2(b). Since the phone suppresses frequencies above 3.5 kHz, each person’s voice is altered. In high-quality audio systems, on the other hand, the circuits are designed to cover the entire frequency range.

20 Hz

20 kHz (a)

f

3.5 kHz f

400 Hz (b)

Figure 11.2 Exercise

Whose voice does the phone system alter more, men’s or women’s?

Example 11.2

When you record your voice and listen to it, it sounds somewhat different from the way you hear it directly when you speak. Explain why?

Solution

During recording, your voice propagates through the air and reaches the audio recorder. On the other hand, when you speak and listen to your own voice simultaneously, your voice propagates not only through the air but also from your mouth through your skull to your ear. Since the frequency response of the path through your skull is different

462

Chapter 11 Frequency Response from that through the air (i.e., your skull passes some frequencies more easily than others), the way you hear your own voice is different from the way other people hear your voice.

Exercise

Explain what happens to your voice when you have a cold.

Example 11.3

Video signals typically occupy a bandwidth of about 5 MHz. For example, the graphics card delivering the video signal to the display of a computer must provide at least 5 MHz of bandwidth. Explain what happens if the bandwidth of a video system is insufficient.

Solution

With insufficient bandwidth, the “sharp” edges on a display become “soft,” yielding a fuzzy picture. This is because the circuit driving the display is not fast enough to abruptly change the contrast from, e.g., complete white to complete black from one pixel to the next. Figures 11.3(a) and (b) illustrate this effect for a high-bandwidth and low-bandwidth driver, respectively. (The display is scanned from left to right.)

(a)

(b)

Figure 11.3 Exercise

What happens if the display is scanned from top to bottom?

What causes the gain roll-off in Fig. 11.1? As a simple example, let us consider the low-pass filter depicted in Fig. 11.4(a). At low frequencies,C1 is nearly open and the current through R1 nearly zero; thus, Vout = Vin . As the frequency increases, the impedance of C1 falls and the voltage divider consisting of R1 and C1 attenuates Vin to a greater extent. The circuit therefore exhibits the behavior shown in Fig. 11.4(b). As a more interesting example, consider the common-source stage illustrated in Fig. 11.5(a), where a load capacitance, CL , appears at the output. At low frequencies, the signal current produced by M1 prefers to flow through RD because the impedance of

Vout V in

R1

1.0

V in

C1

Vout f

Figure 11.4

(a) Simple low-pass filter, and (b) its frequency response.

11.1 Fundamental Concepts

463

VDD RD

V in Vout

V in

M1

m

CL

(a)

Figure 11.5

Vout g V in

RD

CL

(b)

(a) CS stage with load capacitance, (b) small-signal model of the circuit.

CL , 1/(CL s), remains high. At high frequencies, on the other hand, CL “steals” some of the signal current and shunts it to ground, leading to a lower voltage swing at the output. In fact, from the small-signal equivalent circuit of Fig. 11.5(b),1 we note that RD and CL are in parallel and hence: 1 Vout = −gmVin RD || . CL s

(11.1)

That is, as the frequency increases, the parallel impedance falls and so does the amplitude of Vout .2 The voltage gain therefore drops at high frequencies. The reader may wonder why we use sinusoidal inputs in our study of frequency response. After all, an amplifier may sense a voice or video signal that bears no resemblance to sinusoids. Fortunately, such signals can be viewed as a summation of many sinusoids with different frequencies (and phases). Thus, responses such as that in Fig. 11.5(b) prove useful so long as the circuit remains linear and hence superposition can be applied.

11.1.2 Relationship Between Transfer Function and Frequency Response We know from basic circuit theory that the transfer function of a circuit can be written as

s 1+ 1+ ωz1 H(s) = A0 s 1+ 1+ ωp1

s ... ωz2 , s ... ωp2

(11.2)

where A0 denotes the low-frequency gain because H(s) → A0 as s → 0. The frequencies ωzj and ωpj represent the zeros and poles of the transfer function, respectively. If the input to the circuit is a sinusoid of the form x(t) = A cos (2π ft) = A cos ωt, then the output can be expressed as y(t) = A|H( jω)|cos[ωt + H( jω)],

1

(11.3)

Channel-length modulation is neglected here. We use upper-case letters for frequency-domain quantities (Laplace transforms) even though they denote small-signal values. 2

464

Chapter 11 Frequency Response where H( jω) is obtained by making the substitution s = jω. Called the “magnitude” and the “phase,” |H( jω)| and H( jω) respectively reveal the frequency response of the circuit. In this chapter, we are primarily concerned with the former. Note that f (in Hz) and ω (in radians per second) are related by a factor of 2π. For example, we may write ω = 5 × 1010 rad/s = 2π(7.96 GHz).

Example 11.4

Determine the transfer function and frequency response of the CS stage shown in Fig. 11.5(a).

Solution

From Eq. (11.1), we have H(s) =

Vout 1 (s) = −gm RD || Vin CL s =

−gmRD . RDCL s + 1

(11.4)

(11.5)

For a sinusoidal input, we replace s = jω and compute the magnitude of the transfer function:3 Vout gmRD . (11.6) V = 2 2 in R C ω2 + 1 D

L

As expected, the gain begins at gmRD at low frequencies, rolling off as R2DC L2 ω2 becomes comparable with unity. At ω = 1/(RDCL ), Vout gmRD V = √ . 2 in Since 20 log (Fig. 11.6).

√

(11.7)

2 ≈ 3 dB, we say the −3 dB bandwidth of the circuit is equal to 1/(RDCL )

Vout V in

–3–dB Bandwidth

–3–dB Rolloff

1 R D CL

ω

Figure 11.6 Exercise

Derive the above results if λ = 0.

3

The magnitude of the complex number a + jb is equal to

√ a 2 + b2 .

11.1 Fundamental Concepts Example 11.5

465

Consider the common-emitter stage shown in Fig. 11.7. Derive a relationship among the gain, the −3 dB bandwidth, and the power consumption of the circuit. Assume VA = ∞. VCC RC Vout V in

Q1

CL

Figure 11.7 Solution

In a manner similar to the CS topology of Fig. 11.5(a), the bandwidth is given by 1/(RC CL ), the low-frequency gain by gmRC = (IC /VT )RC , and the power consumption by IC · VCC . For the highest performance, we wish to maximize both the gain and the bandwidth (and hence the product of the two) and minimize the power dissipation. We therefore define a “figure of merit” as 1 IC RC × Gain × Bandwidth VT RC CL = Power Consumption IC · VCC =

(11.8)

1 1 . VT · VCC CL

(11.9)

Thus, the overall performance can be improved by lowering (a) the temperature;4 (b) VCC but at the cost of limiting the voltage swings; or (c) the load capacitance. In practice, the load capacitance receives the greatest attention. Equation (11.9) becomes more complex for CS stages (Problem 11.13). Exercise

Derive the above results if VA < ∞.

Example 11.6

Explain the relationship between the frequency response and step response of the simple low-pass filter shown in Fig. 11.4(a).

Solution

To obtain the transfer function, we view the circuit as a voltage divider and write Vout H(s) = (s) = Vin =

1 C1 s 1 + R1 C1 s 1 . R1C1 s + 1

(11.10)

(11.11)

4 For example, by immersing the circuit in liquid nitrogen (T = 77 K), but requiring that the user carry a tank around!

466

Chapter 11 Frequency Response The frequency response is determined by replacing s with jω and computing the magnitude: 1 . (11.12) |H(s = jω)| = 2 2 2 R1C 1 ω + 1 The −3 dB bandwidth is equal to 1/(R1C1 ). The circuit’s response to a step of the form V0 u(t) is given by −t Vout (t) = V0 1 − exp u(t). R1C1

(11.13)

The relationship between Eqs. (11.12) and (11.13) is that, as R1C1 increases, the bandwidth drops and the step response becomes slower. Figure 11.8 plots this behavior, revealing that a narrow bandwidth results in a sluggish time response. This observation explains the effect seen in Fig. 11.3(b): since the signal cannot rapidly jump from low (white) to high (black), it spends some time at intermediate levels (shades of gray), creating “fuzzy” edges. H

R 1C 1

1.0

Vout

R 1C 1 f

t

(a)

(b)

Figure 11.8 Exercise

At what frequency does |H| fall by a factor of two?

11.1.3 Bode’s Rules The task of obtaining |H( jω)| from H(s) and plotting the result is somewhat tedious. For this reason, we often utilize Bode’s rules (approximations) to construct |H( jω)| rapidly. Bode’s rules for |H( jω)| are as follows: • As ω passes each pole frequency, the slope of |H( jω)| decreases by 20 dB/dec. (A slope of 20 dB/dec simply means a tenfold change in H for a tenfold increase in frequency); • As ω passes each zero frequency, the slope of |H( jω)| increases by 20 dB/dec.5

Example 11.7

Construct the Bode plot of |H( jω)| for the CS stage depicted in Fig. 11.5(a).

Solution

Equation (11.5) indicates a pole frequency of |ωp1 | =

1 . RDCL

(11.14)

5 Complex poles may result in sharp peaks in the frequency response, an effect neglected in Bode’s approximation.

11.1 Fundamental Concepts

467

The magnitude thus begins at gmRD at low frequencies and remains flat up to ω = |ωp1 |. At this point, the slope changes from zero to −20 dB/dec. Figure 11.9 illustrates the result. In contrast to Fig. 11.5(b), the Bode approximation ignores the 3 dB roll-off at the pole frequency—but it greatly simplifies the algebra. As evident from Eq. (11.6), for R2DC L2 ω2 1, Bode’s rule provides a good approximation. 20 log

Vout V in –2

g m RD

0 /d dB ec

ω p1

log ω

Figure 11.9 Exercise

Construct the Bode plot for gm = (150 )−1 , RD = 2 k, and CL = 100 fF.

11.1.4 Association of Poles with Nodes The poles of a circuit’s transfer function play a central role in the frequency response. The designer must therefore be able to identify the poles intuitively so as to determine which parts of the circuit appear as the “speed bottleneck.” The CS topology studied in Example 11.4 serves as a good example for identifying poles by inspection. Equation (11.5) reveals that the pole frequency is given by the inverse of the product of the total resistance seen between the output node and ground and the total capacitance seen between the output node and ground. Applicable to many circuits, this observation can be generalized as follows: if node j in the signal path exhibits a smallsignal resistance of Rj to ground and a capacitance of C j to ground, then it contributes a pole of magnitude (RjC j )−1 to the transfer function.

Example 11.8

Determine the poles of the circuit shown in Fig. 11.10. Assume λ = 0. VDD RD V in

Vout

RS M1

CL

C in

Figure 11.10

Solution

Setting Vin to zero, we recognize that the gate of M1 sees a resistance of RS and a capacitance of Cin to ground. Thus, |ωp1 | =

1 . RSCin

(11.15)

468

Chapter 11 Frequency Response We may call ωp1 the “input pole” to indicate that it arises in the input network. Similarly, the “output pole” is given by |ωp2 | =

1 . RDCL

(11.16)

Since the low-frequency gain of the circuit is equal to −gmRD , we can readily write the magnitude of the transfer function as: Vout gmRD (11.17) V = . in 2 2 2 2 1 + ω /ωp1 1 + ω ω p2 Exercise

If ωp1 = ωp2 , at what frequency does the gain drop by 3 dB?

Example 11.9

Compute the poles of the circuit shown in Fig. 11.11. Assume λ = 0. VDD RD Vout

V in

RS

Vb

M1

CL

C in

Figure 11.11 Solution

With Vin = 0, the small-signal resistance seen at the source of M1 is given by RS ||(1/gm), yielding a pole at 1 . 1 RS || Cin gm

ωp1 =

(11.18)

The output pole is given by ωp2 = (RDCL )−1 . Exercise

How do we choose the value of RD such that the output pole frequency is ten times the input pole frequency?

The reader may wonder how the foregoing technique can be applied if a node is loaded with a “floating” capacitor, i.e., a capacitor whose other terminal is also connected to a node in the signal path (Fig. 11.12). In general, we cannot utilize this technique and must write the circuit’s equations and obtain the transfer function. However, an approximation given by “Miller’s theorem” can simplify the task in some cases.

11.1 Fundamental Concepts

469

VDD RD CF V in

Figure 11.12

Vout

RS M1

Circuit with floating capacitor.

11.1.5 Miller’s Theorem Our above study and the example in Fig. 11.12 make it desirable to obtain a method that “transforms” a floating capacitor to two grounded capacitors, thereby allowing association of one pole with each node. Miller’s theorem is such a method. Miller’s theorem, however, was originally conceived for another reason. In the late 1910s, John Miller had observed that parasitic capacitances appearing between the input and output of an amplifier may drastically lower the input impedance. He then proposed an analysis that led to the theorem. Consider the general circuit shown in Fig. 11.13(a), where the floating impedance, ZF , appears between nodes 1 and 2. We wish to transform ZF to two grounded impedances as depicted in Fig. 11.13(b), while ensuring all of the currents and voltages in the circuit remain unchanged. To determine Z1 and Z2 , we make two observations: (1) the current drawn by ZF from node 1 in Fig. 11.13(a) must be equal to that drawn by Z1 in Fig. 11.13(b); and (2) the current injected to node 2 in Fig. 11.13(a) must be equal to that injected by Z2 in Fig. 11.13(b). (These requirements guarantee that the circuit does not “feel” the transformation.) Thus, V1 V1 − V2 = ZF Z1

(11.19)

V1 − V2 V2 =− . ZF Z2

(11.20)

Denoting the voltage gain from node 1 to node 2 by Av , we obtain Z1 = ZF =

1

ZF

V1

(11.21)

ZF 1 − Av

(11.22)

1

2

V2

(a)

V1 V1 − V2

Z1

2

V1

V2

Z2

(b)

(a) General circuit including a floating impedance, (b) equivalent of (a) as obtained from Miller’s theorem.

Figure 11.13

470

Chapter 11 Frequency Response and Z2 = ZF

−V2 V1 − V2 ZF

=

1 1− Av

(11.23)

.

(11.24)

Called Miller’s theorem, the results expressed by Eqs. (11.22) and (11.24) prove extremely useful in analysis and design. In particular, Eq. (11.22) suggests that the floating impedance is reduced by a factor of 1 − Av when “seen” at node 1. As an important example of Miller’s theorem, let us assume ZF is a single capacitor, CF , tied between the input and output of an inverting amplifier [Fig. 11.14(a)]. Applying Eq. (11.22), we have ZF Z1 = (11.25) 1 − Av =

1 , (1 + A0 )CF s

(11.26)

where the substitution Av = −A0 is made. What type of impedance is Z1 ? The 1/s dependence suggests a capacitor of value (1 + A0 )CF , as ifCF is “amplified” by a factor of 1 + A0 . In other words, a capacitor CF tied between the input and output of an inverting amplifier with a gain of A0 raises the input capacitance by an amount equal to (1 + A0 )CF . We say such a circuit suffers from “Miller multiplication” of the capacitor. The effect of CF at the output can be obtained from Eq. (11.24): ZF

Z2 =

1−

(11.27)

1 Av

1 , 1 1+ CF s A0

=

(11.28)

which is close to (CF s)−1 if A0 1. Figure 11.14(b) summarizes these results. The Miller multiplication of capacitors can also be explained intuitively. Suppose the input voltage in Fig. 11.14(a) goes up by a small amount V. The output then goes down by A0 V. That is, the voltage across CF increases by (1 + A0 )V, requiring that the input

CF

V in

–A 0

Vout –A 0 Δ V

ΔV (a)

V in

–A 0

CF ( 1 + A 0 (

Vout CF ( 1 +

1 ( A0

(b)

(a) Inverting circuit with floating capacitor, (b) equivalent circuit as obtained from Miller’s theorem.

Figure 11.14

11.1 Fundamental Concepts

471

provide a proportional charge. By contrast, if CF were not a floating capacitor and its right plate voltage did not change, it would experience only a voltage change of V and require less charge. The above study points to the utility of Miller’s theorem for conversion of floating capacitors to grounded capacitors. The following example demonstrates this principle.

Example 11.10

Estimate the pole of the circuit shown in Fig. 11.15(a). Assume λ = 0. VDD

VDD

RD

RD

CF V in

Vout

RS

V in

M1

Vout

RS M1

C out

C in (a)

(b)

Figure 11.15 Solution

Noting that M1 and RD constitute an inverting amplifier having a gain of −gmRD , we utilize the results in Fig. 11.14(b) to write: Cin = (1 + A0 )CF = (1 + gmRD )CF and

Cout = 1 +

1 CF , gmRD

(11.29) (11.30)

(11.31)

thereby arriving at the topology depicted in Fig. 11.15(b). From our study in Example 11.8, we have: ωin = =

1 RSCin

(11.32)

1 RS (1 + gmRD )CF

(11.33)

and ωout =

1 RDCout

= RD

(11.34) 1

. 1 1+ CF gmRD

(11.35)

Why does the circuit in (a) have one pole but that in (b) two? This is explained below. Exercise

Calculate Cin if gm = (150 )−1 , RD = 2 k, and CF = 80 fF.

472

Chapter 11 Frequency Response The reader may find the above example somewhat inconsistent. Miller’s theorem requires that the floating impedance and the voltage gain be computed at the same frequency whereas Example 11.10 uses the low-frequency gain, gmRD , even for the purpose of finding high-frequency poles. After all, we know that the existence of CF lowers the voltage gain from the gate of M1 to the output at high frequencies. Owing to this inconsistency, we call the procedure in Example 11.10 the “Miller approximation.” Without this approximation, i.e., if A0 is expressed in terms of circuit parameters at the frequency of interest, application of Miller’s theorem would be no simpler than direct solution of the circuit’s equations. Due to the approximation, the circuit in the above example exhibits two poles. Another artifact of Miller’s approximation is that it may eliminate a zero of the transfer function. We return to this issue in Section 11.4.3. The general expression in Eq. (11.22) can be interpreted as follows: an impedance tied between the input and output of an inverting amplifier with a gain of Av is lowered by a factor of 1 + Av if seen at the input (with respect to ground). This reduction of impedance (hence increase in capacitance) is called “Miller effect.” For example, we say Miller effect raises the input capacitance of the circuit in Fig. 11.15(a) to (1 + gmRD )CF . 11.1.6 General Frequency Response Our foregoing study indicates that capacitances in a circuit tend to lower the voltage gain at high frequencies. It is possible that capacitors reduce the gain at low frequencies as well. As a simple example, consider the high-pass filter shown in Fig. 11.16(a), where the voltage division between C1 and R1 yields Vout (s) = Vin

(11.36)

1 R1 + C1 s R1C1 s , R1C1 s + 1

(11.37)

Vout R1C1 ω . V = 2 2 2 in R1C 1 ω1 + 1

(11.38)

= and hence

R1

Plotted in Fig. 11.16(b), the response exhibits a roll-off as the frequency of operation falls below 1/(R1C1 ). As seen from Eq. (11.37), this roll-off arises because the zero of the transfer function occurs at the origin.

Vout C1

V in 1.0

v in

R1

Vout 1 R 1C 1

(a)

Figure 11.16

(b)

(a) Simple high-pass filter, and (b) its frequency response.

ω

11.1 Fundamental Concepts

473

The low-frequency roll-off may prove undesirable. The following example illustrates this point.

Example 11.11

Figure 11.17 depicts a source follower used in a high-quality audio amplifier. Here, Ri establishes a gate bias voltage equal to VDD for M1 , and I1 defines the drain bias current. Assume λ = 0, gm = 1/(200 ), and R1 = 100 k. Determine the minimum required value of C1 and the maximum tolerable value of CL . VDD V in

Ri M1

Ci

Vout I1

CL

Figure 11.17 Solution

Similar to the high-pass filter of Fig. 11.16, the input network consisting of Ri and Ci attenuates the signal at low frequencies. To ensure that audio components as low as 20 Hz experience a small attenuation, we set the corner frequency 1/(RiCi ) to 2π × (20 Hz), thus obtaining Ci = 79.6 nF.

(11.39)

This value is, of course, much too large to be integrated on a chip. Since Eq. (11.38) reveals a 3 dB attenuation at ω = 1/(RiCi ), in practice we must choose even a larger capacitor if a lower attenuation is desired. The load capacitance creates a pole at the output node, lowering the gain at high frequencies. Setting the pole frequency to the upper end of the audio range, 20 kHz, and recognizing that the resistance seen from the output node to ground is equal to 1/gm, we have gm ω p,out = (11.40) CL = 2π × (20 kHz),

(11.41)

and hence CL = 39.8 nF.

(11.42)

An efficient driver, the source follower can tolerate a very large load capacitance (for the audio band). Exercise

Repeat the above example if I1 and the width of M1 are halved.

Why did we use capacitorCi in the above example? WithoutCi , the circuit’s gain would not fall at low frequencies, and we would not need perform the above calculations. Called a “coupling” capacitor, Ci allows the signal frequencies of interest to pass through the

474

Chapter 11 Frequency Response circuit while blocking the dc content of Vin . In other words, Ci isolates the bias conditions of the source follower from those of the preceding stage. Figure 11.18(a) illustrates an example in which a CS stage precedes the source follower. The coupling capacitor permits independent bias voltages at nodes X and Y. For example, VY can be chosen relatively low (placing M2 near the triode region) to allow a large drop across RD , thereby maximizing the voltage gain of the CS stage (why?).

VDD RD

Ri

Y V in

VDD

Ci

RD

M2

P

M1

X

Vout I1

M1 Vout

V in

M2

(a)

I1

(b)

Cascade of CS stage and source follower with (a) capacitor coupling and (b) direct coupling.

Figure 11.18

To convince the reader that capacitive coupling proves essential in Fig. 11.18(a), we consider the case of “direct coupling” [Fig. 11.18(b)] as well. Here, to maximize the voltage gain, we wish to set VP just above VGS2 − VTH2 , e.g., 200 mV. On the other hand, the gate of M2 must reside at a voltage of at least VGS1 + VI1 , where VI1 denotes the minimum voltage required by I1 . Since VGS1 + VI1 may reach 600-700 mV, the two stages are quite incompatible in terms of their bias points, necessitating capacitive coupling. Capacitive coupling (also called “ac coupling”) is more common in discrete circuit design due to the large capacitor values required in many applications (e.g.,Ci in the above audio example). Nonetheless, many integrated circuits also employ capacitive coupling, especially at low supply voltages, if the necessary capacitor values are no more than a few picofarads. Figure 11.19 shows a typical frequency response and the terminology used to refer to its various attributes. We call ωL the lower corner or lower “cut-off” frequency and ωH the upper corner or upper cut-off frequency. Chosen to accommodate the signal frequencies of interest, the band between ωL and ωH is called the “midband range” and the corresponding gain the “midband gain.”

H Midband

Midband Gain

ωL Figure 11.19

Typical frequency response.

ωH

ω

11.2 High-Frequency Models of Transistors

11.2

475

HIGH-FREQUENCY MODELS OF TRANSISTORS The speed of many circuits is limited by the capacitances within each transistor. It is therefore necessary to study these capacitances carefully. 11.2.1 High-Frequency Model of Bipolar Transistor Recall from Chapter 4 that the bipolar transistor consists of two pn junctions. The depletion region associated with the junctions6 gives rise to a capacitance between base and emitter, denoted by Cje , and another between base and collector, denoted by Cμ [Fig. 11.20(a)]. We may then add these capacitances to the small-signal model to arrive at the representation shown in Fig. 11.20(b). C

n B

Cμ

Cμ

p

B C je

C C je

n+

rπ

g vπ m

vπ

rO

E

E (a)

(b)

Cμ B

C Cπ

rπ

vπ

g vπ m

rO

E (c)

(a) Structure of bipolar transistor showing junction capacitances, (b) small-signal model with junction capacitances, (c) complete model accounting for base charge.

Figure 11.20

Unfortunately, this model is incomplete because the base-emitter junction exhibits another effect that must be taken into account. As explained in Chapter 4, the operation of the transistor requires a (nonuniform) charge profile in the base region to allow the diffusion of carriers toward the collector. In other words, if the transistor is suddenly turned on, proper operation does not begin until enough charge carriers enter the base region and accumulate so as to create the necessary profile. Similarly, if the transistor is suddenly turned off, the charge carriers stored in the base must be removed for the collector current to drop to zero. The above phenomenon is quite similar to charging and discharging a capacitor: to change the collector current, we must change the base charge profile by injecting or removing some electrons or holes. Modeled by a second capacitor between the base and emitter, Cb, this effect is typically more significant than the depletion region capacitance. Since Cb and Cje appear in parallel, they are lumped into one and denoted by Cπ [Fig. 11.20(c)]. 6 As mentioned in Chapter 4, both forward-biased and reversed-biased junctions contain a depletion region and hence a capacitance associated with it.

476

Chapter 11 Frequency Response C

B

p

E

Cμ

Cμ B

n+

Cπ

n

B

C rπ

g vπ m

vπ

rO

C CS

C CS

Substrate

C C CS

Cπ E

E

(a)

(b)

(c)

(a) Structure of an integrated bipolar transistor, (b) small-signal model including collector-substrate capacitance, (c) device symbol with capacitances shown explicitly.

Figure 11.21

In integrated circuits, the bipolar transistor is fabricated atop a grounded substrate [Fig. 11.21(a)]. The collector-substrate junction remains reverse-biased (why?), exhibiting a junction capacitance denoted byCCS . The complete model is depicted in Fig. 11.21(b). We hereafter employ this model in our analysis. In modern integrated-circuit bipolar transistors,Cje ,Cμ , andCCS are on the order of a few femtofarads for the smallest allowable devices. In the analysis of frequency response, it is often helpful to first draw the transistor capacitances on the circuit diagram, simplify the result, and then construct the small-signal equivalent circuit. We may therefore represent the transistor as shown in Fig. 11.21(c). Example 11.12

Identify all of the capacitances in the circuit shown in Fig. 11.22(a). VCC RC

VCC RC Vout V b1

Q2

V in

Q1

Vout

C μ2 Vb

Q2

C π2

C CS2

C μ1 V in

C π1

(a)

Q1

C CS1

(b)

Figure 11.22 Solution

From Fig. 11.21(b), we add the three capacitances of each transistor as depicted in Fig. 11.22(b). Interestingly, CCS1 and Cπ 2 appear in parallel, and so do Cμ2 and CCS2 .

Exercise

Construct the small-signal equivalent circuit of the above cascode.

11.2.2 High-Frequency Model of MOSFET Our study of the MOSFET structure in Chapter 6 revealed several capacitive components. We now study these capacitances in the device in greater detail.

11.2 High-Frequency Models of Transistors C2 n+

477

C1

n+

p (a)

(b)

(a) Structure of MOS device showing various capacitances, (b) partitioning of gate-channel capacitance between source and drain.

Figure 11.23

Illustrated in Fig. 11.23(a), the MOSFET displays three prominent capacitances: one between the gate and the channel (called the “gate oxide capacitance” and given by WLCox ), and two associated with the reverse-biased source-bulk and drain-bulk junctions. The first component presents a modeling difficulty because the transistor model does not contain a “channel.” We must therefore decompose this capacitance into one between the gate and the source and another between the gate and the drain [Fig. 11.23(b)]. The exact partitioning of this capacitance is beyond the scope of this book, but, in the saturation region, C1 is about 2/3 of the gate-channel capacitance whereas C 2 ≈ 0. Two other capacitances in the MOSFET become critical in some circuits. Shown in Fig. 11.24, these components arise from both the physical overlap of the gate with source/drain areas7 and the fringe field lines between the edge of the gate and the top of the S/D regions. Called the gate-drain or gate-source “overlap” capacitance, this (symmetric) effect persists even if the MOSFET is off.

n+

Figure 11.24

Overlap capacitance between gate and drain (or source).

We now construct the high-frequency model of the MOSFET. Depicted in Fig. 11.25(a), this representation consists of: (1) the capacitance between the gate and source, CGS (including the overlap component); (2) the capacitance between the gate and drain (including the overlap component); (3) the junction capacitances between the source and bulk and the drain and bulk, CSB and CDB , respectively. (We assume the bulk remains at ac ground.) C GD G

C GD

D C GS

v GS

g mv GS

rO

C DB

D C DB

G C GS

S C SB

(a)

Figure 11.25

S (b)

(a) High-frequency model of MOSFET, (b) device symbol with capacitances shown

explicitly. 7

C SB

As mentioned in Chapter 6, the S/D areas protrude under the gate during fabrication.

478

Chapter 11 Frequency Response As mentioned in Section 11.2.1, we often draw the capacitances on the transistor symbol [Fig. 11.25(b)] before constructing the small-signal model.

Example 11.13

Identify all of the capacitances in the circuit of Fig. 11.26(a). VDD C GS2

C SB2

VDD M2

C DB2

VDD

M1

V in

V in

M1

C DB1

C GS1

M1

C GS1

(b)

C DB1 + C DB2 + C GS2 C SB1

C SB1 (a)

Vout

C GD1

C GD1

Vout V in

M2

Vout

C GD2

M2

C SB2

(c)

Figure 11.26 Solution

Adding the four capacitances of each device from Fig. 11.25, we arrive at the circuit in Fig. 11.26(b). Note that CSB1 and CSB2 are shorted to ac ground on both ends, CGD2 is shorted “out,” andCDB1 ,CDB2 , andCGS2 appear in parallel at the output node. The circuit therefore reduces to that in Fig. 11.26(c).

Exercise

Noting that M2 is a diode-connected device, construct the small-signal equivalent circuit of the amplifier.

11.2.3 Transit Frequency With various capacitances surrounding bipolar and MOS devices, is it possible to define a quantity that represents the ultimate speed of the transistor? Such a quantity would prove useful in comparing different types or generations of transistors as well as in predicting the performance of circuits incorporating the devices. A measure of the intrinsic speed of transistors8 is the “transit” or “cut-off” frequency, fT , defined as the frequency at which the small-signal current gain of the device falls to unity. Illustrated in Fig. 11.27 (without the biasing circuitry), the idea is to inject a sinusoidal current into the base or gate and measure the resulting collector or drain current while the input frequency, fin , is increased. We note that, as fin increases, the input capacitance of the device lowers the input impedance, Zin , and hence the input voltage Vin = Iin Zin and the output current. We neglect Cμ and CGD here (but take them into account in Problem 11.26). For the bipolar device in Fig. 11.27(a), Zin =

1 ||rπ . Cπ s

(11.43)

8 By “intrinsic” speed, we mean the performance of the device by itself , without any other limitations imposed or enhancements provided by the circuit.

11.2 High-Frequency Models of Transistors I out

I out

ac GND

Q1 I in

Figure 11.27

C in

479

ac GND

M1

Vin

I in

C in

Vin

Conceptual setup for measurement of fT of transistors.

Since Iout = gmIin Zin , Iout gmrπ = Iin r π Cπ s + 1 =

β . r π Cπ s + 1

(11.44)

(11.45)

At the transit frequency, ωT (= 2π fT ), the magnitude of the current gain falls to unity: rπ2C π2 ωT2 = β 2 − 1

(11.46)

≈ β 2.

(11.47)

gm . Cπ

(11.48)

That is, ωT ≈

The transit frequency of MOSFETs is obtained in a similar fashion. We therefore write: 2π fT ≈

gm Cπ

or

gm . CGS

(11.49)

Note that the collector-substrate or drain-bulk capacitance does not affect fT owing to the ac ground established at the output. Modern bipolar and MOS transistors boast fT ’s above 100 GHz. Of course, the speed of complex circuits using such devices is quite lower. Example 11.14

The minimum channel length of MOSFETs has been scaled from 1 μm in the late 1980s to 65 nm today. Also, the inevitable reduction of the supply voltage has reduced the gate-source overdive voltage from about 400 mV to 100 mV. By what factor has the fT of MOSFETs increased?

Solution

It can proved (Problem 11.28) that 2π fT =

3 μn (VGS − VTH ). 2 L2

(11.50)

Thus, the transit frequency has increased by approximately a factor of 59. For example, if μn = 400 cm2 /(V·s), then 65 nm devices having an overdrive of 100 mV exhibit an fT of 226 GHz. Exercise

Determine the fT if the channel length is scaled down to 45 nm but the mobility degrades to 300 cm2 /(V·s).

480

Chapter 11 Frequency Response

11.3

ANALYSIS PROCEDURE We have thus far seen a number of concepts and tools that help us study the frequency response of circuits. Specifically, we have observed that: • The frequency response refers to the magnitude of the transfer function of a system.9 • Bode’s approximation simplifies the task of plotting the frequency response if the poles and zeros are known. • In many cases, it is possible to associate a pole with each node in the signal path. • Miller’s theorem proves helpful in decomposing floating capacitors into grounded elements. • Bipolar and MOS devices exhibit various capacitances that limit the speed of circuits. In order to methodically analyze the frequency response of various circuits, we prescribe the following steps: 1. Determine which capacitors impact the low-frequency region of the response and compute the low-frequency cut-off. In this calculation, the transistor capacitances can be neglected as they typically impact only the high-frequency region. 2. Calculate the midband gain by replacing the above capacitors with short circuits while still neglecting the transistor capacitances. 3. Identify and add to the circuit the capacitances contributed by each transistor. 4. Noting ac grounds (e.g., the supply voltage or constant bias voltages), merge the capacitors that are in parallel and omit those that play no role in the circuit. 5. Determine the high-frequency poles and zeros by inspection or by computing the transfer function. Miller’s theorem may prove useful here. 6. Plot the frequency response using Bode’s rules or exact calculations. We now apply this procedure to various amplifier topologies.

11.4

FREQUENCY RESPONSE OF CE AND CS STAGES 11.4.1 Low-Frequency Response As mentioned in Section 11.1.6, the gain of amplifiers may fall at low frequencies due to certain capacitors in the signal path. Let us consider a general CS stage with its input bias network and an input coupling capacitor [Fig. 11.28(a)]. At low frequencies, the transistor capacitances negligibly affect the frequency response, leaving only Ci as the frequency-dependent component. We write Vout /Vin = (Vout /VX )(VX /Vin ), neglect channellength modulation, and note that both R1 and R2 are tied between X and ac ground. Thus, Vout /VX = −RD /(RS + 1/gm) and VX (s) = Vin

R1 ||R2

1 Ci s (R1 ||R2 )Ci s = . (R1 ||R2 )Ci s + 1

(11.51)

R1 ||R2 +

(11.52)

Similar to the high-pass filter of Fig. 11.16, this network attenuates the low frequencies, dictating that the lower cut-off be chosen below the lowest signal frequency, fsig,min (e.g., 9 In a more general case, the frequency response also includes the phase of the transfer function, as studied in Chapter 12.

11.4 Frequency Response of CE and CS Stages VDD R1

V in

Ci

R1 Vout

X RS

V in

Ci

g m RD Vout

M1

R2

(a)

VX

RD

X

M1

R2

Vout

VDD

RD

481

RS

g m RD Cb

1 + g m RS

(b)

1 R SCb

1 + g m RS R SCb

ω

(c)

(a) CS stage with input coupling capacitor, (b) effect of bypassed degeneration, (c) frequency response with bypassed degeneration.

Figure 11.28

20 Hz in audio applications): 1 < fsig,min . 2π [(R1 ||R2 )Ci ]

(11.53)

In applications demanding a greater midband gain, we place a “bypass” capacitor in parallel with RS [Fig. 11.28(b)] so as to remove the effect of degeneration at midband frequencies. To quantify the role of Cb, we place its impedance, 1/(Cbs), in parallel with RS in the midband gain expression: Vout (s) = VX

=

−RD 1 1 RS || + Cbs gm −gmRD (RSCbs + 1) . RSCbs + gmRS + 1

(11.54)

(11.55)

Figure 11.28(c) shows the Bode plot of the frequency response in this case. At frequencies well below the zero, the stage operates as a degenerated CS amplifier, and at frequencies well above the pole, the circuit experiences no degeneration. Thus, the pole frequency must be chosen significantly smaller than the lowest signal frequency of interest. The above analysis can also be applied to a CE stage. Both types exhibit low-frequency roll-off due to the input coupling capacitor and the degeneration bypass capacitor. 11.4.2 High-Frequency Response Consider the CE and CS amplifiers shown in Fig. 11.29(a), where RS may represent the output impedance of the preceding stage, i.e., it is not added deliberately. Identifying the capacitances of Q 1 and M1 , we arrive at the complete circuits depicted in Fig. 11.29(b), where the source-bulk capacitance of M1 is grounded on both ends. The small-signal equivalents of these circuits differ by only rπ [Fig. 11.29(c)],10 and can be reduced to one if Vin , RS and rπ are replaced with their Thevenin equivalent [Fig. 11.29(d)]. In practice, RS rπ and hence RThev ≈ RS . Note that the output resistance of each transistor would simply appear in parallel with RL . With this unified model, we now study the high-frequency response, first applying Miller’s approximation to develop insight and then performing an accurate analysis to arrive at more general results. 10

The Early effect and channel-length modulation are neglected here.

482

Chapter 11 Frequency Response VDD

VCC VCC

V in

RS

RL

VDD

RL Vout

Vout

RS

V in

RS

V in

M1

Cπ

Vout

C GD

Vout

Cμ

RL Q1

RL

V in C CS

Q1

M1

C DB

C GS C SB

(a)

(b)

Cμ V in

C GD

RS Cπ

Vout rπ

vπ

g Vπ m

C CS

V in

RL

RS

Vout

C GS

v GS

g mV GS

C DB

RL

(c)

C XY R Thev X VX

C in

V Thev

Y

Vout

g mVX

C out

RL

(d)

(a) CE and CS stages, (b) inclusion of transistor capacitances, (c) smallsignal equivalents, (d) unified model of both circuits.

Figure 11.29

11.4.3 Use of Miller’s Theorem With CXY tied between two floating nodes, we cannot simply associate one pole with each node. However, following Miller’s approximation as in Example 11.10, we can decompose CXY into two grounded components (Fig. 11.30): CX = (1 + gmRL )CXY 1 CY = 1 + CXY . gmRL

R Thev V Thev

Figure 11.30

CX

X C in

(11.56) (11.57)

Y vX

Vout

g mv X

C out

CY

RL

CS Stage

CE Stage rπ V Thev = V in r π + RS R Thev = R S r π

V Thev = V in

CX = C μ ( 1 + g m RL ( 1 ( CY = C μ ( 1 + g m RL

C X = C GD ( 1 + g m R L ( 1 ( C Y = C GD ( 1 + g m RL

R Thev = R S

Parameters in unified model of CE and CS stages with Miller’s approximation.

11.4 Frequency Response of CE and CS Stages

483

Now, each node sees a resistance and capacitances only to ground. In accordance with our notations in Section 11.1, we write |ωp,in | =

|ω p,out | =

1 RThev [Cin + (1 + gmRL )CXY ]

(11.58)

1 RL Cout + 1 +

(11.59)

. 1 CXY gmRL

If gmRL 1, the capacitance at the output node is simply equal to Cout + CXY . The intuition gained from the application of Miller’s theorem proves invaluable. The input pole is approximately given by the source resistance, the base-emitter or gate-source capacitance, and the Miller multiplication of the base-collector or gate-drain capacitance. The Miller multiplication makes it undesirable to have a high gain in the circuit. The output pole is roughly determined by the load resistance, the collector-substrate or drain-bulk capacitance, and the base-collector or gate-drain capacitance.

Example 11.15

In the CE stage of Fig. 11.29(a), RS = 200 , IC = 1 mA, β = 100,Cπ = 100 fF, Cμ = 20 fF, and CCS = 30 fF. (a) Calculate the input and output poles if RL = 2 k. Which node appears as the speed bottleneck (limits the bandwidth)? (b) Is it possible to choose RL such that the output pole limits the bandwidth?

Solution

(a) Since rπ = 2.6 k, we have RThev = 186 . Fig. 11.30 and Eqs. (11.58) and (11.59) thus give |ωp,in | = 2π × (516 MHz)

(11.60)

|ω p,out | = 2π × (1.59 GHz).

(11.61)

We observe that the Miller effect multiplies Cμ by a factor of 78, making its contribution much greater than that of Cπ . As a result, the input pole limits the bandwidth. (b) We must seek such a value of RL that yields |ωp,in | > ω p,out |: 1 > (RS ||rπ )[Cπ + (1 + gmRL )Cμ ]

1 RL CCS + 1 +

. 1 Cμ gmRL

(11.62)

If gmRL 1, then we have [CCS + Cμ − gm(RS ||rπ )Cμ ]RL > (RS ||rπ )Cπ .

(11.63)

With the values assumed in this example, the left-hand side is negative, implying that no solution exists. The reader can prove that this holds even if gmRL is not much greater than unity. Thus, the input pole remains the speed bottleneck here. Exercise

Repeat the above example if IC = 2 mA and Cπ = 180 fF.

484

Chapter 11 Frequency Response

Example 11.16

An electrical engineering student designs the CS stage of Fig. 11.29(a) for a certain lowfrequency gain and high-frequency response. Unfortunately, in the layout phase, the student uses a MOSFET half as wide as that in the original design. Assuming that the bias current is also halved, determine the gain and the poles of the circuit.

Solution

Both the width and the bias current of the transistor are halved, and so is its transconductance (why?). The small-signal gain, gmRL , is therefore halved. Reducing the transistor width by a factor of two also lowers all of the capacitances by the same factor. From Fig. 11.30 and Eqs. (11.58) and (11.59), we can express the poles as 1 (11.64) |ωp,in | = Cin gmRL CXY + 1+ RS 2 2 2

|ω p,out | = RL

1 , Cout CXY 2 + 1+ 2 gmRL 2

(11.65)

where Cin , gm, CXY and Cout denote the parameters corresponding to the original device width. We observe that ωp,in has risen in magnitude by more than a factor of two, and ω p,out by approximately a factor of two (if gmRL 2). In other words, the gain is halved and the bandwidth is roughly doubled, suggesting that the gain-bandwidth product is approximately constant. Exercise

What happens if both the width and the bias current are twice their nominal values?

11.4.4 Direct Analysis The use of Miller’s theorem in the previous section provides a quick and intuitive perspective on the performance. However, we must carry out a more accurate analysis so as to understand the limitations of Miller’s approximation in this case. The circuit of Fig. 11.29(d) contains two nodes and can therefore be solved by writing two KCLs. That is,11 At Node X: (Vout − VX )CXY s = VXCin s +

VX − VThev RThev

At Node Y: (VX − Vout )CXY s = gmVX + Vout

1 + Cout s . RL

(11.66)

(11.67)

We compute VX from Eq. (11.67): VX = Vout

11

1 + Cout s RL CXY s − gm

CXY s +

Recall that we denote frequency-domain quantities with upper-case letters.

(11.68)

11.4 Frequency Response of CE and CS Stages

485

and substitute the result in Eq. (11.66) to arrive at VoutCXY s − CXY s + Cin s + It follows that

1 RThev

1 + Cout s −VThev RL Vout = . CXY s − gm RThev

CXY s +

(CXY s − gm)RL Vout (s) = , VThev as2 + bs + 1

(11.69)

(11.70)

where a = RThev RL (CinCXY + CoutCXY + CinCout )

(11.71)

b = (1 + gmRL )CXY RThev + RThevCin + RL (CXY + Cout ).

(11.72)

Note from Fig. 11.30 that for a CE stage, Eq. (11.70) must be multiplied by rπ /(RS + rπ ) to obtain Vout /Vin —without affecting the location of the poles and the zero. Let us examine the above results carefully. The transfer function exhibits a zero at ωz =

gm . CXY

(11.73)

(The Miller approximation fails to predict this zero.) Since CXY (i.e., the base-collector or the gate-drain overlap capacitance) is relatively small, the zero typically appears at very high frequencies and hence is unimportant.12 As expected, the system contains two poles given by the values of s that force the denominator to zero. We can solve the quadratic as2 + bs + 1 = 0 to determine the poles but the results provide little insight. Instead, we first make an interesting observation in regard to the quadratic denominator: if the poles are given by ωp1 and ωp2 , we can write s s 2 as + bs + 1 = +1 +1 (11.74) ωp1 ωp2 s2 1 1 = s + 1. (11.75) + + ωp1 ωp2 ωp1 ωp2 Now suppose one pole is much farther from the origin than the other: ωp2 ωp1 . (This is called the “dominant pole” approximation to emphasize that ωp1 dominates the frequency −1 −1 response). Then, ω−1 p1 + ω p2 ≈ ω p1 , i.e., b=

1 , ωp1

(11.76)

and from Eq. (11.72), |ωp1 | =

1 . (1 + gmRL )CXY RThev + RThevCin + RL (CXY + Cout )

(11.77)

How does this result compare with that obtained using the Miller approximation? Equation (11.77) does reveal the Miller effect of CXY but it also contains the additional term RL (CXY + Cout ) [which is close to the output time constant predicted by Eq. (11.59)]. 12 As explained in more advanced courses, this zero does become problematic in the internal circuitry of op amps.

486

Chapter 11 Frequency Response To determine the “nondominant” pole, ωp2 , we recognize from Eqs. (11.75) and (11.76) that |ωp2 | = =

b a

(11.78)

(1 + gmRL )CXY RThev + RThevCin + RL (CXY + Cout ) . RThev RL (CinCXY + CoutCXY + CinCout )

(11.79)

Example 11.17

Using the dominant-pole approximation, compute the poles of the circuit shown in Fig. 11.31(a). Assume both transistors operate in saturation and λ = 0.

Solution

Noting thatCSB1 ,CGS2 , andCSB2 do not affect the circuit (why?), we add the remaining capacitances as depicted in Fig. 11.31(b), simplifying the result as illustrated in Fig. 11.31(c), where Cin = CGS1 CXY = CGD1 Cout = CDB1 + CGD2 + CDB2 .

(11.80) (11.81) (11.82)

It follows from Eqs. (11.77) and (11.79) that ωp1 ≈

1 [1 + gm1 (rO1 ||rO2 )]CXY RS + RSCin + (rO1 ||rO2 )(CXY + Cout )

(11.83)

ωp2 ≈

[1 + gm1 (rO1 ||rO2 )]CXY RS + RSCin + (rO1 ||rO2 )(CXY + Cout ) . RS (rO1 ||rO2 )(CinCXY + CoutCXY + CinC out )

(11.84)

C SB2 M2 VDD Vb V in

C GD2

M2 M1

Vout

C GD1 Vout

RS

V in

RS

M1

C GS1 (a)

(b)

C DB2

C DB1

C XY V in

Vout

RS

M1

C in

C out

r O1 r O2

(c)

Figure 11.31

Exercise

Repeat the above example if λ = 0.

Example 11.18

In the CS stage of Fig. 11.29(a), we have RS = 200 ,CGS = 250 fF, CGD = 80 fF, CDB = 100 fF, gm = (150 )−1 , λ = 0, and RL = 2 k. Plot the frequency response with the aid of (a) Miller’s approximation, (b) the exact transfer function, (c) the dominantpole approximation.

11.4 Frequency Response of CE and CS Stages Solution

487

(a) With gmRL = 13.3, Eqs. (11.58) and (11.59) yield |ωp,in | = 2π × (571 MHz)

(11.85)

|ω p,out | = 2π × (428 MHz).

(11.86)

(b) The transfer function in Eq. (11.70) gives a zero at gm/CGD = 2π × (13.3 GHz). Also, a = 2.12 × 10−20 s−2 and b = 6.39 × 10−10 s. Thus, |ωp1 | = 2π × (264 MHz)

(11.87)

|ωp2 | = 2π × (4.53 GHz).

(11.88)

Note the large error in the values predicted by Miller’s approximation. This error arises because we have multiplied CGD by the midband gain (1 + gmRL ) rather than the gain at high frequencies.13 (c) The results obtained in part (b) predict that the dominant-pole approximation produces relatively accurate results as the two poles are quite far apart. From Eqs. (11.77) and (11.79), we have |ωp1 | = 2π × (249 MHz) (11.89) |ωp2 | = 2π × (4.79 GHz). (11.90) Figure 11.32 plots the results. The low-frequency gain is equal to 22 dB ≈ 13 and the −3 dB bandwidth predicted by the exact equation is around 250 MHz. Magnitude of Transfer Function (dB)

30 Dominant-Pole Appr. Miller's Approx. Exact Eq.

20 10 0 –10 –20 –30 7 10

8

9

10

10

10

10

Frequency (Hz)

Figure 11.32 Exercise

Repeat the above example if the device width (and hence its capacitances) and the bias current are halved.

11.4.5 Input Impedance The high-frequency input impedances of the CE and CS amplifiers determine the ease with which these circuits can be driven by other stages. Our foregoing analysis of 13 The large discrepancy between |ω p,out | and |ωp2 | results from an effect called “pole splitting” and is studied in more advanced courses.

488

Chapter 11 Frequency Response VCC Cμ Cπ

VDD

RC

Q1

C GD

M1 C CS

Z in

Z in

C GS

C DB

(b)

(a)

Figure 11.33

RD

Input impedance of (a) CE and (b) CS stages.

the frequency response and particularly the Miller approximation readily yields this impedance. As illustrated in Fig. 11.33(a), the input impedance of a CE stage consists of two parallel components: Cπ + (1 + gmRD )Cμ and rπ .14 That is, Zin ≈

1 ||rπ . [Cπ + (1 + gmRD )Cμ ]s

(11.91)

Similarly, the MOS counterpart exhibits an input impedance given by Zin ≈

1 . [CGS + (1 + gmRD )CGD ]s

(11.92)

With a high voltage gain, the Miller effect may substantially lower the input impedance at high frequencies.

11.5

FREQUENCY RESPONSE OF CB AND CG STAGES 11.5.1 Low-Frequency Response As with CE and CS stages, the use of capacitive coupling leads to low-frequency roll-off in CB and CG amplifiers. Consider the CB circuit depicted in Fig. 11.34(a), where I1 defines the bias current ofQ 1 and Vb is chosen to ensure operation in the forward active region (Vb is less than the collector bias voltage). How large should Ci be? Since Ci appears in series with RS , we replace RS with RS + (Ci s)−1 in the midband gain expression, RC /(RS + 1/gm), and write the resulting transfer function as RC Vout (s) = Vin RS + (Ci s)−1 + 1/gm

(11.93)

gmRC Ci s . (1 + gmRS )Ci s + gm

(11.94)

=

Equation (11.93) implies that the signal does not “feel” the effect of Ci if |(Ci s)−1 | RS + 1/gm. From another perspective, Eq. (11.94) yields the response shown in 14

In calculation of the input impedance, the output impedance of the preceding stage (denoted by RS ) is excluded.

11.5 Frequency Response of CB and CG Stages

489

VCC Vout

RC

V in

Vout Vb

Q1 V in

RS

RD RS + 1 gm

Ci I1

gm (1 + g m RS ( Ci

(a)

Figure 11.34

ω

(b)

(a) CB stage with input capacitor coupling, (b) resulting frequency response.

Fig. 11.34(b), revealing a pole at |ω p | =

gm (1 + gmRS )Ci

(11.95)

and suggesting that this pole must remain quite lower than the minimum signal frequency of interest. These two conditions are equivalent. 11.5.2 High-Frequency Response We know from Chapters 5 and 7 that CB and CG stages exhibit a relatively low input impedance (≈ 1/gm). The high-frequency response of these circuits does not suffer from Miller effect, an important advantage in some cases. Consider the stages shown in Fig. 11.35, where rO = ∞ and the transistor capacitances are included. Since Vb is at ac ground, we note that (1) Cπ and CGS + CSB go to ground; (2) CCS and Cμ of Q 1 appear in parallel to ground, and so do CGD and CDB of M1 ; (3) no capacitance appears between the input and output networks, avoiding the Miller effect. In fact, with all of the capacitances seeing ground at one of their terminals, we can readily associate one pole with each node. At node X, the total resistance seen to ground is given by RS ||(1/gm), yielding 1 , 1 RS || CX gm

|ω p,X | =

(11.96)

VDD

VCC

RD

RC Cμ

C CS Y Q1 V in

RS

C DB Y C GD

Vb Cπ

V in

Vb

M1 RS X

C GS C SB

X (a)

Figure 11.35

Vout

Vout

(b)

(a) CB and (b) CG stages including transistor capacitances.

490

Chapter 11 Frequency Response where CX = Cπ or CGS + CSB . Similarly, at Y, 1 , RLCY

|ω p,Y | =

(11.97)

where CY = Cμ + CCS or CGD + CDB . It is interesting to note that the “input” pole magnitude is on the order of the fT of the transistor: CX is equal to Cπ or roughly equal to CGS while the resistance seen to ground is less than 1/gm. For this reason, the input pole of the CB/CG stage rarely creates a speed bottleneck.15

Example 11.19

Compute the poles of the circuit shown in Fig. 11.36(a). Assume λ = 0. C SB2 VDD M2

V in

RS

M1

VDD M2

Vout Vb

Vout

Y V in

RS

Vb

M1

C DB1 + C GD1 + C GS2 + C DB2

X C SB1 + C GS1

(a)

(b)

Figure 11.36 Solution

Noting that CGD2 and CSB2 play no role in the circuit, we add the device capacitances as depicted in Fig. 11.36(b). The input pole is thus given by 1 . 1 RS (CSB1 + CGD1 ) g

|ω p,X | =

(11.98)

m1

Since the small-signal resistance at the output node is equal to 1/gm2 , we have |ω p,Y | =

1 . 1 (CDB1 + CGD1 + CGS2 + CDB2 ) gm2

(11.99)

Exercise

Repeat the above example if M2 operates as a current source, i.e., its gate is connected to a constant voltage.

Example 11.20

The CS stage of Example 11.18 is reconfigured to a common-gate amplifier (with RS tied to the source of the transistor). Plot the frequency response of the circuit.

15 One exception is encountered in radio-frequency circuits (e.g., cellphones), where the input capacitance becomes undesirable.

11.6 Frequency Response of Followers Solution

491

With the values given in Example 11.18 and noting that CSB = CDB ,16 we obtain from Eqs. (11.96) and (11.97), |ω p,in | = 2π × (5.31 GHz) (11.100) |ω p,out | = 2π × (442 MHz).

(11.101)

With no Miller effect, the input pole has dramatically risen in magnitude. The output pole, however, limits the bandwidth. Also, the low-frequency gain is now equal to RD /(RS + 1/gm) = 5.7, more than a factor of two lower than that of the CS stage. Figure 11.37 plots the result. The low-frequency gain is equal to 15 dB ≈ 5.7 and the −3 dB bandwidth is around 450 MHz.

Magnitude of Frequency Response (dB)

20 15 10 5 0 –5 –10 –15 –20 6 10

7

10

8

10 Frequency (Hz)

9

10

10

10

Figure 11.37

Exercise

Repeat the above example if the CG amplifier drives a load capacitance of 150 fF.

11.6

FREQUENCY RESPONSE OF FOLLOWERS The low-frequency response of followers is similar to that studied in Example 11.11 and that of CE/CS stages. We thus study the high-frequency behavior here. In Chapters 5 and 7, we noted that emitter and source followers provide a high input impedance and a relatively low output impedance while suffering from a sub-unity (positive) voltage gain. Emitter followers, and occasionally source followers, are utilized as buffers and their frequency characteristics are of interest. Figure 11.38 illustrates the stages with relevant capacitances. The emitter follower is loaded withCL to create both a more general case and greater similarity between the bipolar and MOS counterparts. We observe that each circuit contains two grounded capacitors and one floating capacitor. While the latter may be decomposed using Miller’s approximation, 16 In reality, the junction capacitances CSB and CDB sustain different reverse bias voltages and are therefore not quite equal.

492

Chapter 11 Frequency Response VCC

Cμ V in

RS

X

Cπ

RS

V in

Q1

X

M1

C GS

Y

VDD C DB

C GD

Y

Vout

C SB + C L

CL (a)

Figure 11.38

Vout

(b)

(a) Emitter follower and (b) source follower including transistor capacitances.

the resulting analysis is beyond the scope of this book. We therefore perform a direct analysis by writing the circuit’s equations. Since the bipolar and MOS versions in Fig. 11.38 differ by only rπ , we first analyze the emitter follower and subsequently let rπ (or β) approach infinity to obtain the transfer function of the source follower. Consider the small-signal equivalent shown in Fig. 11.39. Recognizing that VX = Vout + Vπ and the current through the parallel combination of rπ and Cπ is given by Vπ /rπ + VπCπ s, we write a KCL at node X: Vout + Vπ − Vin Vπ + (Vout + Vπ )Cμ s + + VπCπ s = 0, RS rπ

(11.102)

and another at the output node: Vπ + VπCπ s + gmVπ = VoutCL s. rπ

(11.103)

The latter gives Vπ =

VoutCL s , 1 + gm + Cπ s rπ

(11.104)

−1 , leads to which, upon substitution in Eq. (11.102) and with the assumption rπ gm

Cπ s 1+ Vout gm = 2 , Vin as + bs + 1

RS V in

Cμ

(11.105)

X Cπ

rπ

g Vπ m

Vπ

Vout CL

Figure 11.39

Small-signal equivalent of emitter follower.

11.6 Frequency Response of Followers

493

where a=

RS (CμCπ + CμCL + CπCL ) gm

b = RSCμ +

Cπ RS CL + 1+ . gm rπ gm

(11.106)

(11.107)

The circuit thus exhibits a zero at |ωz| =

gm , Cπ

(11.108)

which, from Eq. (11.49), is near the fT of the transistor. The poles of the circuit can be computed using the dominant-pole approximation described in Section 11.4.4. In practice, however, the two poles do not fall far from each other, necessitating direct solution of the quadratic denominator. The above results also apply to the source follower if rπ → ∞ and corresponding capacitance substitutions are made (CSB and CL are in parallel): CGS s 1+ Vout gm = 2 , Vin as + bs + 1

(11.109)

where a=

RS [CGDCGS + CGD (CSB + CL ) + CGS (CSB + CL )] gm

b = RSCGD +

CGD + CSB + CL . gm

(11.110)

(11.111)

Example 11.21

A source follower is driven by a resistance of 200 and drives a load capacitance of 100 fF. Using the transistor parameters given in Example 11.18, plot the frequency response of the circuit.

Solution

The zero occurs at gm/CGS = 2π × (4.24 GHz). To compute the poles, we obtain a and b from Eqs. (11.110) and (11.111), respectively: a = 2.58 × 10−21 s−2

(11.112)

b = 5.8 × 10−11 s.

(11.113)

The two poles are then equal to ωp1 = 2π [−1.79 GHz + j(2.57 GHz)]

(11.114)

ωp2 = 2π [−1.79 GHz − j(2.57 GHz)].

(11.115)

494

Chapter 11 Frequency Response

Magnitude of Frequency Response (dB)

0 –2 –4 –6 –8 –10 –12 –14 6 10

7

8

10

9

10 Frequency (Hz)

10

10

10

Figure 11.40

With the values chosen here, the poles are complex. Figure 11.40 plots the frequency response. The −3 dB bandwidth is approximately equal to 3.5 GHz. Exercise

For what value of gm do the two poles become real and equal?

Example 11.22

Determine the transfer function of the source follower shown in Fig. 11.41(a), where M2 acts as a current source. C GD1

V in

VDD

RS

V in

RS C GS1

M1 Vout Vb

M2 (a)

X

M1 Y

C GD2 Vb C GS2

VDD

M2

C DB1 Vout C DB2 + C SB1 C SB2

(b)

Figure 11.41 Solution

Noting thatCGS2 andCSB2 play no role in the circuit, we include the transistor capacitances as illustrated in Fig. 11.41(b). The result resembles that in Fig. 11.38, but with CGD2 and CDB2 appearing in parallel with CSB1 . Thus, Eq. (11.109) can be rewritten as CGS1 s 1+ Vout gm1 , (s) = 2 Vin as + bs + 1

(11.116)

11.6 Frequency Response of Followers

495

where a=

RS [CGD1CGS1 + (CGD1 + CGS1 )(CSB1 + CGD2 + CDB2 )] gm1

b = RSCGD1 +

Exercise

CGD1 + CSB1 + CGD2 + CDB2 . gm1

(11.117) (11.118)

Assuming M1 and M2 are identical and using the transistor parameters given in Example 11.18, calculate the pole frequencies.

11.6.1 Input and Output Impedances In Chapter 5, we observed that the input resistance of the emitter follower is given by rπ + (β + 1)RL , where RL denotes the load resistance. Also, in Chapter 7, we noted that the source follower input resistance approaches infinity at low frequencies. We now employ an approximate but intuitive analysis to obtain the input capacitance of followers. Consider the circuits shown in Fig. 11.42, where Cπ and CGS appear between the input and output and can therefore be decomposed using Miller’s theorem. Since the low-frequency gain is equal to Av =

RL RL +

1 gm

,

(11.119)

we note that the “input” component of Cπ or CGS is expressed as CX = (1 − Av )CXY =

(11.120)

1 CXY . 1 + gmRL

(11.121)

Interestingly, the input capacitance of the follower contains only a fraction of Cπ or CGS , depending on how large gmRL is. Of course, Cμ or CGD directly adds to this value to yield the total input capacitance.

Cμ X

C XY = C π

C XY = C GS

Y

(a)

C GD X

Q1

RL

Figure 11.42

VCC

CL

VDD

M1

C DB

Y RL

C L+ C SB

(b)

Input impedance of (a) emitter follower and (b) source follower.

496

Chapter 11 Frequency Response

Example 11.23

Estimate the input capacitance of the follower shown in Fig. 11.43. Assume λ = 0. VDD V in Vb

M1

M2

Figure 11.43 Solution

From Chapter 7, the low-frequency gain of the circuit can be written as Av =

rO1 ||rO2 rO1 ||rO2 +

1 gm1

.

(11.122)

Also, from Fig. 11.42(b), the capacitance appearing between the input and output is equal to CGS1 , thereby providing Cin = CGD1 + (1 − Av )CGS1 = CGD1 +

(11.123)

1 CGS1 . 1 + gm1 (rO1 ||rO2 )

(11.124)

For example, if gm1 (rO1 ||rO2 ) ≈ 10, then only 9% of CGS1 appears at the input. Exercise

Repeat the above example if λ = 0.

Let us now turn our attention to the output impedance of followers. Our study of the emitter follower in Chapter 5 revealed that the output resistance is equal to RS /(β + 1) + 1/gm. Similarly, Chapter 7 indicated an output resistance of 1/gm for the source follower. At high frequencies, these circuits display an interesting behavior. Consider the followers depicted in Fig. 11.44(a), where other capacitances and resistances are neglected for the sake of simplicity. As usual, RS represents the output resistance of a preceding stage or device. We first compute the output impedance of the emitter follower and subsequently let rπ → ∞ to determine that of the source follower. From the

V in

VCC

RS Cπ

Q1

V in

RS C GS

VDD M1

RS Cπ

rπ

g Vπ m

Vπ IX

Z out

Z out (a)

Figure 11.44

(b)

(a) Output impedance of emitter and source followers, (b) small-signal model.

VX

11.6 Frequency Response of Followers equivalent circuit in Fig. 11.44(b), we have 1 (IX + gmVπ ) rπ = −Vπ Cπ s

497

(11.125)

and also (IX + gmVπ )RS − Vπ = VX .

(11.126)

Finding Vπ from Eq. (11.125) Vπ = −IX

rπ r π Cπ s + β + 1

(11.127)

and substituting in Eq. (11.126), we obtain VX RS rπCπ s + rπ + RS = . IX r π Cπ s + β + 1

(11.128)

As expected, at low frequencies VX /IX = (rπ + RS )/(β + 1) ≈ 1/gm + RS /(β + 1). On the other hand, at very high frequencies, VX /IX = RS , a meaningful result considering that Cπ becomes a short circuit. The two extreme values calculated above for the output impedance of the emitter follower can be used to develop greater insight. Plotted in Fig. 11.45, the magnitude of this impedance falls with ω if RS < 1/gm + RS /(β + 1) or rises with ω if RS > 1/gm + RS /(β + 1). In analogy with the impedance of capacitors and inductors, we say Zout exhibits a capacitive behavior in the former case and an inductive behavior in the latter. Z out RS

+

Z out

1

RS

β + 1 gm

RS

RS

ω

+

1

β + 1 gm

(a)

ω (b)

Figure 11.45 Output impedance of emitter follower as a function of frequency for (a) small RS and

(b) large RS .

Which case is more likely to occur in practice? Since a follower serves to reduce the driving impedance, it is reasonable to assume that the follower low-frequency output impedance is lower than RS .17 Thus, the inductive behavior is more commonly encountered. (It is even possible that the inductive output impedance leads to oscillation if the follower sees a certain amount of load capacitance.) The above development can be extended to source followers by factoring rπ from the numerator and denominator of Eq. (11.128) and letting rπ and β approach infinity: VX RSCGS s + 1 = , IX CGS s + gm

(11.129)

where(β + 1)/rπ is replaced with gm, and Cπ with CGD . The plots of Fig. 11.45 are redrawn for the source follower in Fig. 11.46, displaying a similar behavior. 17

If the follower output resistance is greater than RS , then it is better to omit the follower!

498

Chapter 11 Frequency Response Z out

Z out

1 gm

RS

RS

1 gm

ω

ω

(a)

Figure 11.46

(b)

Output impedance of source follower as a function of frequency for (a) small RS and

(b) large RS .

The inductive impedance seen at the output of followers proves useful in the realization of “active inductors.”

Example 11.24

Figure 11.47 depicts a two-stage amplifier consisting of a CS circuit and a source follower. Assuming λ = 0 for M1 and M2 but λ = 0 for M3 , and neglecting all capacitances except CGS3 , compute the output impedance of the amplifier. VDD Vb

M2

r O1 r O2

M3 V in

VDD M3

Vout

M1

Z out (a)

(b)

Figure 11.47 Solution

The source impedance seen by the follower is equal to the output resistance of the CS stage, which is equal to rO1 ||rO2 . Assuming RS = rO1 ||rO2 in Eq. (11.129), we have VX (rO1 ||rO2 )CGS3 s + 1 = . IX CGS3 s + gm3

Exercise

Determine Zout in the above example if λ = 0 for M1 -M3 .

11.7

FREQUENCY RESPONSE OF CASCODE STAGE

(11.130)

Our analysis of the CE/CS stage in Section 11.4 and the CB/CG stage in Section 11.5 reveals that the former provides a relatively high input resistance but suffers from Miller effect whereas the latter exhibits a relatively low input resistance but is free from Miller effect. We wish to combine the desirable properties of the two topologies, obtaining a circuit with a relatively high input resistance and no or little Miller effect. Indeed, this thought process led to the invention of the cascode topology in the 1940s. Consider the cascodes shown in Fig. 11.48. As mentioned in Chapter 9, this structure can be viewed as a CE/CS transistor, Q 1 or M1 , followed by a CB/CG device, Q 2 or M2 . As such, the circuit still exhibits a relatively high (for Q 1 ) or infinite (for M1 ) input resistance

11.7 Frequency Response of Cascode Stage VCC

VDD

RL

RL Vout

V b1

V in

M2 C GD1

Y Q1

RS X

V in

RS X

(a)

Figure 11.48

Vout

Vb

Q2

C μ1

499

Y M1

(b)

(a) Bipolar and (b) MOS cascode stages.

while providing a voltage gain equal to gm1 RL .18 But, how about the Miller multiplication of Cμ1 or CGD1 ? We must first compute the voltage gain from node X to node Y. Assuming rO = ∞ for all transistors, we recognize that the impedance seen at Y is equal to 1/gm2 , yielding a small-signal gain of Av,XY =

vY vX

=−

(11.131)

gm1 . gm2

(11.132)

In the bipolar cascode, gm1 = gm2 (why?), resulting in a gain of −1. In the MOS counterpart, M1 and M2 need not be identical, but gm1 and gm2 are comparable because of their relatively weak dependence upon W/L. We therefore say the gain from X to Y remains near −1 in most practical cases, concluding that the Miller effect of CXY = Cμ1 or CGD1 is given by CX = (1 − Av,XY )CXY ≈ 2CXY .

(11.133) (11.134)

This result stands in contrast to that expressed by Eq. (11.56), suggesting that the cascode transistor breaks the trade-off between the gain and the input capacitance due to Miller effect. Let us continue our analysis and estimate the poles of the cascode topology with the aid of Miller’s approximation. Illustrated in Fig. 11.49 is the bipolar cascode along with the transistor capacitances. Note that the effect of Cμ1 at Y is also equal to (1 − A−1 v,XY )Cμ1 = 2Cμ1 . VCC RL V b1 V in

RS X

C π 1+ 2 C μ 1

Figure 11.49 18

Q2

Vout C CS2 + C μ 2

Y Q1

C CS1 + C π 2+ 2 C μ 1

Bipolar cascode including transistor capacitances.

The voltage division between RS and rπ 1 lowers the gain slightly in the bipolar circuit.

500

Chapter 11 Frequency Response Associating one pole with each node gives |ω p,X | =

1 (RS ||rπ 1 )(C π 1 + 2Cμ1 )

|ω p,Y | =

1 1 (CCS1 + Cπ 2 + 2Cμ1 ) gm2 1

|ω p,out | =

RL (CCS2 + Cμ2 )

(11.135)

.

(11.136)

(11.137)

It is interesting to note that the pole at node Y falls near the fT ofQ 2 ifCπ 2 CCS1 + 2Cμ1 . Even for comparable values of Cπ 2 and CCS1 + 2Cμ1 , we can say this pole is on the order of fT /2, a frequency typically much higher than the signal bandwidth. For this reason, the pole at node Y often has negligible effect on the frequency response of the cascode stage. The MOS cascode is shown in Fig. 11.50 along with its capacitances after the use of Miller’s approximation. Since the gain from X to Y in this case may not be equal to −1, we use the actual value, −gm1 /gm2 , to arrive at a more general solution. Associating one pole with each node, we have |ω p,X | =

1 gm1 CGD1 RS CGS1 + 1 + gm2

|ω p,Y | =

1 1 gm2 CDB1 + CGS2 + 1 + CGD1 + CSB2 gm2 gm1

|ω p,out | =

(11.138)

1 . RL (CDB2 + CGD2 )

(11.139)

(11.140)

We note that ω p,Y is still in the range of fT /2 if CGS2 and CDB1 + (1 + gm2 /gm1 )CGD1 are comparable. VDD RL Vout

Vb V in C GS1 + C GD1 (1+

Figure 11.50

Example 11.25

RS g m1 g m2

X

M2

C GD2 + C DB2

Y M1

C GS2 + C GD1 (1+

g m2 ) + C DB1 + C SB2 g m1

)

MOS cascode including transistor capacitances.

The CS stage studied in Example 11.18 is converted to a cascode topology. Assuming the two transistors are identical, estimate the poles, plot the frequency response, and compare the results with those of Example 11.18. Assume CDB = CSB .

11.7 Frequency Response of Cascode Stage Solution

501

Using the values given in Example 11.18, we write from Eqs. (11.138), (11.139), and (11.140): |ω p,X | = 2π × (1.95 GHz)

(11.141)

|ω p,Y | = 2π × (1.73 GHz)

(11.142)

|ω p,out | = 2π × (442 MHz).

(11.143)

Note that the pole at node Y is significantly lower than fT /2 in this particular example. Compared with the Miller approximation results obtained in Example 11.18, the input pole has risen considerably. Compared with the exact values derived in that example, the cascode bandwidth (442 MHz) is nearly twice as large. Figure 11.51 plots the frequency response of the cascode stage. Magnitude of Frequency Response (dB)

30 20 10 0 –10 –20 –30 6 10

7

8

10

9

10 Frequency (Hz)

10

10

10

Figure 11.51 Exercise

Repeat the above example if the width of M2 and hence all of its capacitances are doubled. Assume gm2 = (100 )−1 .

Example 11.26

In the cascode shown in Fig. 11.52, transistor M3 serves as a constant current source, allowing M1 to carry a larger current than M2 . Estimate the poles of the circuit, assuming λ = 0. VDD V b2

M3

V in

Figure 11.52

RL Vout

V b1

M2

RS

Y M1

X

502

Chapter 11 Frequency Response

Solution

Transistor M3 contributes CGD3 and CDB3 to node Y, thus lowering the corresponding pole magnitude. The circuit contains the following poles: |ω p,X | =

1 gm1 CGD1 RS CGS1 + 1 + gm2

1 1 gm2 CDB1 + CGS2 + 1 + CGD1 + CGD3 + CDB3 + CSB2 gm2 gm1 1 |ω p,out | = . RL (CDB2 + CGD2 ) |ω p,Y | =

(11.144)

(11.145)

(11.146)

Note that ω p,X also reduces in magnitude because the addition of M3 lowers ID2 and hence gm2 . Exercise

Calculate the pole frequencies in the above example using the transistor parameters given in Example 11.18 for M1 -M3 .

From our studies of the cascode topology in Chapter 9 and in this chapter, we identify two important, distinct attributes of this circuit: (1) the ability to provide a high output impedance and hence serve as a good current source and/or high-gain amplifier; (2) the reduction of the Miller effect and hence better high-frequency performance. Both of these properties are exploited extensively. 11.7.1 Input and Output Impedances The foregoing analysis of the cascode stage readily provides estimates for the I/O impedances. From Fig. 11.49, the input impedance of the bipolar cascode is given by 1 , (11.147) Zin = rπ 1 (C π 1 + 2Cμ1 )s where Zin does not include RS . The output impedance is equal to 1 , Zout = RL (Cμ2 + CCS2 )s

(11.148)

where the Early effect is neglected. Similarly, for the MOS stage shown in Fig. 11.50, we have 1 Zin = gm1 CGS1 + 1 + CGD1 s gm2 Zout = where it is assumed λ = 0.

1 , RL (CGD2 + CDB2 )

(11.149)

(11.150)

11.8 Frequency Response of Differential Pairs

503

If RL is large, the output resistance of the transistors must be taken into account. This calculation is beyond the scope of this book.

11.8

FREQUENCY RESPONSE OF DIFFERENTIAL PAIRS The half-circuit concept introduced in Chapter 10 can also be applied to the high-frequency model of differential pairs, thus reducing the circuit to those studied above. Figure 11.53(a) depicts two bipolar and MOS differential pairs along with their capacitances. For small differential inputs, the half circuits can be constructed as shown in Fig. 11.53(b). The transfer function is therefore given by Eq. (11.70): Vout (CXY s − gm)RL (s) = , VThev as2 + bs + 1

(11.151)

where the same notation is used for various parameters. Similarly, the input and output impedances (from each node to ground) are equal to those in Eqs. (11.91) and (11.92), respectively.

VCC RC C CS1

RD

RD

C CS2

C DB1

C DB2

C GD1

C GD2

C μ1 V in1

VDD

RC

C μ2

RS C π2

RS Q1

Q2

V in2

V in1

C π1

RS

RS

C GS1

I EE

M1

M2 I SS

C SB1

C GS2 C SB2

(a)

VCC

VDD

RC C μ1 V in1

RS C π2

RD Vout1

C GD1

C CS1

V in1

RS C GS1

Q1

C DB1 M1

C SB1

(b)

(a) Bipolar and MOS differential pairs including transistor capacitances, (b) half circuits.

Figure 11.53

V in2

504

Chapter 11 Frequency Response

Example 11.27

A differential pair employs cascode devices to lower the Miller effect [Fig. 11.54(a)]. Estimate the poles of the circuit. VDD RD M3

Vout

Vb V in1

VDD RD

RD

M4

RS

M2

M1

I SS

Vout

Vb RS

Vin2

RS

V in

C GS1 + C GD1 (1+

g m1 g m3

X

M3

C GD3 + C DB3

Y M1

)

(a)

C GS3 + C GD1 (1+

g m3 ) + C DB1 + C SB3 g m1

(b)

Figure 11.54 Solution

Employing the half circuit shown in Fig. 11.54(b), we utilize the results obtained in Section 11.7: |ω p,X | =

1 gm1 CGD1 RS CGS1 + 1 + gm3

|ω p,Y | =

1 1 gm3 CDB1 + CGS3 + 1 + CGD1 + CSB3 gm3 gm1

|ω p,out | =

Exercise

1 . RL (CDB3 + CGD3 )

(11.152)

(11.153)

(11.154)

Calculate the pole frequencies using the transistor parameters given in Example 11.18. Assume √ the width and hence the capacitances of M3 are twice those of M1 . Also, gm3 = 2gm1 .

11.8.1 Common-Mode Frequency Response ∗ The CM response studied in Chapter 10 included no transistor capacitances. At high frequencies, capacitances may raise the CM gain (and lower the differential gain), thus degrading the common-mode rejection ratio. Let us consider the MOS differential pair shown in Fig. 11.55(a), where a finite capacitance appears between node P and ground. Since CSS shunts RSS , we expect the total impedance between P and ground to fall at high frequencies, leading to a higher CM gain. ∗

This section can be skipped in a first reading.

11.8 Frequency Response of Differential Pairs VDD

CM Gain g m ΔR D

R D + ΔR D

RD V out1

Vout2 M1

V CM

P

I EE

M2

ΔRD 2 R SS + 1 gm

R SS

1 R SS C SS

C SS

(a)

Figure 11.55

505

2 gm C SS

ω

(b)

(a) Differential pair with parasitic capacitance at the tail node, (b) CM frequency

response.

In fact, we can simply replace RSS with RSS ||[1/(CSS s)] in Eq. (10.186): Vout RD V = 1 1 CM + 2 RSS gm CSS s =

gmRD (RSSCSS + 1) . RSSCSS s + 2gmRSS + 1

(11.155)

(11.156)

Since RSS is typically quite large, 2gmRSS 1, yielding the following zero and pole frequencies: |ωz| =

1 RSSCSS

(11.157)

|ω p | =

2gm , CSS

(11.158)

and the Bode approximation plotted in Fig. 11.55(b). The CM gain indeed rises dramatically at high frequencies—by a factor of 2gmRSS (why?). Figure 11.56 depicts the transistor capacitances that constitute CSS . For example, M3 is typically a wide device so that it can operate with a small VDS , thereby adding large capacitances to node P.

M1

M2

C GD3

C SB1 Vb

M3

Figure 11.56

P

C SB2 C SB3

Transistor capacitance contributions to the tail node.

506

Chapter 11 Frequency Response

PROBLEMS 11.1. For the circuit in Fig. 11.57, −3 dB bandwidth at 1.2 GHz is desired. Maximum gain required is 1.8 with power dissipation of 2.5 mW. Take V CC = 2.5 V, neglect early effect and other capacitances. Calculate the value of CL required. VCC

11.5. For the transfer function (TF) 25 +1 50 sketch the Bode plot. 11.6. Find TF =

Bode

magnitude

plot

for

5 × 104S . (S 2 + 60 S + 500)

11.7. Figure 11.59 (a) shows CS amplifier. Analyze for low frequency response.

R1 Vout Vin

Ibias = 100 μA, (rds(ON) ) = 8000L/ID(mA) · rds p = 12000L/ID mA .

Q1

11.8. In Fig. 11.60, identify poles at various node points.

CL

VDD RD

Figure 11.57

11.2. For the amplifier in Fig. 11.58, RD = 1.5 k,C L = 1.5 PF. Determine by what percentage gain reduces if operated at 3 GHz. Neglect channel-length modulation and other capacitances.

VB Vin

CL

A

Figure 11.60

RD

11.9. For Fig. 11.61 with parasitic resistance RP1 (on source) determine input and output poles of circuit. λ = 0 and neglect other parasitic capacitances.

Vout M1

M1

Vout

Cin

VDD

Vin

RG

B

CL

VDD

Figure 11.58

RD

11.3. Determine the −3 dB bandwidth of the circuits shown in Fig. 11.59. Assume VA = ∞ but λ > 0. Neglect other capacitances.

Vout

A Vb

CL

11.4. For Fig. 11.59 (e), Rin = 200 k, C L = 0.25 pF, C gs1 = 0.22 pF, C gd1 = 0.014 pF, C db1 = 21 fF and C db2 = 40 fF. Estimate −3 dB frequency (W/L) = 100/1.6. μnC ox = 90 μA/V2 , μ pC ox = 30 μA/V2 ,

RP1

RS Vin

B Cin Figure 11.61

VCC

VCC

Q2 Vout V in

Q1

CL

RB V in

(a)

Q1

CL

V in

M2

Vout

(b)

Figure 11.59

Vb

Q2

M1

(c)

CL

Q2

M1

Vout V in

Q3

VDD

VDD

Vout Vout

M2

(d)

CL

I bias

Vin

(e)

Q1

R out

Problems 11.10. Figure 11.62 shows CS amplifier. Discuss gain roll-off for this current for range of frequencies and which meter is used for “figure of merit”.

507

VDD RD CF Vin

Vout

RG M1

VDD Figure 11.65

RD Vout

VM

M1

11.15. Repeat Problem 11.14 for the source follower in Fig. 11.66. Assume λ = 0 and RF is large enough to allow the approximation −1 vout /vX = RL /(RL + gm ).

CL

Figure 11.62

11.11. Repeat Problem 11.10 for the circuit shown in Fig. 11.63.

V in

RS

VDD X

M1 Vout

RF

VDD

RL

RD Vout RP V in

CL Vb

RS

Figure 11.66

11.16. For Fig. 11.67, determine input and output impedances using Miller’s theorem.

C in

VDD Figure 11.63

RD

CGD

11.12. Repeat Problem 11.10 for the CS stage depicted in Fig. 11.64.

M1

Z in VDD

Zout CDB

CGS

Figure 11.67

RD V in

Vout

RS M1 C in

CL

11.17. For a CG circuit in Fig. 11.68, find pole frequencies at points X and Y (λ = 0).

RP

VDD CGD

Figure 11.64

*11.13. Derive a relationship for the figure of merit defined by Eq. (11.8) for a CS stage. Consider only the load capacitance. 11.14. For Fig. 11.65, apply Miller’s theorem to get input and output pole frequencies (λ = 0).

RD

CDB

Y

VB CGS

RS X CSB

Figure 11.68

Vin

508

Chapter 11 Frequency Response

11.18. Repeat Problem 11.17 for the source fol- **11.21. Repeat Problem 11.22 for the circuit in lower shown in Fig. 11.69. Fig. 11.72. VDD VCC

M1

RC

CF C in V in

Q2

RB Q1

Figure 11.69

11.19. For Fig. 11.70, determine the voltage gain of the circuit which is source follower (λ = 0).

Figure 11.72

VDD

CGD

X

11.22. For the bipolar circuits depicted in Fig. 11.73, identify all of the transistor capacitances and determine which ones are in parallel and which ones are grounded on both ends.

M1 Y

Vout

CGS

C SB

11.23. For the MOS circuits shown in Fig. 11.74, identify all of the transistor capacitances and determine which ones are in parallel and which ones are grounded on both ends.

Figure 11.70

11.20. For Fig. 11.71, find expression for input capacitance for the source follower (λ = 0). CGD

CXY = CGS

Vout

CF

X

VDD

*11.25. It can be shown that CGS ≈ (2/3)WLCox for a MOSFET operating in saturation. Using Eq. (11.49), prove that

M1 Y CGS

RS

11.24. In arriving at Eq. (11.49) for the fT of transistors, we neglected Cμ and CGD . Repeat the derivation without this approximation.

2π fT =

C SB

3 μn (VGS − VTH ). 2 L2

(11.180)

Note that fT increases with the overdrive voltage.

Figure 11.71

VCC VCC Q2 Vout V in

Q1

(a)

Figure 11.73

I1

VCC

CL

RB V in

Vout

Q2

V b1

Q1

V in

Q2

Vout Q1

(b)

CL

VCC Q3

(c)

V b3

Problems

509

VDD VDD Vb

VDD V in

M2

V in

M2

Vout V in

RE M2

Vout Vb

M1

VDD

RG

Vin

M1

V b1

M1

M1

Vout

X C GS

RS (a)

(b)

(c)

Z out

(d)

Figure 11.74

* 11.26. Having solved Problem 11.25 successfully, a student attempts a different substitution for gm: 2ID /(VGS − VTH ), arriving at

VB

M2

1 3 2ID 2π fT = . 2 WLCox VGS − VTH

Vin

M1

M3

(11.181)

This result suggests that fT decreases as the overdrive voltage increases! Explain this apparent discrepancy between Eqs. (11.180) and (11.181). 11.27. For Fig. 11.74 (d), obtain the output impedance of source follower (λ = 0).

Vout

Figure 11.75

11.31. Repeat Problem 11.30 for the stage shown in Fig. 11.76.

11.28. Explain how the source follower shown in Fig. 11.74 (d) acts as a virtual active inductor.

VCC Vb

11.29. Using Miller’s theorem, determine the input and output poles of the CE and CS stages depicted in Fig. 11.29(a) while including the output impedance of the transistors.

V in

Q2 Vout

RS Q1

Figure 11.76

11.30. For Fig. 11.75 common-source stage, de- *11.32. Assuming λ > 0 and using Miller’s theorive expression for output impedance. rem, determine the input and output poles Take λ3 = 0. of the stages depicted in Fig. 11.77.

VDD

VDD

M2 V in

Vout

RS M1 (a)

Figure 11.77

V in

M2 V in

VDD

RS

M2

Vout

RS M1 (b)

Vout Vb

M1 (c)

510

Chapter 11 Frequency Response

11.33. Consider the amplifier shown in Fig. 11.78, where VA = ∞. Determine the poles of the circuit using (a) Miller’s approximation, and (b) the transfer function expressed by Eq. (11.70). Compare the results.

11.36. Figure 11.81 shows CE amplifier. Perform high-frequency analysis for this circuit. VCC

Rin

VCC

Vin V in

+

Q1

Vout

RB

Vout

RS Q1

Figure 11.81

11.37. Figure 11.82 shows CS amplifier. Perform exact analysis for the given circuit.

Figure 11.78

11.34. For Fig. 11.79 CS stage analyze for pole locations. Take λ = 0.

VDD RD

VDD

Rin

RD Vin

Vout

RG

Vin

RL

+ –

Vout

M1 RG

RL

M1 Figure 11.82

Figure 11.79

11.35. For Fig. 11.80, derive expression for voltage gain and cut-off frequency (higher side).

11.38. For Fig. 11.83 source follower circuits, find the effective input capacitance. Take λ = 0. VDD

VDD RL Vout

VG

Vin

M1

VB

M2

CL

Rin + –

Figure 11.83

Vin

11.39. For Fig. 11.84 cascade stage, determine input and output impedances.

Figure 11.80

RD VB Vin

RG

g CGS 1 + CGD 1 (1+ m1 ) gm2

Figure 11.84

VDD

M2 X

M1

Vout CGD2 + CDB2 CGS2 + CGD1 (1+

g m2 ) + CDB1 + CSB2 gm1

Problems 11.40. Determine the output impedance of the emitter follower depicted in Fig. 11.85, including Cμ and other capacitances. Sketch |Zout | as a function of frequency. Assume VA = ∞. VCC

RB

V in

Q1

Design Problems 11.44. We wish to design the CE stage of Fig. 11.88 for an input pole at 500 MHz and an output pole at 2 GHz. Assuming IC = 1 mA, Cπ = 20 fF, Cμ = 5 fF, CCS = 10 fF, and VA = ∞, and using Miller’s theorem, determine the values of RB and RC such that the (low-frequency) voltage gain is maximized. You may need to use iteration. VCC

Z out

RC

Figure 11.85 V in

11.41. In the cascode of Fig. 11.86, Q 3 serves as a constant current source, providing 75% of the bias current of Q 1 . Assuming VA = ∞ and using Miller’s theorem, determine the poles of the circuit. Is Miller’s effect more or less significant here than in the standard cascode topology of Fig. 11.48(a)? VCC V b2

RC

Q3

Vout V b1

Q2

511

Vout

RB Q1

Figure 11.88

11.45. We wish to design the common-base stage of Fig. 11.89 for a −3 dB bandwidth of 10 GHz. Assume IC = 1 mA, VA = ∞, RS = 50 , Cπ = 20 fF, Cμ = 5 fF, and CCS = 20 fF. Determine the maximum allowable value of RC and hence the maximum achievable gain. (Note that the input and output poles may affect the bandwidth.) VCC

V in

RB

RC

Q1

Vout

Figure 11.86

Vb

11.42. For Fig. 11.84 Cascode MOSFET stage, find the pole frequencies. **11.43. In analogy with the circuit of Fig. 11.86, a student constructs the stage depicted in Fig. 11.87 but mistakenly uses an NMOS device for M3 . Assuming λ = 0 and using Miller’s theorem, compute the poles of the circuit.

V in

Q1

RS

Figure 11.89

11.46. The emitter follower of Fig. 11.90 must be designed for an input capacitance of VCC V in

Q1

VDD V b2

M3

Vout

RD

RL

Vout V b1 V in

RG

Figure 11.87

M2 M1

Figure 11.90

less than 50 fF. If Cμ = 10 fF, Cπ = 100 fF, VA = ∞, and IC = 1 mA, what is the minimum tolerable value of RL ?

512

Chapter 11 Frequency Response

11.47. An NMOS source follower must drive a load resistance of 100 with a voltage gain of 0.8. If ID = 1 mA, μnC ox = 100 μA/V2 , C ox = 12 fF/μm2 , and L = 0.18 μm, what is the minimum input capacitance that can be achieved? Assume λ = 0, CGD ≈ 0, CSB ≈ 0, and CGS = (2/3)WLCox .

unit width. Determine the maximum allowable values of RG , RD , and the voltage gain. Use Miller’s approximation forCGD1 . Assume an overdrive voltage of 200 mV for each transistor. VDD

11.48. We wish to design the MOS cascode of Fig. 11.91 for an input pole of 5 GHz and an output pole of 10 GHz. Assume M1 and M2 are identical, ID = 0.5 mA, CGS = (2/3)WLCox , Cox = 12 fF/μm2 , μnC ox = 100 μA/V2 , λ = 0, L = 0.18 μm, and CGD = C 0 W, where C 0 = 0.2fF/μm denotes the gate-drain capacitance per

RD Vout Vb V in

M2

RG M1

Figure 11.91

SPICE PROBLEMS In the following problems, use the MOS device models given in Appendix A. For bipolar transistors, assume IS,npn = 5 × 10−16 A, βnpn = 100, VA,npn = 5 V, IS,pnp = 8 × 10−16 A, βpnp = 50, VA,pnp = 3.5 V. Also, SPICE models the effect of charge storage in the base by a parameter called τF = Cb/gm. Assume τF (tf ) = 20 ps. 11.1. In the two-stage amplifier shown in Fig. 11.92, W/L = 10 μm/0.18 μm for M1 -M4 . (a) Select the input dc level to obtain an output dc level of 0.9 V. (b) Plot the frequency response and compute the low-frequency gain and the −3 dB bandwidth. (c) Repeat (a) and (b) for W = 20 μm and compare the results. VDD = 1.8 V M2 M3 V in

(a) Select the input dc level to obtain an output dc level of 1.2 V. (b) Plot the frequency response and compute the low-frequency gain and the −3 dB bandwidth. VCC = 2.5 V 1 kΩ

V in

1 kΩ

Vout

5 kΩ

Q2

Q1

Figure 11.93

11.3. The self-biased stage depicted in Fig. 11.94 must drive a load capacitance of 50 fF with a maximum gain-bandwidth product (= midband gain × unity-gain bandwidth). Assuming R1 = 500 and L1 = 0.18 μm, determine W1 , RF , and RD .

Vout

M1

VDD = 1.8 V

M4

RD RF

Figure 11.92 V in

11.2. The circuit of Fig. 11.93 must drive a load capacitance of 100 fF.

Vout

100 pF R 1

Figure 11.94

M1

CL

Chapter

12

Feedback

Feedback is an integral part of our lives. Try touching your fingertips together with your eyes closed; you may not succeed the first time because you have broken a feedback loop that ordinarily “regulates” your motions. The regulatory role of feedback manifests itself in biological, mechanical, and electronic systems, allowing precise realization of “functions.” For example, an amplifier targeting a precise gain of 2.00 is designed much more easily with feedback than without. This chapter deals with the fundamentals of (negative) feedback and its application to electronic circuits. The outline is shown below.

General Considerations • Elements of Feedback Systems

➤

Amplifiers and Sense/Return Methods • Types of Amplifiers

• Loop Gain

• Amplifier Models

• Properties of Negative Feedback

• Sense/Return Methods

12.1

➤

Analysis of Feedback Circuits • Four Types of Feedback • Effect of Finite I/O Impedances

➤

Stability and Compensation • Loop Instability • Phase Margin • Frequency Compensation

• Polarity of Feedback

GENERAL CONSIDERATIONS As soon as he reaches the age of 18, John eagerly obtains his driver’s license, buys a used car, and begins to drive. Upon his parents’ stern advice, John continues to observe the speed limit while noting that every other car on the highway drives faster. He then reasons that the speed limit is more of a “recommendation” and exceeding it by a small amount would not be harmful. Over the ensuing months, John gradually raises his speed so as to catch up with the rest of the drivers on the road, only to see flashing lights in his rear-view mirror one day. He pulls over to the shoulder of the road, listens to the sermon given by the police officer, receives a speeding ticket, and, dreading his parents’ reaction, drives home—now strictly adhering to the speed limit.

513

514

Chapter 12 Feedback Feedforward System

X Comparison Mechanism

Sense Mechanism

XF

Output Port of Feedback Network

Figure 12.1

Y

A1

K Feedback Network

Input Port of Feedback Network

General feedback system.

John’s story exemplifies the “regulatory” or “corrective” role of negative feedback. Without the police officer’s involvement, John would probably continue to drive increasingly faster, eventually becoming a menace on the road. Shown in Fig. 12.1, a negative feedback system consists of four essential components. (1) The “feedforward” system:1 the main system, probably “wild” and poorly controlled. John, the gas pedal, and the car form the feedforward system, where the input is the amount of pressure that John applies to the gas pedal and the output is the speed of the car. (2) Output sense mechanism: a means of measuring the output. The police officer’s radar serves this purpose here. (3) Feedback network: a network that generates a “feedback signal,” XF , from the sensed output. The police officer acts as the feedback network by reading the radar display, walking to John’s car, and giving him a speeding ticket. The quantity K = XF /Y is called the “feedback factor.” (4) Comparison or return mechanism: a means of subtracting the feedback signal from the input to obtain the “error,” E = X − XF . John makes this comparison himself, applying less pressure to the gas pedal—at least for a while. The feedback in Fig. 12.1 is called “negative” because XF is subtracted from X. Positive feedback, too, finds application in circuits such as oscillators and digital latches. If K = 0, i.e., no signal is fed back, then we obtain the “open-loop” system. If K = 0, we say the system operates in the “closed-loop” mode. As seen throughout this chapter, analysis of a feedback system requires expressing the closed-loop parameters in terms of the open-loop parameters. Note that the input port of the feedback network refers to that sensing the output of the forward system. As our first step towards understanding the feedback system of Fig. 12.1, let us determine the closed-loop transfer function Y/X. Since XF = KY, the error produced by the subtractor is equal to X − KY, which serves as the input of the forward system: (X − KY)A1 = Y.

(12.1)

Y A1 . = X 1 + KA1

(12.2)

That is,

This equation plays a central role in our treatment of feedback, revealing that negative feedback reduces the gain from A1 (for the open-loop system) to A1 /(1 + KA1 ). 1

Also called the “forward” system.

12.1 General Considerations

515

The quantity A1 /(1 + KA1 ) is called the “closed-loop gain.” Why do we deliberately lower the gain of the circuit? As explained in Section 12.2, the benefits accruing from negative feedback very well justify this reduction of the gain. Example 12.1

Analyze the noninverting amplifier of Fig. 12.2 from a feedback point of view.

X

A1

Y R1

XF

R2

Figure 12.2 Solution

The op amp A1 performs two functions: subtraction of X and XF and amplification. The network R1 and R2 also performs two functions: sensing the output voltage and providing a feedback factor of K = R2 /(R1 + R2 ). Thus, Eq. (12.2) gives Y = X

A1 , R2 1+ A1 R1 + R 2

(12.3)

which is identical to the result obtained in Chapter 8. Exercise

Perform the above analysis if R2 = ∞. It is instructive to compute the error, E, produced by the subtractor. Since E = X − XF and XF = KA1 E, E=

X , 1 + KA1

(12.4)

suggesting that the difference between the feedback signal and the input diminishes as KA1 increases. In other words, the feedback signal becomes a close “replica” of the input (Fig. 12.3). This observation leads to a great deal of insight into the operation of feedback systems.

X

Good Replica

Figure 12.3

A1 XF

R1 R2

Feedback signal as a good replica of the input.

516

Chapter 12 Feedback

Example 12.2

Explain why in the circuit of Fig. 12.2, Y/X approaches 1 + R1 /R2 as [R2 / (R1 + R2 )]A1 becomes much greater than unity.

Solution

If KA1 = [R2 /(R1 + R2 )]A1 is large, XF becomes almost identical to X, i.e., XF ≈ X. The voltage divider therefore requires that Y

R2 ≈X R1 + R 2

(12.5)

and hence Y R1 ≈1+ . X R2

(12.6)

Of course, Eq. (12.3) yields the same result if [R2 /(R1 + R2 )]A1 1. Exercise

Repeat the above example if R2 = ∞.

12.1.1 Loop Gain In Fig. 12.1, the quantity KA1 , which is equal to product of the gain of the forward system and the feedback factor, determines many properties of the overall system. Called the “loop gain,” KA1 has an interesting interpretation. Let us set the input X to zero and “break” the loop at an arbitrary point, e.g., as depicted in Fig. 12.4(a).

A1

A1 VN

N

K

K

M

V test

(a)

Figure 12.4

(b)

Computation of the loop gain by (a) breaking the loop and (b) applying a test signal.

The resulting topology can be viewed as a system with an input M and an output N. Now, as shown in Fig. 12.4(b), let us apply a test signal at M and follow it through the feedback network, the subtractor, and the forward system to obtain the signal at N.2 The input of A1 is equal to −KVtest , yielding VN = −KVtest A1

2

We use voltage quantities in this example, but other quantities work as well.

(12.7)

12.1 General Considerations

517

and hence KA1 = −

VN . Vtest

(12.8)

In other words, if a signal “goes around the loop,” it experiences a gain equal to −KA1 ; hence the term “loop gain.” It is important not to confuse the closed-loop gain, A1 /(1 + KA1 ), with the loop gain, KA1 .

Example 12.3

Compute the loop gain of the feedback system of Fig. 12.1 by breaking the loop at the input of A1 .

Solution

Illustrated in Fig. 12.5 is the system with the test signal applied to the input of A1 . The output of the feedback network is equal to KA1 Vtest , yielding VN = −KA1 Vtest

(12.9)

and hence the same result as in Eq. (12.8).

N VN

M

Y

A1

V test

K Figure 12.5 Exercise

Compute the loop gain by breaking the loop at the input of the subtractor.

The reader may wonder if an ambiguity exists with respect to the direction of the signal flow in the loop gain test. For example, can we modify the topology of Fig. 12.4(b) as shown in Fig. 12.6? This would mean applying Vtest to the output of A1 and expecting to observe a signal at its input and eventually at N. While possibly yielding a finite value, such a test does not represent the actual behavior of the circuit. In the feedback system, the signal flows from the input of A1 to its output and from the input of the feedback network to its output. X

A1 V test

K VN

Figure 12.6

Incorrect method of applying test signal.

518

Chapter 12 Feedback

12.2

PROPERTIES OF NEGATIVE FEEDBACK 12.2.1 Gain Desensitization Suppose A1 in Fig. 12.1 is an amplifier whose gain is poorly controlled. For example, a CS stage provides a voltage gain of gmRD while both gm and RD vary with process and temperature; the gain thus may vary by as much as ±20%. Also, suppose we require a voltage gain of 4.00.3 How can we achieve such precision? Equation (12.2) points to a potential solution: if KA1 1, we have 1 Y ≈ , X K

(12.10)

a quantity independent of A1 . From another perspective, Eq. (12.4) indicates that KA1 1 leads to a small error, forcing XF to be nearly equal to X and hence Y nearly equal to X/K. Thus, if K can be defined precisely, then A1 impacts Y/X negligibly and a high precision in the gain is attained. The circuit of Fig. 12.2 exemplifies this concept very well. If A1 R2 /(R1 + R2 ) 1, then 1 Y ≈ X K ≈1+

(12.11) R1 . R2

(12.12)

Why is R1 /R2 more precisely defined than gmRD is? If R1 and R2 are made of the same material and constructed identically, then the variation of their value with process and temperature does not affect their ratio. As an example, for a closed-loop gain of 4.00, we choose R1 = 3R2 and implement R1 as the series combination of three “unit” resistors equal to R2 . Illustrated in Fig. 12.7, the idea is to ensure that R1 and R2 “track” each other; if R2 increases by 20%, so does each unit in R1 and hence the total value of R1 , still yielding a gain of 1 + 1.2R1 /(1.2R2 ) = 4.

R1 R2

Figure 12.7

Construction of resistors for good matching.

Example 12.4

The circuit of Fig. 12.2 is designed for a nominal gain of 4. (a) Determine the actual gain if A1 = 1000. (b) Determine the percentage change in the gain if A1 drops to 500.

Solution

For a nominal gain of 4, Eq. (12.12) implies that R1 /R2 = 3. (a) The actual gain is given by Y A1 = X 1 + KA1

(12.13)

= 3.984.

(12.14)

3 Some analog-to-digital converters (ADCs) require very precise voltage gains. For example, a 10-bit ADC may call for a gain of 2.000.

12.2 Properties of Negative Feedback

519

Note that the loop gain KA1 = 1000/4 = 250. (b) If A1 falls to 500, then Y = 3.968. X

(12.15)

Thus, the closed-loop gain changes by only (3.984/3.968)/3.984 = 0.4% if A1 drops by factor of 2. Exercise

Determine the percentage change in the gain if A1 falls to 200.

The above example reveals that the closed-loop gain of a feedback circuit becomes relatively independent of the open-loop gain so long as the loop gain, KA1 , remains sufficiently higher than unity. This property of negative feedback is called “gain desensitization.” We now see why we are willing to accept a reduction in the gain by a factor of 1 + KA1 . We begin with an amplifier having a high, but poorly-controlled gain and apply negative feedback around it so as to obtain a better-defined, but inevitably lower gain. This concept was also extensively employed in the op amp circuits described in Chapter 8. The gain desensitization property of negative feedback means that any factor that influences the open-loop gain has less effect on the closed-loop gain. Thus far, we have blamed only process and temperature variations, but many other phenomena change the gain as well. • As the signal frequency rises, A1 may fall, but A1 /(1 + KA1 ) remains relatively constant. We therefore expect that negative feedback increases the bandwidth (at the cost of gain). • If the load resistance changes, A1 may change; e.g., the gain of a CS stage depends on the load resistance. Negative feedback, on the other hand, makes the gain less sensitive to load variations. • The signal amplitude affects A1 because the forward amplifier suffers from nonlinearity. For example, the large-signal analysis of differential pairs in Chapter 10 reveals that the small-signal gain falls at large input amplitudes. With negative feedback, however, the variation of the open-loop gain due to nonlinearity manifests itself to a lesser extent in the closed-loop characteristics. That is, negative feedback improves the linearity. We now study these properties in greater detail.

12.2.2 Bandwidth Extension Let us consider a one-pole open-loop amplifier with a transfer function A1 (s) =

A0 1+

s . ω0

(12.16)

Here, A0 denotes the low-frequency gain and ω0 the −3 dB bandwidth. Noting from Eq. (12.2) that negative feedback lowers the low-frequency gain by a factor of 1 + KA1 , we wish to determine the resulting bandwidth improvement. The closed-loop transfer

520

Chapter 12 Feedback function is obtained by substituting Eq. (12.16) for A1 in Eq. (12.2): A0 Y = X

1+ 1+K

s ω0 A0

1+

.

(12.17)

s ω0

Multiplying the numerator and the denominator by 1 + s/ω0 gives Y A0 (s) = s X 1 + KA0 + ω0

(12.18)

A0 1 + KA0 = . s 1+ (1 + KA0 )ω0

(12.19)

In analogy with Eq. (12.16), we conclude that the closed-loop system now exhibits: Closed−Loop Gain =

A0 1 + KA0

Closed−Loop Bandwidth = (1 + KA0 )ω0 .

(12.20) (12.21)

In other words, the gain and bandwidth are scaled by the same factor but in opposite directions, displaying a constant product. Example 12.5

Plot the closed-loop frequency response given by Eq. (12.19) for K = 0, 0.1, and 0.5. Assume A0 = 200.

Solution

For K = 0, the feedback vanishes and Y/X reduces to A1 (s) as given by Eq. (12.16). For K = 0.1, we have 1 + KA0 = 21, noting that the gain decreases and the bandwidth increases by the same factor. Similarly, for K = 0.5, 1 + KA0 = 101, yielding a proportional reduction in gain and increase in bandwidth. The results are plotted in Fig. 12.8.

A0

K=0 K = 0.1 K = 0.5

ω Figure 12.8 Exercise

Repeat the above example for K = 1.

12.2 Properties of Negative Feedback

521

Example 12.6

Prove that the unity-gain bandwidth of the above system remains independent of K if 1 + KA0 1 and K2 1.

Solution

The magnitude of Eq. (12.19) is equal to Y ( jω) = X

A0 1 + KA0 1+

.

ω2

(12.22)

(1 + KA0 )2 ω02

Equating this result to unity and squaring both sides, we write

A0 1 + KA0

2 =1+

ωu2 (1 + KA0 )2 ω02

,

(12.23)

where ωu denotes the unity-gain bandwidth. It follows that ωu = ω0 A20 − (1 + KA0 )2

(12.24)

≈ ω0 A20 − K2 A20

(12.25)

≈ ω0 A0 ,

(12.26)

which is equal to the gain-bandwidth product of the open-loop system. Figure 12.9 depicts the results.

A0

0 dB

ω0

A 0 ω0

ω

Figure 12.9

Exercise

If A0 = 1000, ω0 = 2π × (10 MHz), and K = 0.5, calculate the unity-gain bandwidth from Eqs. (12.24) and (12.26) and compare the results.

12.2.3 Modification of I/O Impedances As mentioned above, negative feedback makes the closed-loop gain less sensitive to the load resistance. This effect fundamentally arises from the modification of the output impedance as a result of feedback. Feedback modifies the input impedance as well. We will formulate these effects carefully in the following sections, but it is instructive to study an example at this point.

522

Chapter 12 Feedback

Example 12.7

Figure 12.10 depicts a transistor-level realization of the feedback circuit shown in Fig. 12.2. Assume λ = 0 and R1 + R2 RD for simplicity. (a) Identify the four components of the feedback system. (b) Determine the open-loop and closed-loop voltage gain. (c) Determine the open-loop and closed-loop I/O impedances.

VDD RD Vout R1 M1 V in

R2

Figure 12.10 Solution

(a) In analogy with Fig. 12.10, we surmise that the forward system (the main amplifier) consists of M1 and RD , i.e., a common-gate stage. Resistors R1 and R2 serve as both the sense mechanism and the feedback network, returning a signal equal to Vout R2 /(R1 + R2 ) to the subtractor. Transistor M1 itself operates as the subtractor because the smallsignal drain current is proportional to the difference between the gate and source voltages: i D = gm(vG − vS ).

(12.27)

(b) The forward system provides a voltage gain equal to A0 ≈ gmRD

(12.28)

because R1 + R2 is large enough that its loading on RD can be neglected. The closed-loop voltage gain is thus given by vout A0 = vin 1 + KA0 =

gmRD . R2 1+ gmRD R1 + R 2

(12.29) (12.30)

We should note that the overall gain of this stage can also be obtained by simply solving the circuit’s equations—as if we know nothing about feedback. However, the use of feedback concepts both provides a great deal of insight and simplifies the task as circuits become more complex. (c) The open-loop I/O impedances are those of the CG stage: Rin,open =

1 gm

Rout,open = RD .

(12.31) (12.32)

12.2 Properties of Negative Feedback

523

At this point, we do not know how to obtain the closed-loop I/O impedances in terms of the open-loop parameters. We therefore simply solve the circuit. From Fig. 12.11(a), we recognize that RD carries a current approximately equal to iX because R1 + R2 is assumed large. The drain voltage of M1 is thus given by iX RD , leading to a gate voltage equal to +iX RD R2 /(R1 + R2 ). Transistor M1 generates a drain current proportional to vGS : i D = gmvGS +iX RD R2 = gm − vX . R1 + R 2

(12.33) (12.34)

Since i D = −iX , Eq. (12.34) yields vX R2 1 1+ = gmRD . iX gm R1 + R 2

(12.35)

That is, the input resistance increases from 1/gm by a factor equal to 1 + gmRD R2 /(R1 + R2 ), the same factor by which the gain decreases. VDD

VDD

RD

RD M1

iX

R1

R1 M1

iX

R2

vX

R2

vX (a)

(b)

Figure 12.11

To determine the output resistance, we write from Fig. 12.11(b), vGS =

R2 vX , R1 + R 2

(12.36)

and hence i D = gmvGS = gm

R2 vX . R1 + R 2

(12.37) (12.38)

Noting that, if R1 + R2 RD , then iX ≈ i D + vX /RD , we obtain iX ≈ gm

R2 vX vX + . R1 + R 2 RD

(12.39)

524

Chapter 12 Feedback It follows that vX = iX

RD . R2 1+ gmRD R1 + R 2

(12.40)

The output resistance thus decreases by the “universal” factor 1 + gmRD R2 / (R1 + R2 ). The above computation of I/O impedances can be greatly simplified if feedback concepts are employed. As exemplified by Eqs. (12.35) and (12.40), the factor 1 + KA0 = 1 + gmRD R2 /(R1 + R2 ) plays a central role here. Our treatment of feedback circuits in this chapter will provide the foundation for this point. Exercise

In some applications, the input and output impedances of an amplifier must both be equal to 50 . What relationship guarantees that the input and output impedances of the above circuit are equal?

The reader may raise several questions at this point. Do the input impedance and the output impedance always scale down and up, respectively? Is the modification of I/O impedances by feedback desirable? We consider one example here to illustrate a point and defer more rigorous answers to subsequent sections.

Example 12.8

The common-gate stage of Fig. 12.10 must drive a load resistance RL = RD /2. How much does the gain change (a) without feedback, (b) with feedback?

Solution

(a) Without feedback [Fig. 12.12(a)], the CG gain is equal to gm(RD ||RL ) = gmRD /3. That is, the gain drops by factor of three. VDD RD Vout M1

Vb

R L=

RD 2

V in

Figure 12.12

(b) With feedback, we use Eq. (12.30) but recognize that the open-loop gain has fallen to gmRD /3: vout = vin

=

gmRD /3 R2 1+ gmRD /3 R1 + R 2 gmRD . R2 3+ gmRD R1 + R 2

(12.41)

(12.42)

12.2 Properties of Negative Feedback

525

For example, if gmRD R2 /(R1 + R2 ) = 10, then this result differs from the “unloaded” gain expression in Eq. (12.30) by about 18%. Feedback therefore desensitizes the gain to load variations. Exercise

Repeat the above example for RL = RD .

12.2.4 Linearity Improvement Consider a system having the input/output characteristic shown in Fig. 12.13(a). The nonlinearity observed here can also be viewed as the variation of the slope of the characteristic, i.e., the small-signal gain. For example, this system exhibits a gain of A1 near x = x1 and A2 near x = x2 . If placed in a negative-feedback loop, the system provides a more uniform gain for different signal levels and, therefore, operates more linearly. In fact, as illustrated in Fig. 12.13(b) for the closed-loop system, we can write Gain at x1 =

≈

A1 1 + KA1

(12.43)

1 1 , 1− K KA1

(12.44)

A2 1 + KA2

(12.45)

where it is assumed KA1 1. Similarly, Gain at x2 =

1 1 1− . ≈ K KA2

(12.46)

Thus, so long as KA1 and KA2 are large, the variation of the closed-loop gain with the signal level remains much less than that of the open-loop gain. All of the above attributes of negative feedback can also be considered a result of the minimal error property illustrated in Fig. 12.3. For example, if at different signal levels, the forward amplifier’s gain varies, the feedback still ensures the feedback signal is a close replica of the input, and so is the output.

y

y

Open–Loop Characteristic

A2

Closed–Loop Characteristic A2

A1

1 + K A2

x1

x2

x

x1

A1

x2

x

1 + K A1 (a)

(b)

(a) Nonlinear open-loop characteristic of an amplifier, (b) improvement in linearity due to feedback.

Figure 12.13

526

Chapter 12 Feedback

12.3

TYPES OF AMPLIFIERS The amplifiers studied thus far in this book sense and produce voltages. While less intuitive, other types of amplifiers also exist, i.e., those that sense and/or produce currents. Figure 12.14 depicts the four possible combinations along with their input and output impedances in the ideal case. For example, a circuit sensing a current must display a low input impedance to resemble a current meter. Similarly, a circuit generating an output current must achieve a high output impedance to approximate a current source. The reader is encouraged to confirm the other cases as well. The distinction among the four types of amplifiers becomes important in the analysis of feedback circuits. Note that the “currentvoltage” and “voltage-current” amplifiers of Figs. 12.14(b) and (c) are commonly known as “transimpedance” and “transconductance” amplifiers, respectively. A0 V in

R in =

R0

R out = 0

Vout

I in

R in = 0

(a)

Gm V in

R in =

Vout

(b)

Al

I out I in

R out =

I out

R in = 0

(c)

Figure 12.14

R out = 0

R out = (d)

(a) Voltage, (b) transimpedance, (c) transconductance, and (d) current amplifiers.

12.3.1 Simple Amplifier Models For our studies later in this chapter, it is beneficial to develop simple models for the four amplifier types. Depicted in Fig. 12.15 are the models for the ideal case. The voltage amplifier in Fig. 12.15(a) provides an infinite input impedance so that it can sense voltages as an ideal voltmeter, i.e., without loading the preceding stage. Also, the circuit exhibits a

v in

v out A 0 v in (a)

v in

R0 I in

i in (b)

i out G mv in

(c)

v out

i out A I i in

i in (d)

Ideal models for (a) voltage, (b) transimpedance, (c) transconductance, and (d) current amplifiers.

Figure 12.15

12.3 Types of Amplifiers R out

v in

v out

v in

R in

v out

A 0 v in

R in

A 0 v in

(a)

i in

R0 i in (d)

R out

v out

R0 i in

R in

(b)

v out

R in

R out

i in

527

(c)

i in

v in G mv in

R in (e)

R out

A I i in

R in

R out

(f)

(a) Realistic model of voltage amplifier, (b) incorrect voltage amplifier model, (c) realistic model of transimpedance amplifier, (d) incorrect model of transimpedance amplifier, (e) realistic model of transconductance amplifier, (f) realistic model of current amplifier.

Figure 12.16

zero output impedance so as to serve as an ideal voltage source, i.e., deliver vout = A0 vin regardless of the load impedance. The transimpedance amplifier in Fig. 12.15(b) has a zero input impedance so that it can measure currents as an ideal current meter. Similar to the voltage amplifier, the output impedance is also zero if the circuit operates as an ideal voltage source. Note that the “transimpedance gain” of this amplifier, R0 = vout /i in , has a dimension of resistance. For example, a transimpedance gain of 2 k means a 1-mA change in the input current leads to a 2-V change at the output. The I/O impedances of the topologies in Figs. 12.15(c) and (d) follow similar observations. It is worth noting that the amplifier of Fig. 12.15(c) has a “transconductance gain,” Gm = i out /vin , with a dimension of transconductance. In reality, the ideal models in Fig. 12.15 may not be accurate. In particular, the I/O impedances may not be negligibly large or small. Figure 12.16 shows more realistic models of the four amplifier types. Illustrated in Fig. 12.16(a), the voltage amplifier model contains an input resistance in parallel with the input port and an output resistance in series with the output port. These choices are unique and become clearer if we attempt other combinations. For example, if we envision the model as shown in Fig. 12.16(b), then the input and output impedances remain equal to infinity and zero, respectively, regardless of the values of Rin and Rout . (Why?) Thus, the topology of Fig. 12.16(a) serves as the only possible model representing finite I/O impedances. Figure 12.16(c) depicts a nonideal transimpedance amplifier. Here, the input resistance appears in series with the input. Again, if we attempt a model such as that in Fig. 12.16(d), the input resistance is zero. The other two amplifier models in Figs. 12.16(e) and (f) follow similar concepts. 12.3.2 Examples of Amplifier Types It is instructive to study examples of the above four types. Figure 12.17(a) shows a cascade of a CS stage and a source follower as a “voltage amplifier.” The circuit indeed provides a high input impedance (similar to a voltmeter) and a low output impedance (similar to a voltage source). Figure 12.17(b) depicts a cascade of a CG stage and a source follower as a transimpedance amplifier. Such a circuit displays low input and output impedances to serve as a “current sensor” and a “voltage generator.” Figure 12.17(c) illustrates a single

528

Chapter 12 Feedback VDD

VDD

RD

RD M2

V in

M1

R out =

R in =

M2

Vout 1 g m2

I in

V in

M1

(c)

Figure 12.17

R out =

1 g m2

(b)

I out R out = r O

M1 I in

R in =

Vout

R in = 1 g m1

(a)

I out

Vb

M1

R out = Vb

R in = 1 g m1 (d)

Examples of (a) voltage, (b) transimpedance, (c) transconductance, and (d) current

amplifiers.

MOSFET as a transconductance amplifier. With high input and output impedances, the circuit efficiently senses voltages and generates currents. Finally, Fig. 12.17(d) shows a common-gate transistor as a current amplifier. Such a circuit must provide a low input impedance and a high output impedance. Let us also determine the small-signal “gain” of each circuit in Fig. 12.17, assuming λ = 0 for simplicity. The voltage gain, A0 , of the cascade in Fig. 12.17(a) is equal to −gmRD if λ = 0.4 The gain of the circuit in Fig. 12.17(b) is defined as vout /i in , called the “transimpedance gain,” and denoted by RT . In this case, i in flows through M1 and RD , generating a voltage equal to i in RD at both the drain of M1 and the source of M2 . That is, vout = i in RD and hence RT = RD . For the circuit in Fig. 12.17(c), the gain is defined as i out /vin , called the “transconductance gain,” and denoted by Gm. In this example, Gm = gm. For the current amplifier in Fig. 12.17(d), the current gain, AI , is equal to unity because the input current simply flows to the output.

Example 12.9

With a current gain of unity, the topology of Fig. 12.17(d) appears hardly better than a piece of wire. What is the advantage of this circuit?

Solution

The important property of this circuit lies in its input impedance. Suppose the current source serving as the input suffers from a large parasitic capacitance, C p . If applied directly to a resistor RD [Fig. 12.18(a)], the current would be wasted 4

Recall from Chapter 7 that the gain of the source follower is equal to unity in this case.

12.4 Sense and Return Techniques

529

VDD RD Vout Vb

M1 Vout i in

CP

i in

RD

(a)

CP

I1

(b)

Figure 12.18

through C p at high frequencies, exhibiting a −3 dB bandwidth of only (RDC p )−1 . On the other hand, the use of a CG stage [Fig. 12.18(b)] moves the input pole to gm/C p , a much higher frequency. Exercise

Determine the transfer function Vout /Iin for each of the above circuits.

12.4

SENSE AND RETURN TECHNIQUES Recall from Section 12.1 that a feedback system includes means of sensing the output and “returning” the feedback signal to the input. In this section, we study such means so as to recognize them easily in a complex feedback circuit. How do we measure the voltage across a port? We place a voltmeter in parallel with the port, and require that the voltmeter have a high input impedance so that it does not disturb the circuit [Fig. 12.19(a)]. By the same token, a feedback circuit sensing an output voltage must appear in parallel with the output and, ideally, exhibit an infinite impedance [Fig. 12.19(b)]. Shown in Fig. 12.19(c) is an example in which the resistive divider consisting of R1 and R2 senses the output voltage and generates the feedback signal, vF . To approach the ideal case, R1 + R2 must be very large so that A1 does not “feel” the effect of the resistive divider. How do we measure the current flowing through a wire? We break the wire and place a current meter in series with the wire [Fig. 12.20(a)]. The current meter in fact consists of a small resistor, so that it does not disturb the circuit, and a voltmeter that measures

Feedforward System

Vout

V in

A1 R1

Voltmeter

V out

Feedback Network (a)

Vout

(b)

VF R2 (c)

(a) Sensing a voltage by a voltmeter, (b) sensing the output voltage by the feedback network, (d) example of implementation.

Figure 12.19

530

Chapter 12 Feedback I out

I out RL

RL

r

Current Meter Voltmeter (a)

(b)

I out Feedforward System

M1 I out

VF

Feedback Network

RS 0

(c)

(d)

(a) Sensing a current by a current meter, (b) actual realization of current meter, (c) sensing the output current by the feedback network, (d) example of implementation.

Figure 12.20

the voltage drop across the resistor [Fig. 12.20(b)]. Thus, a feedback circuit sensing an output current must appear in series with the output and, ideally, exhibit a zero impedance [Fig. 12.20(c)]. Depicted in Fig. 12.20(d) is an implementation of this concept. A resistor placed in series with the source of M1 senses the output current, generating a proportional feedback voltage, VF . Ideally, RS is so small ( 1/gm1 ) that the operation of M1 remains unaffected. To return a voltage or current to the input, we must employ a mechanism for adding or subtracting such quantities.5 To add two voltage sources, we place them in series [Fig. 12.21(a)]. Thus, a feedback network returning a voltage must appear in series with the input signal [Fig. 12.21(b)], so that ve = vin − vF .

(12.47)

For example, as shown in Fig. 12.21(c), a differential pair can subtract the feedback voltage from the input. Alternatively, as mentioned in Example 12.7, a single transistor can operate as a voltage subtractor [Fig. 12.21(d)]. To add two current sources, we place them in parallel [Fig. 12.22(a)]. Thus, a feedback network returning a current must appear in parallel with the input signal, Fig. 12.22(b), so that i e = i in − iF .

(12.48)

For example, a transistor can return a current to the input [Fig. 12.22(c)]. So can a resistor if it is large enough to approximate a current source [Fig. 12.22(d)]. 5 Of course, only quantities having the same dimension can be added or subtracted. That is, a voltage cannot be added to a current.

12.4 Sense and Return Techniques

v in

v1

ve

Feedforward System

vF

Feedback Network

v2

(a)

v in

(b)

vF vF

M1

v in

M1

v in

vF

(c)

(d)

(a) Addition of two voltages, (b) addition of feedback and input voltages, (c) differential pair as a voltage subtractor, (d) single transistor as a voltage subtractor.

Figure 12.21

ie Feedforward System

i in i1

iF

i2

Feedback Network (b)

(a)

ie

i in

ie

iF

iF

i in

M1

RF

(c)

(d)

(a) Addition of two currents, (b) addition of feedback current and input current, (c) circuit realization, (d) another realization.

Figure 12.22

Example 12.10

Determine the types of sensed and returned signals in the circuit of Fig. 12.23. VDD M3

M4 v out R1

v in

M1

M2 I SS

Figure 12.23

vF R2

531

532

Chapter 12 Feedback

Solution

This circuit is an implementation of the noninverting amplifier shown in Fig. 12.2. Here, the differential pair with the active load plays the role of an op amp. The resistive divider senses the output voltage and serves as the feedback network, producing vF = [R2 /(R1 + R2 )]vout . Also, M1 and M2 operate as both part of the op amp (the forward system) and a voltage subtractor. The amplifier therefore combines the topologies in Figs. 12.19(c) and 12.21(c).

Exercise

Repeat the above example if R2 = ∞.

Example 12.11

Compute the feedback factor, K, for the circuit depicted in Fig. 12.24. Assume λ = 0. VDD R D1

R D2

Vout

M2 M1 I in

iF MF

Figure 12.24 Solution

Transistor MF both senses the output voltage and returns a current to the input. The feedback factor is thus given by iF = gmF , (12.49) K= vout where gmF denotes the transconductance of MF .

Exercise

Calculate the feedback factor if MF is degenerated by a resistor of value RS . Let us summarize the properties of the “ideal” feedback network. As illustrated in Fig. 12.25(a), we expect such a network to exhibit an infinite input impedance if sensing a voltage and a zero input impedance if sensing a current. Moreover, the network must provide a zero output impedance if returning a voltage and an infinite output impedance if returning a current.

12.5

POLARITY OF FEEDBACK While the block diagram of a feedback system, e.g., Fig. 12.1, readily reveals the polarity of feedback, an actual circuit implementation may not. The procedure of determining this polarity involves three steps: (a) assume the input signal goes up (or down); (b) follow the change through the forward amplifier and the feedback network; (c) determine whether the returned quantity opposes or enhances the original “effect” produced by the input change. A simpler procedure is as follows: (a) set the input to zero; (b) break the loop; (c) apply a test signal, V test , travel around the loop, examine the returned signal, V ret , and determine the polarity of V ret /V test .

12.5 Polarity of Feedback

533

I out V in

Vout

K

K

VF 0

I in

K

IF

K

(a)

(b)

(a) Input impedance of ideal feedback networks for sensing voltage and current quantities, (b) output impedance of ideal feedback networks for producing voltage and current quantities.

Figure 12.25

Example 12.12

Determine the polarity of feedback in the circuit of Fig. 12.26. VDD M3

M4 v out R1

v in

M1

X R2

M2 I SS

Figure 12.26 Solution

If Vin goes up, ID1 tends to increase and ID2 tends to decrease. As a result, Vout and hence VX tend to rise. The rise in VX tends to increase ID2 and decrease ID1 , counteracting the effect of the change in Vin . The feedback is therefore negative. The reader is encouraged to apply the second procedure.

Exercise

Suppose the top terminal of R1 is tied to the drain of M1 rather than the the drain of M2 . Determine the polarity of feedback.

Example 12.13

Determine the polarity of feedback in the circuit of Fig. 12.27. VDD R D1 A v in

Figure 12.27

R D2

v out

M2 M1

R F1 X R F2

534

Chapter 12 Feedback

Solution

If Vin goes up, ID1 tends to increase. Thus, VA falls, Vout rises, and so does VX . The rise in VX tends to reduce ID1 (why?), thereby opposing the effect produced by Vin . The feedback is therefore negative.

Exercise

Repeat the above example if M2 is converted to a CG stage, i.e., its source is tied to node A and its gate to a bias voltage.

Example 12.14

Determine the polarity of feedback in the circuit of Fig. 12.28. VDD R D1 Vout

X M1 I in M2

Figure 12.28

Solution

If Iin goes up, VX tends to rise (why?), thus raising ID1 . As a result, Vout falls and ID2 decreases, allowing VX to rise (why?). Since the returned signal enhances the effect produced by Iin , the polarity of feedback is positive.

Exercise

Repeat the above example if M2 is a PMOS device (still operating as a CS stage). What happens if RD → ∞? Is this result expected?

12.6

FEEDBACK TOPOLOGIES Our study of different types of amplifiers in Section 12.3 and sense and return mechanisms in Section 12.4 suggests that four feedback topologies can be constructed. Each topology includes one of four types of amplifiers as its forward system. The feedback network must, of course, sense and return quantities compatible with those produced and sensed by the forward system, respectively. For example, a voltage amplifier requires that the feedback network sense and return voltages, whereas a transimpedance amplifier must employ a feedback network that senses a voltage and returns a current. In this section, we study each topology and compute the closed-loop characteristics such as gain and I/O impedances with the assumption that the feedback network is ideal (Fig. 12.25).

12.6.1 Voltage-Voltage Feedback Illustrated in Fig. 12.29(a), this topology incorporates a voltage amplifier, requiring that the feedback network sense the output voltage and return a voltage to the subtractor. Recall from Section 12.4 that such a feedback network appears in parallel with the output and

12.6 Feedback Topologies

535

in series with the input,6 ideally exhibiting an infinite input impedance and a zero output impedance.

Vin

V1

A0

VF

K

Vout

Figure 12.29

Voltage-voltage feedback.

We first calculate the closed-loop gain. Since V1 = Vin − VF

(12.50)

Vout = A0 V1

(12.51)

VF = KVout ,

(12.52)

we have Vout = A0 (Vin − KVout ),

(12.53)

Vout A0 = , Vin 1 + KA0

(12.54)

and hence

an expected result.

Example 12.15

Determine the closed-loop gain of the circuit shown in Fig. 12.30, assuming R1 + R2 is very large. VDD M3

M4 v out R1

v in

M1

M2

vF R2

I SS

Figure 12.30

6 For this reason, this type of feedback is also called the “series-shunt” topology, where the first term refers to the return mechanism at the input and the second term to the sense mechanism at the output.

536

Chapter 12 Feedback

Solution

As evident from Examples 12.10 and 12.12, this topology indeed employs negative voltage-voltage feedback: the resistive network senses Vout with a high impedance (because R1 + R2 is very large), returning a voltage to the gate of M2 . As mentioned in Example 12.10, M1 and M2 serve as the input stage of the forward system and as a subtractor. Noting that A0 is the gain of the circuit consisting of M1 -M4 , we write from Chapter 10 A0 = gmN (rON ||rOP ),

(12.55)

where the subscripts N and P refer to NMOS and PMOS devices, respectively.7 With K = R2 /(R1 + R2 ), we obtain Vout = Vin

gmN (rON ||rOP ) . R2 1+ gmN (rON ||rOP ) R1 + R 2

(12.56)

As expected, if the loop gain remains much greater than unity, then the closed-loop gain is approximately equal to 1/K = 1 + R1 /R2 . Exercise

If gmN = 1/(100 ), rON = 5 k, and rOP = 2 k, determine the required value of R2 /(R1 + R2 ) for a closed loop gain of 4. Compare the result with the nominal value of (R2 + R1 )/R2 = 4. Feedforward System

I in

I in

V in

R in

VF

Figure 12.31

A0

K

Calculation of input impedance.

In order to analyze the effect of feedback on the I/O impedances, we assume the forward system is a nonideal voltage amplifier (i.e., it exhibits finite I/O impedances) while the feedback network remains ideal. Depicted in Fig. 12.31 is the overall topology including a finite input resistance for the forward amplifier. Without feedback, of course, the entire input signal would appear across Rin , producing an input current of Vin /Rin .8 With feedback, on the other hand, the voltage developed at the input of A0 is equal to Vin − VF and also equal to Iin Rin . Thus, Iin Rin = Vin − VF = Vin − (Iin Rin )A0 K.

(12.57) (12.58)

7 We observe that R1 + R2 must be much greater than rON ||rOP for this to hold. This serves as the definition of R1 + R2 being “very large.” 8 Note that Vin and Rin carry equal currents because the feedback network must appear in series with the input [Fig. 12.21(a)].

12.6 Feedback Topologies

537

It follows that Vin = Rin (1 + KA0 ). Iin

(12.59)

Interestingly, negative feedback around a voltage amplifier raises the input impedance by the universal factor of one plus the loop gain. This impedance modification brings the circuit closer to an ideal voltage amplifier. Example 12.16

Determine the input impedance of the stage shown in Fig. 12.32(a) if R1 + R2 is very large. VDD

VDD

RD

RD Vout R1

M1 V in

VF

Vout R1 M1

R2

R2 R in

(a)

(b)

Figure 12.32 Solution

We first open the loop to calculate Rin in Eq. (12.59). To open the loop, we break the gate of M1 from the feedback signal and tie it to ground [Fig. 12.32(b)]: Rin =

1 . gm

The closed-loop input impedance is therefore given by Vin R2 1 1+ = gmRD . Iin gm R1 + R 2 Exercise

(12.60)

(12.61)

What happens if R2 → ∞? Is this result expected?

The effect of feedback on the output impedance can be studied with the aid of the diagram shown in Fig. 12.33, where the forward amplifier exhibits an output impedance of Rout . Expressing the error signal at the input of A0 as −VF = −KVX , we write the output voltage of A0 as −KA0 VX and hence IX =

VX − (−KA0 VX ) , Rout

(12.62)

where the current drawn by the feedback network is neglected. Thus, Rout VX = , IX 1 + KA0

(12.63)

538

Chapter 12 Feedback Feedforward System

IX

A0

VX

K

VF

Figure 12.33

R out

Calculation of output impedance.

revealing that negative feedback lowers the output impedance if the topology senses the output voltage. The circuit is now a better voltage amplifier—as predicted by our gain desensitization analysis in Section 12.2. Example 12.17

Calculate the output impedance of the circuit shown in Fig. 12.34 if R1 + R2 is very large.

VDD M3

M4

iX R1

M1

M2

vX

vF R2

I SS

Figure 12.34 Solution

Recall from Example 12.15 that the open-loop output impedance is equal to rON ||rOP and KA0 = [R2 /(R1 + R2 )]gmN (rON ||rOP ). Thus, the closed-loop output impedance, Rout,closed , is given by Rout,closed =

rON ||rOP . R2 1+ gmN (rON ||rOP ) R1 + R 2

(12.64)

If the loop gain is much greater than unity, Rout,closed

1 R1 ≈ 1+ , R2 gmN

(12.65)

a value independent of rON and rOP . In other words, while the open-loop amplifier suffers from a high output impedance, the application of negative feedback lowers Rout to a multiple of 1/gmN . Exercise

What happens if R2 → ∞? Can you prove this result by direct analysis of the circuit?

12.6 Feedback Topologies

539

In summary, voltage-voltage feedback lowers the gain and the output impedance by 1 + KA0 and raises the input impedance by the same factor. 12.6.2 Voltage-Current Feedback Depicted in Fig. 12.35, this topology employs a transimpedance amplifier as the forward system, requiring that the feedback network sense the output voltage and return a current to the subtractor. In our terminology, the first term in “voltage-current feedback” refers to the quantity sensed at the output, and the second, to the quantity returned to the input. (This terminology is not standard.) Also, recall from Section 12.4 that such a feedback network must appear in parallel with the output and with the input,9 ideally providing both an infinite input impedance and an infinite output impedance (why?). Note that the feedback factor in this case has a dimension of conductance because K = IF /Vout . Ie R0

I in

Vout

IF K

Figure 12.35

Voltage-current feedback.

We first compute the closed-loop gain, expecting to obtain a familiar result. Since Ie = Iin − IF and Vout = Ie R0 , we have Vout = (Iin − IF )R0 = (Iin − KVout )R0 ,

(12.66) (12.67)

and hence Vout R0 = . Iin 1 + KR0

(12.68)

Example 12.18

For the circuit shown in Fig. 12.36(a), assume λ = 0 and RF is very large and (a) prove that the feedback is negative; (b) calculate the open-loop gain; (c) calculate the closed-loop gain.

Solution

(a) If Iin increases, ID1 decreases and VX rises. As a result, Vout falls, thereby reducing IRF . Since the currents injected by Iin and RF into the input node change in opposite directions, the feedback is negative. (b) To calculate the open-loop gain, we consider the forward amplifier without the feedback network, exploiting the assumption that RF is very large [Fig. 12.36(b)]. 9

For this reason, this type is also called “shunt-shunt” feedback.

540

Chapter 12 Feedback VDD

VDD R D1

M1 i in

R D2

X Vb RF

R D1

v out

M2

M1

i RF

R D2

X

v out v out

M2

Vb

i in

(a)

(b)

M1

Vb

1 g m1

RF

i RF

(c)

Figure 12.36

The transimpedance gain is given by the gain from Iin to VX (i.e., RD1 ) multiplied by that from VX to Vout (i.e., −gm2 RD2 ): R0 = RD1 (−gm2 RD2 ).

(12.69)

Note that this result assumes RF RD2 so that the gain of the second stage remains equal to −gm2 RD2 . (c) To obtain the closed-loop gain, we first note that the current returned by RF to the input is approximately equal to Vout /RF if RF is very large. To prove this, we consider a section of the circuit as in Fig. 12.36(c) and write IRF =

Vout RF +

1 gm1

.

(12.70)

Thus, if RF 1/gm1 , the returned current is approximately equal to Vout /RF . (We say “RF operates as a current source.”) That is, K = −1/RF , where the negative sign arises from the direction of the current drawn by RF from the input node with respect to that in Fig. 12.35. Forming 1 + KR0 , we express the closed-loop gain as Vout −gm2 RD1 RD2 = , gm2 RD1 RD2 Iin closed 1+ RF

(12.71)

which reduces to −RF if gm2 RD1 RD2 RF . It is interesting to note that the assumption that RF is very large translates to two conditions in this example: RF RD2 and RF 1/gm1 . The former arises from the output network calculations and the latter from the input network calculations. What happens if one or both of these assumptions are not valid? We deal with this (relatively common) situation in Section 12.7. Exercise

What is the closed-loop gain if RD1 → ∞? How can this result be interpreted? (Hint: the infinite open-loop gain creates a virtual ground node at the source of M1 .)

12.6 Feedback Topologies R in IX

VX

541

R0

IF K

Figure 12.37

Calculation of input impedance.

We now proceed to determine the closed-loop I/O impedances. Modeling the forward system as an ideal transimpedance amplifier but with a finite input impedance Rin (Section 12.3), we construct the test circuit shown in Fig. 12.37. Since the current flowing through Rin is equal to VX /Rin (why?), the forward amplifier produces an output voltage equal to (VX /Rin )R0 and hence VX R0 . Rin

(12.72)

VX VX R0 = Rin Rin

(12.73)

IF = K Writing a KCL at the input node thus yields IX − K and hence

Rin VX = . IX 1 + KR0

(12.74)

That is, a feedback loop returning current to the input lowers the input impedance by a factor of one plus the loop gain, bringing the circuit closer to an ideal “current sensor.”

Example 12.19

Determine the closed-loop input impedance of the circuit studied in Example 12.18.

Solution

The open-loop amplifier shown in Fig. 12.36(b) exhibits an input impedance Rin = 1/gm1 because RF is assumed to be very large. With 1 + KR0 from the denominator of Eq. (12.71), we obtain Rin,closed =

Exercise

1 · gm1

1 . gm2 RD1 RD2 1+ RF

(12.75)

Explain what happens if RD1 → ∞ and why.

From our study of voltage-voltage feedback in Section 12.6.1, we postulate that voltage-current feedback too lowers the output impedance because a feedback loop “regulating” the output voltage tends to stabilize it despite load impedance variations. Drawing the circuit as shown in Fig. 12.38, where the input current source is set to zero and Rout models the open-loop output resistance, we observe that the feedback network produces a current of IF = KVX . Upon flowing through the forward amplifier, this current translates

542

Chapter 12 Feedback 0

VA

R0

IF

R out

IX

A

VX

K

Figure 12.38

Calculation of output impedance.

to VA = −KVX R0 and hence IX = =

VX − VA Rout

(12.76)

VX + KVX R0 , Rout

(12.77)

where the current drawn by the feedback network is neglected. Thus, VX Rout = , IX 1 + KR0

(12.78)

an expected result. Example 12.20

Calculate the closed-loop output impedance of the circuit studied in Example 12.18.

Solution

From the open-loop circuit in Fig. 12.36(b), we have Rout ≈ RD2 because RF is assumed very large. Writing 1 + KR0 from the denominator of Eq. (12.71) gives Rout,closed =

Exercise

RD2 . gm2 RD1 RD2 1+ RF

(12.79)

Explain what happens if RD1 → ∞ and why.

12.6.3 Current-Voltage Feedback Shown in Fig. 12.39(a), this topology incorporates a transconductance amplifier, requiring that the feedback network sense the output current and return a voltage to the subtractor. Again, in our terminology, the first term in “current-voltage feedback” refers to the I out Vin

Figure 12.39

Current-voltage feedback.

V1

Gm

VF

K 0

12.6 Feedback Topologies

543

quantity sensed at the output, and the second, to the quantity returned to the input. Recall from Section 12.4 that such a feedback network must appear in series with the output and with the input,10 ideally exhibiting zero input and output impedances. Note that the feedback factor in this case has a dimension of resistance because K = VF /Iout . Let us first confirm that the closed-loop gain is equal to the open-loop gain divided by one plus the loop gain. Since the forward system produces a current equal to Iout = Gm(Vin − VF ) and since VF = KI out , we have Iout = Gm(Vin − KI out )

(12.80)

Gm Iout = . Vin 1 + KGm

(12.81)

and hence

Example 12.21

We wish to deliver a well-defined current to a laser diode as shown in Fig. 12.40(a),11 but the transconductance of M1 is poorly controlled. For this reason, we “monitor” the current by inserting a small resistor RM in series, sensing the voltage across RM , and returning the result to the input of an op amp [Fig. 12.40(b)]. Estimate Iout if the op amp provides a very high gain. Calculate the closed-loop gain for the implementation shown in Fig. 12.40(c). VDD V in

M

VDD

VDD

V in

M

1

M5

1

M

M6

X

I out

I out

Laser Laser

Laser

v in

M3

M4

VF

VF

(a)

RM

I SS

RM (b)

(c)

VDD M5

M6

M

1

VDD M5

M

M6

I out

X

1

I out

X

Laser

v in

M3

M4 I SS (d)

M3

Vin

M4

VF RM

I SS (e)

Figure 12.40

10

For this reason, this type is also called “series-series” feedback. Laser diodes convert electrical signals to optical signals and are widely used in DVD players, long-distance communications, etc. 11

1

I out

544

Chapter 12 Feedback

Solution

If the gain of the op amp is very high, the difference between Vin and VF is very small. Thus, RM sustains a voltage equal to Vin and hence Iout ≈

Vin . RM

(12.82)

We now determine the open-loop gain of the transistor-level implementation in Fig. 12.40(c). The forward amplifier can be identified as shown in Fig. 12.40(d), where the gate of M4 is grounded because the feedback signal (voltage) is set to zero. Since Iout = −gm1 VX (why?) and VX = −gm3 (rO3 ||rO5 )Vin , we have Gm = gm1 gm3 (rO3 ||rO5 ). The feedback factor K = VF /Iout = RM . Thus, Iout gm1 gm3 (rO3 ||rO5 ) = . Vin closed 1 + gm1 gm3 (rO3 ||rO5 )RM Note that if the loop gain is much greater than unity, then Iout 1 ≈ . Vin closed RM

(12.83)

(12.84)

(12.85)

We must now answer two questions. First, why is the drain of M1 shorted to ground in the open-loop test? The simple answer is that, if this drain is left open, then Iout = 0! But, more fundamentally, we can observe a duality between this case and that of voltage outputs, e.g., in Fig. 12.36. If driving no load, the output port of a voltage amplifier is left open. Similarly, if driving no load, the output port of a circuit delivering a current must be shorted to ground. Second, why is the active-load amplifier in Fig. 12.40(c) drawn with the diodeconnected device on the right? This is to ensure negative feedback. For example, if Vin goes up, VX goes down (why?), M1 provides a greater current, and the voltage drop across RM rises, thereby steering a larger fraction of ISS to M4 and opposing the effect of the change in Vin . Alternatively, the circuit can be drawn as shown in Fig. 12.40(e). Exercise

Suppose Vin is a sinusoid with a peak amplitude of 100 mV. Plot VF and the current through the laser as a function of time if RM = 10 and Gm = 1/(0.5 ). Is the voltage at the gate of M1 necessarily a sinusoid?

From our analysis of other feedback topologies in Sections 12.6.1 and 12.6.2, we postulate that current-voltage feedback increases the input impedance by a factor of 1 + KGm. In fact, the test circuit shown in Fig. 12.41(a) is similar to that in Fig. 12.31—except that the forward system is denoted by Gm rather than A0 . Thus, Eq. (12.59) can be rewritten as Vin = Rin (1 + KGm). Iin

(12.86)

The output impedance is calculated using the test circuit of Fig. 12.41(b). Note that, in contrast to the cases in Figs. 12.33 and 12.38, the test voltage source is inserted in series with the output port of the forward amplifier and the input port of the feedback network. The voltage developed at port A is equal to −KI X and the current drawn by the Gm stage

12.6 Feedback Topologies I in

I

Gm

V in

Gm

A

R in

IX VF

K

KIX

(a)

Figure 12.41

X

R out

I out

545

VX

IX

K (b)

Calculation of (a) input and (b) output impedances.

equal to −KGmIX . Since the current flowing through Rout is given by VX /Rout , a KCL at the output node yields IX =

VX − KGmIX Rout

(12.87)

and hence VX = Rout (1 + KGm). IX

(12.88)

Interestingly, a negative feedback loop sensing the output current raises the output impedance, bringing the circuit closer to an ideal current generator. As in other cases studied thus far, this occurs because negative feedback tends to regulate the output quantity that it senses. Example 12.22

An alternative approach to regulating the current delivered to a laser diode is shown in Fig. 12.42(a). As in the circuit of Fig. 12.40(b), the very small resistor RM monitors the current, generating a proportional voltage and feeding it back to the subtracting device, M1 . Determine the closed-loop gain and I/O impedances of the circuit. VDD RD

VDD RD

M2 I out

X M1

I out

X M1

Laser

V in

M2

V in

VF RM

(b)

(a)

Figure 12.42

Solution

Since RM is very small, the open-loop circuit reduces to that shown in Fig. 12.42(b), where the gain can be expressed as VX Iout · Vin VX

(12.89)

= gm1 RD · gm2 .

(12.90)

Gm =

546

Chapter 12 Feedback The input impedance is equal to 1/gm1 and the output impedance equal to 1/gm2 .12 The feedback factor is equal to RM , yielding Iout gm1 gm2 RD = , Vin closed 1 + gm1 gm2 RD RM

(12.91)

which reduces to 1/RM if the loop gain is much greater than unity. The input impedance rises by a factor of 1 + GmRM : Rin,closed =

1 (1 + gm1 gm2 RD RM ), gm1

(12.92)

and so does the output impedance (i.e., that seen by the laser): Rout,closed =

1 (1 + gm1 gm2 RD RM ). gm2

(12.93)

Exercise

If an input impedance of 500 and an output impedance of 5 k are desired, determine the required values of gm1 and gm2 . Assume RD = 1 k and RM = 100 .

Example 12.23

A student attempts to calculate the output impedance of the current-voltage feedback topology with the aid of circuit depicted in Fig. 12.43. Explain why this topology is an incorrect representation of the actual circuit.

VA

IX

Gm R out

VX

K

Figure 12.43

Solution

If sensing the output current, the feedback network must remain in series with the output port of the forward amplifier, and so must the test voltage source. In other words, the output current of the forward system must be equal to both the input current of the feedback network and the current drawn by VX [as in Fig. 12.41(b)]. In the arrangement of Fig. 12.43, however, these principles are violated because VX is placed in parallel with the output.13

Exercise

Apply the above (incorrect) test to the circuit of Fig. 12.42 and examine the results.

12

To measure the output impedance, the test voltage source must be placed in series with the output wire. If the feedback network is ideal and hence has a zero input impedance, then VX must supply an infinite current. 13

12.6 Feedback Topologies

547

12.6.4 Current-Current Feedback From the analysis of the first three feedback topologies, we predict that this type lowers the gain, raises the output impedance, and lowers the input impedance, all by a factor of one plus the loop gain. Ie

I out AI

I in IF

K 0

Figure 12.44

Current-current feedback.

As shown in Fig. 12.44, current-current feedback senses the output in series and returns the signal in parallel with the input. The forward system has a current gain of AI and the feedback network a dimensionless gain of K = IF /Iout . Given by Iin − IF , the current entering the forward amplifier yields Iout = AI (Iin − IF )

(12.94)

= AI (Iin − KI out )

(12.95)

and hence Iout AI = . Iin 1 + KAI

(12.96)

The input impedance of the circuit is calculated with the aid of the arrangement depicted in Fig. 12.45. As in the case of voltage-current feedback (Fig. 12.37), the input impedance of the forward amplifier is modeled by a series resistor, Rin . Since the current flowing through Rin is equal to VX /Rin , we have Iout = AI VX /Rin and hence IF = KAI VX /Rin . A KCL at the input node therefore gives VX + IF Rin VX VX + KAI . = Rin Rin

IX =

R in IX

VX

AI

IF K

Figure 12.45

Calculation of input impedance.

I out

(12.97) (12.98)

548

Chapter 12 Feedback That is, VX Rin = . IX 1 + KAI

(12.99)

For the output impedance, we utilize the test circuit shown in Fig. 12.46, where the input is left open and VX is inserted in series with the output port. Since IF = KI X , the forward amplifier produces an output current equal to −KAI IX . Noting that Rout carries a current of VX /Rout and writing a KCL at the output node, we have VX − KAI IX . Rout

(12.100)

VX = Rout (1 + KAI ). IX

(12.101)

IX = It follows that

IX

Gm IF

VX

R out IX

IX

K

Figure 12.46

Example 12.24

Calculation of output impedance.

Consider the circuit shown in Fig. 12.47(a), where the output current delivered to a laser diode is regulated by negative feedback. Prove that the feedback is negative and compute the closed-loop gain and I/O impedances if RM is very small and RF very large.

VDD RD

I out

X Vb

M1 I in

IF

RF

(a)

Figure 12.47

VDD RD

M2

I out

X M1

Laser

P RM

M2

I in

Vb RF

(b)

Laser

12.6 Feedback Topologies Solution

549

Suppose Iin increases. Then, the source voltage of M1 tends to rise, and so does its drain voltage (why?). As a result, the overdrive of M2 decreases, Iout and hence VP fall, and IF increases, thereby lowering the source voltage of M1 . Since the feedback signal, IF , opposes the effect produced by Iin , the feedback is negative. We must now analyze the open-loop system. Since RM is very small, we assume VP remains near zero, arriving at the open-loop circuit depicted in Fig. 12.47(b). The assumption that RF is very large (1/gm1 ) indicates that almost all of Iin flows through M1 and RD , thus generating VX = Iin RD and hence Iout = −gm2 VX

(12.102)

= −gm2 RD Iin .

(12.103)

That is, AI = −gm2 RD .

(12.104)

The input impedance is approximately equal to 1/gm1 and the output impedance is equal to rO2 . To obtain the closed-loop parameters, we must compute the feedback factor, IF /Iout . Recall from Example 12.18 that the current returned by RF can be approximated as −VP /RF if RF 1/gm1 . We also note that VP = Iout RM , concluding that K= =

IF Iout

(12.105)

−VP 1 · RF Iout

(12.106)

=−

RM . RF

(12.107)

The closed-loop parameters are therefore given by: AI,closed =

Rin,closed =

Rout,closed

−gm2 RD RM 1 + gm2 RD RF 1 · gm1

1

RM RF RM . = rO2 1 + gm2 RD RF

(12.108)

(12.109)

1 + gm2 RD

(12.110)

Note that if gm2 RD RM /RF 1, then the closed-loop gain is simply given by −RF /RM . Exercise

Noting that Rout |closed is the impedance seen by the laser in the closed-loop circuit, construct a Norton equivalent for the entire circuit that drives the laser.

550

Chapter 12 Feedback AI

Vout

A0

K

K

Output impedance falls by 1+ loop gain.

Output impedance rises by 1+ loop gain.

V in

AI

A0 I in

IF

K

K Input impedance rises by 1+ loop gain.

Figure 12.48

I out

Input impedance falls by 1+ loop gain.

Effect of feedback on input and output impedances.

The effect of feedback on the input and output impedances of the forward amplifier is summarized in Fig. 12.48.

12.7

EFFECT OF NONIDEAL I/O IMPEDANCES Our study of feedback topologies in Section 12.6 has been based on idealized models for the feedback network, always assuming that the I/O impedances of this network are very large or very small depending on the type of feedback. In practice, however, the finite I/O impedances of the feedback network may considerably alter the performance of the circuit, thereby necessitating analysis techniques to account for these effects. In such cases, we say the feedback network “loads” the forward amplifier and the “loading effects” must be determined. Before delving into the analysis, it is instructive to understand the difficulty in the context of an example.

Example 12.25

Suppose in the circuit of Example 12.7, R1 + R2 is not much greater than RD . How should we analyze the circuit?

Solution

In Example 12.7, we constructed the open-loop circuit by simply neglecting the effect of R1 + R2 . Here, on the other hand, R1 + R2 tends to reduce the open-loop gain because it appears in parallel with RD . We therefore surmise that the open-loop circuit must be configured as shown in Fig. 12.49, with the open-loop gain given by AO = gm1 [RD ||(R1 + R2 )],

(12.111)

Rout,open = RD ||(R1 + R2 ).

(12.112)

and the output impedance

12.7 Effect of Nonideal I/O Impedances

551

VDD RD Vout R1 M1 V in

R2

Figure 12.49

Other forward and feedback parameters are identical to those calculated in Example 12.7. Thus, gm1 [RD ||(R1 + R2 )] R2 1+ gm1 [RD ||(R1 + R2 )] R1 + R 2 R2 1 1+ = gm1 [RD ||(R1 + R2 )] gm1 R1 + R 2

Av,closed =

(12.113)

Rin,closed

(12.114)

Rout,closed =

Exercise

RD ||(R1 + R2 ) 1+

R2 gm1 [RD ||(R1 + R2 )] R1 + R 2

.

(12.115)

Repeat the above example if RD is replaced with an ideal current source.

The above example easily lends itself to intuitive inspection. But many other circuits do not. To gain more confidence in our analysis and deal with more complex circuits, we must develop a systematic approach.

12.7.1 Inclusion of I/O Effects We present a methodology here that allows the analysis of the four feedback topologies even if the I/O impedances of the forward amplifier or the feedback network depart from their ideal values. The methodology is based on a formal proof that is somewhat beyond the scope of this book and can be found in [1]. Our methodology proceeds in six steps: 1. 2. 3. 4. 5. 6.

Identify the forward amplifier. Identify the feedback network. Break the feedback network according to the rules described below. Calculate the open-loop parameters. Determine the feedback factor according to the rules described below. Calculate the closed-loop parameters.

Rules for Breaking the Feedback Network The third step is carried out by “duplicating” the feedback network at both the input and the output of the overall system.

552

Chapter 12 Feedback X

Y

A1

K

? ?

K

Return Duplicate

Figure 12.50

Sense Duplicate

Method of breaking the feedback loop.

Illustrated in Fig. 12.50, the idea is to “load” both the input and the output of the forward amplifier by proper copies of the feedback network. The copy tied to the output is called the “sense duplicate” and that connected to the input, the “return duplicate.” We must also decide what to do with the output port of the former and the input port of the latter, i.e., whether to short or open these ports. This is accomplished through the use of the “termination” rules depicted in Fig. 12.51. For example, for voltage-voltage feedback [Fig. 12.51(a)], the output port of the sense replica is left open while the input of the return duplicate is shorted. Similarly, for voltage-current feedback [Fig. 12.51(b)], both the output port of the sense duplicate and the input port of the return duplicate are shorted. The formal proof of these concepts is given in [1] but it is helpful to remember these rules based on the following intuitive (but not quite rigorous) observations. In an ideal situation, a feedback network sensing an output voltage is driven by a zero impedance, namely, the output impedance of the forward amplifier. Thus, the input port of the return duplicate is shorted. Moreover, a feedback network returning a voltage to the input ideally sees an infinite impedance, namely, the input impedance of the forward amplifier. Thus, the output port of the sense duplicate is left open. Similar observations apply to the other three cases.

V in

R0

Vout

A0

I in

K

Open

K

IF

K

(a)

K (b)

Gm

V in

AI I in

Vout

I out

IF

K

Open (c)

K

I out

K

Open Open (d)

Proper termination of duplicates in (a) voltage-voltage, (b) voltagecurrent, (c) current-current, and (d) current-voltage feedback.

Figure 12.51

K

12.7 Effect of Nonideal I/O Impedances K

K V1

V2

K=

K V1

I2

V2

K=

V1

(a)

K I1

I2

I2

K=

V1

(b)

553

I1

V2

I2

K=

I1

(c)

V2 I1

(d)

Calculation of feedback factor for (a) voltage-voltage, (b) voltage-current, (c) current-current, and (d) current-voltage feedback.

Figure 12.52

Calculation of Feedback Factor The fifth step entails the calculation of the feedback factor, a task requiring the rules illustrated in Fig. 12.52. Depending on the type of feedback, the output port of the feedback network is shorted or opened, and the ratio of the output current or voltage to the input is defined as the feedback factor. For example, in a voltagevoltage feedback topology, the output port of the feedback network is open [Fig. 12.52(a)] and K = V2 /V1 . The proof of these rules is provided in [1], but an intuitive view can also be developed. First, the stimulus (voltage or current) applied to the input of the feedback network is of the same type as the quantity sensed at the output of the forward amplifier. Second, the output port of the feedback network is opened (shorted) if the returned quantity is a voltage (current)—just as in the case of the sense duplicates in Fig. 12.51. Of course, if the output port of the feedback network is left open, the quantity of interest is a voltage, V2 . Similarly,